freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
This commit is contained in:
Rob Clark
parent
9450bd56be
commit
21ceedfd8b
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@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14748 bytes, from 2015-04-12 15:01:13)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14895 bytes, from 2015-04-19 15:23:28)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-04-12 18:16:35)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 57486 bytes, from 2015-04-12 18:10:00)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 59314 bytes, from 2015-04-19 16:21:40)
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Copyright (C) 2013-2014 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14748 bytes, from 2015-04-12 15:01:13)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14895 bytes, from 2015-04-19 15:23:28)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-04-12 18:16:35)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 57486 bytes, from 2015-04-12 18:10:00)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 59314 bytes, from 2015-04-19 16:21:40)
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Copyright (C) 2013-2015 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14748 bytes, from 2015-04-12 15:01:13)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14895 bytes, from 2015-04-19 15:23:28)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-04-12 18:16:35)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 57486 bytes, from 2015-04-12 18:10:00)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 59314 bytes, from 2015-04-19 16:21:40)
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Copyright (C) 2013-2015 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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@ -229,6 +229,12 @@ enum a4xx_depth_format {
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DEPTH4_24_8 = 2,
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};
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enum a4xx_tess_spacing {
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EQUAL_SPACING = 0,
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ODD_SPACING = 2,
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EVEN_SPACING = 3,
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};
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enum a4xx_tex_filter {
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A4XX_TEX_NEAREST = 0,
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A4XX_TEX_LINEAR = 1,
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@ -1440,6 +1446,14 @@ static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
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return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
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}
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#define REG_A4XX_SP_HS_OBJ_START 0x0000230e
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#define REG_A4XX_SP_HS_PVT_MEM_PARAM 0x0000230f
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#define REG_A4XX_SP_HS_PVT_MEM_ADDR 0x00002310
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#define REG_A4XX_SP_HS_LENGTH_REG 0x00002312
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#define REG_A4XX_SP_DS_OBJ_OFFSET_REG 0x00002334
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#define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
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#define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
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@ -1454,6 +1468,14 @@ static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
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return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
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}
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#define REG_A4XX_SP_DS_OBJ_START 0x00002335
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#define REG_A4XX_SP_DS_PVT_MEM_PARAM 0x00002336
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#define REG_A4XX_SP_DS_PVT_MEM_ADDR 0x00002337
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#define REG_A4XX_SP_DS_LENGTH_REG 0x00002339
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#define REG_A4XX_SP_GS_OBJ_OFFSET_REG 0x0000235b
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#define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
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#define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
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@ -1740,6 +1762,44 @@ static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
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#define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380
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#define REG_A4XX_TPL1_TP_TEX_COUNT 0x00002381
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#define A4XX_TPL1_TP_TEX_COUNT_VS__MASK 0x000000ff
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#define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT 0
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static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val)
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{
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return ((val) << A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_VS__MASK;
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}
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#define A4XX_TPL1_TP_TEX_COUNT_HS__MASK 0x0000ff00
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#define A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT 8
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static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val)
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{
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return ((val) << A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_HS__MASK;
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}
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#define A4XX_TPL1_TP_TEX_COUNT_DS__MASK 0x00ff0000
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#define A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT 16
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static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val)
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{
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return ((val) << A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_DS__MASK;
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}
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#define A4XX_TPL1_TP_TEX_COUNT_GS__MASK 0xff000000
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#define A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT 24
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static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val)
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{
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return ((val) << A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_GS__MASK;
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}
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#define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002384
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#define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR 0x00002387
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#define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR 0x0000238a
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#define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR 0x0000238d
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#define REG_A4XX_TPL1_TP_FS_TEX_COUNT 0x000023a0
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#define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x000023a1
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#define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR 0x000023a6
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#define REG_A4XX_GRAS_TSE_STATUS 0x00000c80
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@ -2057,7 +2117,12 @@ static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK;
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}
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#define A4XX_HLSQ_CONTROL_1_REG_ZWCOORD 0x02000000
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#define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK 0xff000000
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#define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT 24
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static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK;
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}
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#define REG_A4XX_HLSQ_CONTROL_2_REG 0x000023c2
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#define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000
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@ -2106,6 +2171,7 @@ static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
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}
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#define A4XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00010000
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#define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
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#define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
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static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
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@ -2132,6 +2198,7 @@ static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
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}
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#define A4XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00010000
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#define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
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#define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
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static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
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@ -2158,6 +2225,7 @@ static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
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}
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#define A4XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00010000
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#define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
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#define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
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static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
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@ -2184,6 +2252,7 @@ static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
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}
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#define A4XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00010000
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#define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
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#define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
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static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
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@ -2210,6 +2279,7 @@ static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
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}
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#define A4XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00010000
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#define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
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#define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
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static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
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@ -2243,6 +2313,7 @@ static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val)
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{
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return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK;
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}
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#define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000
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#define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000
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#define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000
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@ -2257,14 +2328,39 @@ static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
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{
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return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK;
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}
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#define A4XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800
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#define A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11
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static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val)
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{
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return ((val) << A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A4XX_PC_GS_PARAM_INVOCATIONS__MASK;
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}
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#define A4XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000
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#define A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23
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static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
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{
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return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK;
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}
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#define A4XX_PC_GS_PARAM_LAYER 0x80000000
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#define REG_A4XX_PC_HS_PARAM 0x000021e7
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#define A4XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f
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#define A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0
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static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val)
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{
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return ((val) << A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A4XX_PC_HS_PARAM_VERTICES_OUT__MASK;
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}
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#define A4XX_PC_HS_PARAM_SPACING__MASK 0x00600000
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#define A4XX_PC_HS_PARAM_SPACING__SHIFT 21
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static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
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{
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return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK;
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}
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#define A4XX_PC_HS_PARAM_PRIMTYPE__MASK 0x01800000
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#define A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT 23
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static inline uint32_t A4XX_PC_HS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
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{
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return ((val) << A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_HS_PARAM_PRIMTYPE__MASK;
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}
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#define REG_A4XX_VBIF_VERSION 0x00003000
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@ -2343,10 +2439,6 @@ static inline uint32_t A4XX_UNKNOWN_20F7(float val)
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#define REG_A4XX_UNKNOWN_22D7 0x000022d7
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#define REG_A4XX_UNKNOWN_2381 0x00002381
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#define REG_A4XX_UNKNOWN_23A0 0x000023a0
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#define REG_A4XX_TEX_SAMP_0 0x00000000
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#define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
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#define A4XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
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@ -701,11 +701,14 @@ fd4_emit_restore(struct fd_context *ctx)
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OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_OFFSET, 1);
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OUT_RING(ring, 0x00000000);
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OUT_PKT0(ring, REG_A4XX_UNKNOWN_2381, 1);
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OUT_RING(ring, 0x00000010);
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OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_COUNT, 1);
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OUT_RING(ring, A4XX_TPL1_TP_TEX_COUNT_VS(16) |
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A4XX_TPL1_TP_TEX_COUNT_HS(0) |
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A4XX_TPL1_TP_TEX_COUNT_DS(0) |
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A4XX_TPL1_TP_TEX_COUNT_GS(0));
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OUT_PKT0(ring, REG_A4XX_UNKNOWN_23A0, 1);
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OUT_RING(ring, 0x00000010);
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OUT_PKT0(ring, REG_A4XX_TPL1_TP_FS_TEX_COUNT, 1);
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OUT_RING(ring, 16);
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/* we don't use this yet.. probably best to disable.. */
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OUT_PKT3(ring, CP_SET_DRAW_STATE, 2);
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@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14748 bytes, from 2015-04-12 15:01:13)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14895 bytes, from 2015-04-19 15:23:28)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-04-12 18:16:35)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 57486 bytes, from 2015-04-12 18:10:00)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 59314 bytes, from 2015-04-19 16:21:40)
|
||||
|
||||
Copyright (C) 2013-2014 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
|
|
|||
|
|
@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are:
|
|||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14748 bytes, from 2015-04-12 15:01:13)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14895 bytes, from 2015-04-19 15:23:28)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-04-12 18:16:35)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 57486 bytes, from 2015-04-12 18:10:00)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 59314 bytes, from 2015-04-19 16:21:40)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
|
@ -80,6 +80,7 @@ enum pc_di_primtype {
|
|||
DI_PT_LINESTRIP_ADJ = 11,
|
||||
DI_PT_TRI_ADJ = 12,
|
||||
DI_PT_TRISTRIP_ADJ = 13,
|
||||
DI_PT_PATCHES = 34,
|
||||
};
|
||||
|
||||
enum pc_di_src_sel {
|
||||
|
|
@ -377,12 +378,19 @@ static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel va
|
|||
{
|
||||
return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
|
||||
}
|
||||
#define CP_DRAW_INDX_OFFSET_0_TESSELLATE 0x00000100
|
||||
#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00
|
||||
#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10
|
||||
static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
|
||||
}
|
||||
#define CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK 0x01f00000
|
||||
#define CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT 20
|
||||
static inline uint32_t CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT) & CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_DRAW_INDX_OFFSET_1 0x00000001
|
||||
#define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK 0xffffffff
|
||||
|
|
|
|||
Loading…
Reference in New Issue