nir: split fuse_ffma into fuse_ffma16/32/64
AMD wants different behavior for each bit size Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6756>
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@ -3056,7 +3056,9 @@ typedef enum {
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typedef struct nir_shader_compiler_options {
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typedef struct nir_shader_compiler_options {
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bool lower_fdiv;
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bool lower_fdiv;
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bool lower_ffma;
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bool lower_ffma;
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bool fuse_ffma;
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bool fuse_ffma16;
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bool fuse_ffma32;
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bool fuse_ffma64;
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bool lower_flrp16;
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bool lower_flrp16;
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bool lower_flrp32;
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bool lower_flrp32;
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/** Lowers flrp when it does not support doubles */
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/** Lowers flrp when it does not support doubles */
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@ -195,7 +195,9 @@ optimizations.extend([
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(('fceil', a), ('fneg', ('ffloor', ('fneg', a))), 'options->lower_fceil'),
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(('fceil', a), ('fneg', ('ffloor', ('fneg', a))), 'options->lower_fceil'),
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(('ffma', a, b, c), ('fadd', ('fmul', a, b), c), 'options->lower_ffma'),
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(('ffma', a, b, c), ('fadd', ('fmul', a, b), c), 'options->lower_ffma'),
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# Always lower inexact ffma, because it will be fused back by late optimizations (nir_opt_algebraic_late).
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# Always lower inexact ffma, because it will be fused back by late optimizations (nir_opt_algebraic_late).
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(('~ffma', a, b, c), ('fadd', ('fmul', a, b), c), 'options->fuse_ffma'),
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(('~ffma@16', a, b, c), ('fadd', ('fmul', a, b), c), 'options->fuse_ffma16'),
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(('~ffma@32', a, b, c), ('fadd', ('fmul', a, b), c), 'options->fuse_ffma32'),
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(('~ffma@64', a, b, c), ('fadd', ('fmul', a, b), c), 'options->fuse_ffma64'),
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(('~fmul', ('fadd', ('iand', ('ineg', ('b2i', 'a@bool')), ('fmul', b, c)), '#d'), '#e'),
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(('~fmul', ('fadd', ('iand', ('ineg', ('b2i', 'a@bool')), ('fmul', b, c)), '#d'), '#e'),
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('bcsel', a, ('fmul', ('fadd', ('fmul', b, c), d), e), ('fmul', d, e))),
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('bcsel', a, ('fmul', ('fadd', ('fmul', b, c), d), e), ('fmul', d, e))),
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@ -2028,7 +2030,9 @@ late_optimizations = [
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(('fneg', a), ('fsub', 0.0, a), 'options->lower_negate'),
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(('fneg', a), ('fsub', 0.0, a), 'options->lower_negate'),
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(('ineg', a), ('isub', 0, a), 'options->lower_negate'),
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(('ineg', a), ('isub', 0, a), 'options->lower_negate'),
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(('iabs', a), ('imax', a, ('ineg', a)), 'options->lower_iabs'),
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(('iabs', a), ('imax', a, ('ineg', a)), 'options->lower_iabs'),
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(('~fadd', ('fmul', a, b), c), ('ffma', a, b, c), 'options->fuse_ffma'),
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(('~fadd@16', ('fmul', a, b), c), ('ffma', a, b, c), 'options->fuse_ffma16'),
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(('~fadd@32', ('fmul', a, b), c), ('ffma', a, b, c), 'options->fuse_ffma32'),
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(('~fadd@64', ('fmul', a, b), c), ('ffma', a, b, c), 'options->fuse_ffma64'),
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# These are duplicated from the main optimizations table. The late
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# These are duplicated from the main optimizations table. The late
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# patterns that rearrange expressions like x - .5 < 0 to x < .5 can create
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# patterns that rearrange expressions like x - .5 < 0 to x < .5 can create
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@ -47,7 +47,9 @@ static const nir_shader_compiler_options options = {
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.lower_usub_borrow = true,
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.lower_usub_borrow = true,
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.lower_mul_high = true,
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.lower_mul_high = true,
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.lower_mul_2x32_64 = true,
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.lower_mul_2x32_64 = true,
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.fuse_ffma = true,
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.fuse_ffma16 = true,
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.fuse_ffma32 = true,
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.fuse_ffma64 = true,
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.vertex_id_zero_based = true,
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.vertex_id_zero_based = true,
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.lower_extract_byte = true,
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.lower_extract_byte = true,
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.lower_extract_word = true,
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.lower_extract_word = true,
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@ -97,7 +99,9 @@ static const nir_shader_compiler_options options_a6xx = {
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.lower_usub_borrow = true,
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.lower_usub_borrow = true,
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.lower_mul_high = true,
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.lower_mul_high = true,
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.lower_mul_2x32_64 = true,
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.lower_mul_2x32_64 = true,
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.fuse_ffma = true,
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.fuse_ffma16 = true,
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.fuse_ffma32 = true,
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.fuse_ffma64 = true,
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.vertex_id_zero_based = false,
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.vertex_id_zero_based = false,
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.lower_extract_byte = true,
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.lower_extract_byte = true,
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.lower_extract_word = true,
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.lower_extract_word = true,
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@ -1004,7 +1004,9 @@ etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu,
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.lower_fpow = true,
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.lower_fpow = true,
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.lower_sub = true,
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.lower_sub = true,
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.lower_ftrunc = true,
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.lower_ftrunc = true,
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.fuse_ffma = true,
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.fuse_ffma16 = true,
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.fuse_ffma32 = true,
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.fuse_ffma64 = true,
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.lower_bitops = true,
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.lower_bitops = true,
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.lower_all_io_to_temps = true,
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.lower_all_io_to_temps = true,
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.vertex_id_zero_based = true,
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.vertex_id_zero_based = true,
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@ -35,7 +35,9 @@ static const nir_shader_compiler_options options = {
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.lower_fmod = true,
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.lower_fmod = true,
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.lower_fdiv = true,
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.lower_fdiv = true,
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.lower_fceil = true,
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.lower_fceil = true,
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.fuse_ffma = true,
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.fuse_ffma16 = true,
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.fuse_ffma32 = true,
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.fuse_ffma64 = true,
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/* .fdot_replicates = true, it is replicated, but it makes things worse */
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/* .fdot_replicates = true, it is replicated, but it makes things worse */
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.lower_all_io_to_temps = true,
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.lower_all_io_to_temps = true,
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.vertex_id_zero_based = true, /* its not implemented anyway */
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.vertex_id_zero_based = true, /* its not implemented anyway */
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@ -3207,7 +3207,9 @@ nvir_nir_shader_compiler_options(int chipset)
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nir_shader_compiler_options op = {};
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nir_shader_compiler_options op = {};
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op.lower_fdiv = (chipset >= NVISA_GV100_CHIPSET);
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op.lower_fdiv = (chipset >= NVISA_GV100_CHIPSET);
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op.lower_ffma = false;
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op.lower_ffma = false;
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op.fuse_ffma = false; /* nir doesn't track mad vs fma */
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op.fuse_ffma16 = false; /* nir doesn't track mad vs fma */
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op.fuse_ffma32 = false; /* nir doesn't track mad vs fma */
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op.fuse_ffma64 = false; /* nir doesn't track mad vs fma */
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op.lower_flrp16 = (chipset >= NVISA_GV100_CHIPSET);
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op.lower_flrp16 = (chipset >= NVISA_GV100_CHIPSET);
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op.lower_flrp32 = true;
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op.lower_flrp32 = true;
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op.lower_flrp64 = true;
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op.lower_flrp64 = true;
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@ -923,7 +923,9 @@ int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
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}
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}
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static const nir_shader_compiler_options nir_options = {
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static const nir_shader_compiler_options nir_options = {
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.fuse_ffma = false, /* nir doesn't track mad vs fma */
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.fuse_ffma16 = false, /* nir doesn't track mad vs fma */
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.fuse_ffma32 = false, /* nir doesn't track mad vs fma */
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.fuse_ffma64 = false, /* nir doesn't track mad vs fma */
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.lower_flrp32 = true,
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.lower_flrp32 = true,
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.lower_flrp64 = true,
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.lower_flrp64 = true,
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.lower_fpow = false,
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.lower_fpow = false,
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@ -1179,7 +1179,9 @@ struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
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}
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}
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const struct nir_shader_compiler_options r600_nir_fs_options = {
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const struct nir_shader_compiler_options r600_nir_fs_options = {
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.fuse_ffma = true,
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.fuse_ffma16 = true,
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.fuse_ffma32 = true,
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.fuse_ffma64 = true,
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.lower_scmp = true,
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.lower_scmp = true,
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.lower_flrp32 = true,
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.lower_flrp32 = true,
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.lower_flrp64 = true,
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.lower_flrp64 = true,
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@ -1203,7 +1205,9 @@ const struct nir_shader_compiler_options r600_nir_fs_options = {
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};
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};
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const struct nir_shader_compiler_options r600_nir_options = {
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const struct nir_shader_compiler_options r600_nir_options = {
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.fuse_ffma = true,
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.fuse_ffma16 = true,
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.fuse_ffma32 = true,
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.fuse_ffma64 = true,
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.lower_scmp = true,
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.lower_scmp = true,
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.lower_flrp32 = true,
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.lower_flrp32 = true,
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.lower_flrp64 = true,
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.lower_flrp64 = true,
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@ -946,7 +946,9 @@ void si_init_screen_get_functions(struct si_screen *sscreen)
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* for gfx10.3 on gfx10.
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* for gfx10.3 on gfx10.
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*/
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*/
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.lower_ffma = sscreen->info.chip_class <= GFX9,
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.lower_ffma = sscreen->info.chip_class <= GFX9,
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.fuse_ffma = sscreen->info.chip_class >= GFX10,
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.fuse_ffma16 = sscreen->info.chip_class >= GFX10,
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.fuse_ffma32 = sscreen->info.chip_class >= GFX10,
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.fuse_ffma64 = sscreen->info.chip_class >= GFX10,
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.lower_fmod = true,
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.lower_fmod = true,
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.lower_pack_snorm_4x8 = true,
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.lower_pack_snorm_4x8 = true,
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.lower_pack_unorm_4x8 = true,
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.lower_pack_unorm_4x8 = true,
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@ -69,7 +69,9 @@ static const nir_shader_compiler_options bifrost_nir_options = {
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.lower_bitfield_extract_to_shifts = true,
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.lower_bitfield_extract_to_shifts = true,
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.vectorize_io = true,
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.vectorize_io = true,
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.fuse_ffma = true,
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.fuse_ffma16 = true,
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.fuse_ffma32 = true,
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.fuse_ffma64 = true,
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.use_interpolated_input_intrinsics = true
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.use_interpolated_input_intrinsics = true
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};
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};
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