freedreno/ir3: fix up cat6 instruction encodings
I think there is at least one more sub-encoding, but these two should be enough to cover the common load/store instructions. Signed-off-by: Rob Clark <robclark@freedesktop.org>
This commit is contained in:
Rob Clark
parent
4abb789bca
commit
20b50a0712
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@ -448,117 +448,114 @@ static void print_instr_cat5(instr_t *instr)
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}
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}
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static int32_t u2i(uint32_t val, int nbits)
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{
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return ((val >> (nbits-1)) * ~((1 << nbits) - 1)) | val;
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}
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static void print_instr_cat6(instr_t *instr)
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{
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instr_cat6_t *cat6 = &instr->cat6;
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char sd = 0, ss = 0; /* dst/src address space */
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bool full = type_size(cat6->type) == 32;
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bool nodst = false;
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printf(".%s ", type[cat6->type]);
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switch (cat6->opc) {
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case OPC_STG:
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sd = 'g';
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break;
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case OPC_STP:
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sd = 'p';
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break;
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case OPC_STL:
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case OPC_STLW:
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sd = 'l';
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break;
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case OPC_LDG:
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ss = 'g';
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break;
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case OPC_LDP:
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ss = 'p';
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break;
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case OPC_LDL:
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case OPC_LDLW:
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case OPC_LDLV:
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/* load instructions: */
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print_reg_dst((reg_t)(cat6->a.dst), type_size(cat6->type) == 32, false);
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printf(",");
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switch (cat6->opc) {
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case OPC_LDG:
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printf("g");
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break;
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case OPC_LDP:
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printf("p");
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break;
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case OPC_LDL:
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case OPC_LDLW:
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case OPC_LDLV:
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printf("l");
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break;
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}
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printf("[");
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print_reg_src((reg_t)(cat6->a.src), true,
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false, false, false, false, false, false);
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if (cat6->a.off)
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printf("%+d", cat6->a.off);
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printf("]");
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ss = 'l';
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break;
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case OPC_PREFETCH:
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/* similar to load instructions: */
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printf("g[");
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print_reg_src((reg_t)(cat6->a.src), true,
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false, false, false, false, false, false);
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if (cat6->a.off)
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printf("%+d", cat6->a.off);
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printf("]");
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break;
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case OPC_STG:
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case OPC_STP:
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case OPC_STL:
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case OPC_STLW:
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/* store instructions: */
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switch (cat6->opc) {
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case OPC_STG:
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printf("g");
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break;
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case OPC_STP:
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printf("p");
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break;
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case OPC_STL:
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case OPC_STLW:
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printf("l");
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break;
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}
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printf("[");
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print_reg_dst((reg_t)(cat6->b.dst), true, false);
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if (cat6->b.off || cat6->b.off_hi)
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printf("%+d", u2i((cat6->b.off_hi << 8) | cat6->b.off, 13));
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printf("]");
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printf(",");
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print_reg_src((reg_t)(cat6->b.src), type_size(cat6->type) == 32,
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false, false, false, false, false, false);
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case OPC_L2G:
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ss = 'l';
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sd = 'g';
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break;
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case OPC_G2L:
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ss = 'g';
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sd = 'l';
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break;
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case OPC_PREFETCH:
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ss = 'g';
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nodst = true;
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break;
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case OPC_STI:
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/* sti has same encoding as other store instructions, but
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* slightly different syntax:
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*/
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print_reg_dst((reg_t)(cat6->b.dst), false /* XXX is it always half? */, false);
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if (cat6->b.off || cat6->b.off_hi)
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printf("%+d", u2i((cat6->b.off_hi << 8) | cat6->b.off, 13));
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printf(",");
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print_reg_src((reg_t)(cat6->b.src), type_size(cat6->type) == 32,
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false, false, false, false, false, false);
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full = false; // XXX or inverts??
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break;
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}
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printf(", %d", cat6->iim_val);
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if (cat6->has_off) {
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if (!nodst) {
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if (sd)
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printf("%c[", sd);
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print_reg_dst((reg_t)(cat6->a.dst), full, false);
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if (sd)
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printf("]");
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printf(", ");
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}
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if (ss)
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printf("%c[", ss);
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print_reg_src((reg_t)(cat6->a.src1), true,
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false, false, cat6->a.src1_im, false, false, false);
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printf("%+d", cat6->a.off);
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if (ss)
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printf("]");
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printf(", ");
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print_reg_src((reg_t)(cat6->a.src2), full,
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false, false, cat6->a.src2_im, false, false, false);
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} else {
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if (!nodst) {
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if (sd)
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printf("%c[", sd);
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print_reg_dst((reg_t)(cat6->b.dst), full, false);
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if (sd)
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printf("]");
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printf(", ");
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}
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if (ss)
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printf("%c[", ss);
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print_reg_src((reg_t)(cat6->b.src1), true,
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false, false, cat6->b.src1_im, false, false, false);
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if (ss)
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printf("]");
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printf(", ");
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print_reg_src((reg_t)(cat6->b.src2), full,
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false, false, cat6->b.src2_im, false, false, false);
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}
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if (debug & PRINT_VERBOSE) {
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switch (cat6->opc) {
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case OPC_LDG:
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case OPC_LDP:
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/* load instructions: */
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if (cat6->a.dummy1|cat6->a.dummy2|cat6->a.dummy3)
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printf("\t{6: %x,%x,%x}", cat6->a.dummy1, cat6->a.dummy2, cat6->a.dummy3);
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if ((cat6->a.must_be_one1 != 1) || (cat6->a.must_be_one2 != 1))
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printf("{?? %d,%d ??}", cat6->a.must_be_one1, cat6->a.must_be_one2);
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if (cat6->a.dummy2|cat6->a.dummy3)
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printf("\t{6: %x,%x}", cat6->a.dummy2, cat6->a.dummy3);
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break;
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case OPC_STG:
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case OPC_STP:
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case OPC_STI:
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/* store instructions: */
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if (cat6->b.dummy1|cat6->b.dummy2)
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printf("\t{6: %x,%x}", cat6->b.dummy1, cat6->b.dummy2);
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if ((cat6->b.must_be_one1 != 1) || (cat6->b.must_be_one2 != 1) ||
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(cat6->b.must_be_zero1 != 0))
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printf("{?? %d,%d,%d ??}", cat6->b.must_be_one1, cat6->b.must_be_one2,
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cat6->b.must_be_zero1);
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if (cat6->b.dummy2|cat6->b.dummy2)
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printf("\t{6: %x,%x}", cat6->b.dummy2, cat6->b.dummy3);
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if (cat6->b.ignore0)
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printf("\t{?? %x}", cat6->b.ignore0);
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break;
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}
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}
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@ -572,15 +572,15 @@ typedef struct PACKED {
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uint32_t opc_cat : 3;
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} instr_cat5_t;
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/* used for load instructions: */
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/* [src1 + off], src2: */
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typedef struct PACKED {
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/* dword0: */
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uint32_t must_be_one1 : 1;
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int16_t off : 13;
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uint32_t src : 8;
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uint32_t dummy1 : 1;
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uint32_t must_be_one2 : 1;
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int32_t iim_val : 8;
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uint32_t mustbe1 : 1;
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int32_t off : 13;
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uint32_t src1 : 8;
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uint32_t src1_im : 1;
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uint32_t src2_im : 1;
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uint32_t src2 : 8;
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/* dword1: */
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uint32_t dst : 8;
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@ -593,35 +593,38 @@ typedef struct PACKED {
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uint32_t opc_cat : 3;
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} instr_cat6a_t;
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/* used for store instructions: */
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/* [src1], src2: */
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typedef struct PACKED {
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/* dword0: */
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uint32_t must_be_zero1 : 1;
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uint32_t src : 8;
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uint32_t off_hi : 5; /* high bits of 'off'... ugly! */
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uint32_t dummy1 : 9;
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uint32_t must_be_one1 : 1;
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int32_t iim_val : 8;
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uint32_t mustbe0 : 1;
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uint32_t src1 : 8;
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uint32_t ignore0 : 13;
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uint32_t src1_im : 1;
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uint32_t src2_im : 1;
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uint32_t src2 : 8;
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/* dword1: */
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uint16_t off : 8;
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uint32_t must_be_one2 : 1;
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uint32_t dst : 8;
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uint32_t dummy2 : 9;
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uint32_t type : 3;
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uint32_t dummy2 : 2;
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uint32_t dummy3 : 2;
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uint32_t opc : 5;
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uint32_t jmp_tgt : 1;
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uint32_t sync : 1;
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uint32_t opc_cat : 3;
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} instr_cat6b_t;
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/* I think some of the other cat6 instructions use additional
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* sub-encodings..
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*/
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typedef union PACKED {
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instr_cat6a_t a;
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instr_cat6b_t b;
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struct PACKED {
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/* dword0: */
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uint32_t pad1 : 24;
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int32_t iim_val : 8;
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uint32_t has_off : 1;
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uint32_t pad1 : 31;
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/* dword1: */
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uint32_t pad2 : 17;
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@ -474,58 +474,40 @@ static int emit_cat5(struct ir3_instruction *instr, void *ptr,
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static int emit_cat6(struct ir3_instruction *instr, void *ptr,
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struct ir3_info *info)
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{
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struct ir3_register *dst = instr->regs[0];
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struct ir3_register *src = instr->regs[1];
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struct ir3_register *dst = instr->regs[0];
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struct ir3_register *src1 = instr->regs[1];
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struct ir3_register *src2 = (instr->regs_count >= 3) ? instr->regs[2] : NULL;
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instr_cat6_t *cat6 = ptr;
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iassert(instr->regs_count == 2);
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iassert(instr->regs_count >= 2);
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switch (instr->opc) {
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/* load instructions: */
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case OPC_LDG:
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case OPC_LDP:
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case OPC_LDL:
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case OPC_LDLW:
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case OPC_LDLV:
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case OPC_PREFETCH: {
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if (instr->cat6.offset) {
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instr_cat6a_t *cat6a = ptr;
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iassert(!((dst->flags ^ type_flags(instr->cat6.type)) & IR3_REG_HALF));
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cat6->has_off = true;
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cat6a->must_be_one1 = 1;
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cat6a->must_be_one2 = 1;
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cat6a->off = instr->cat6.offset;
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cat6a->src = reg(src, info, instr->repeat, 0);
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cat6a->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
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break;
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}
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/* store instructions: */
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case OPC_STG:
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case OPC_STP:
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case OPC_STL:
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case OPC_STLW:
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case OPC_STI: {
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cat6a->src1 = reg(src1, info, instr->repeat, IR3_REG_IMMED);
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cat6a->src1_im = !!(src1->flags & IR3_REG_IMMED);
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if (src2) {
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cat6a->src2 = reg(src2, info, instr->repeat, IR3_REG_IMMED);
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cat6a->src2_im = !!(src2->flags & IR3_REG_IMMED);
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}
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cat6a->off = instr->cat6.offset;
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} else {
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instr_cat6b_t *cat6b = ptr;
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uint32_t src_flags = type_flags(instr->cat6.type);
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uint32_t dst_flags = (instr->opc == OPC_STI) ? IR3_REG_HALF : 0;
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iassert(!((src->flags ^ src_flags) & IR3_REG_HALF));
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cat6->has_off = false;
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cat6b->must_be_one1 = 1;
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cat6b->must_be_one2 = 1;
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cat6b->src = reg(src, info, instr->repeat, src_flags);
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cat6b->off_hi = instr->cat6.offset >> 8;
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cat6b->off = instr->cat6.offset;
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cat6b->dst = reg(dst, info, instr->repeat, IR3_REG_R | dst_flags);
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break;
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}
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default:
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// TODO
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break;
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cat6b->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
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cat6b->src1 = reg(src1, info, instr->repeat, IR3_REG_IMMED);
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cat6b->src1_im = !!(src1->flags & IR3_REG_IMMED);
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if (src2) {
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cat6b->src2 = reg(src2, info, instr->repeat, IR3_REG_IMMED);
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cat6b->src2_im = !!(src2->flags & IR3_REG_IMMED);
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}
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}
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cat6->iim_val = instr->cat6.iim_val;
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cat6->type = instr->cat6.type;
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cat6->opc = instr->opc;
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cat6->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
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