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pvr: Add helper macros for creating pvr_dev_addr_t instances 

The two macros introduced here form a (hopefully) unobjectionable
subset of those added in !17203.

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17488>
This commit is contained in:
Matt Coster 2022-07-12 13:37:43 +01:00
parent 282f0a9330
commit 20350a73a7
10 changed files with 109 additions and 89 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/imagination/include/hwdef/rogue_hw_utils.h
View File

@ -36,7 +36,7 @@
#define __pvr_address_type pvr_dev_addr_t
#define __pvr_get_address(pvr_dev_addr) (pvr_dev_addr).addr
/* clang-format off */
#define __pvr_make_address(addr_u64) (pvr_dev_addr_t){ .addr = addr_u64 }
#define __pvr_make_address(addr_u64) PVR_DEV_ADDR(addr_u64)
/* clang-format on */
#include "csbgen/rogue_cdm.h"

6
src/imagination/include/pvr_types.h
View File

@ -34,8 +34,8 @@ typedef struct pvr_dev_addr {
uint64_t addr;
} pvr_dev_addr_t;
/* clang-format off */
#define PVR_DEV_ADDR_INVALID (pvr_dev_addr_t){ .addr = 0 }
/* clang-format on */
#define PVR_DEV_ADDR(addr_) ((pvr_dev_addr_t){ .addr = (addr_) })
#define PVR_DEV_ADDR_OFFSET(base, offset) PVR_DEV_ADDR((base).addr + (offset))
#define PVR_DEV_ADDR_INVALID PVR_DEV_ADDR(0)
#endif /* PVR_TYPES_H */

88
src/imagination/vulkan/pvr_cmd_buffer.c
View File

@ -661,12 +661,13 @@ static void pvr_pds_bgnd_pack_state(
uint64_t pds_reg_values[static const ROGUE_NUM_CR_PDS_BGRND_WORDS])
{
pvr_csb_pack (&pds_reg_values[0], CR_PDS_BGRND0_BASE, value) {
value.shader_addr.addr = load_op->pds_frag_prog.data_offset;
value.texunicode_addr.addr = load_op->pds_tex_state_prog.code_offset;
value.shader_addr = PVR_DEV_ADDR(load_op->pds_frag_prog.data_offset);
value.texunicode_addr =
PVR_DEV_ADDR(load_op->pds_tex_state_prog.code_offset);
}
pvr_csb_pack (&pds_reg_values[1], CR_PDS_BGRND1_BASE, value) {
value.texturedata_addr.addr = load_op_program->data_offset;
value.texturedata_addr = PVR_DEV_ADDR(load_op_program->data_offset);
}
pvr_csb_pack (&pds_reg_values[2], CR_PDS_BGRND3_SIZEINFO, value) {
@ -758,9 +759,9 @@ static void pvr_setup_pbe_state(
/* FIXME: Should we have an inline function to return the address of a mip
* level?
*/
surface_params.addr.addr =
image->vma->dev_addr.addr +
image->mip_levels[iview->vk.base_mip_level].offset;
surface_params.addr =
PVR_DEV_ADDR_OFFSET(image->vma->dev_addr,
image->mip_levels[iview->vk.base_mip_level].offset);
surface_params.mem_layout = image->memlayout;
surface_params.stride = pvr_stride_from_pitch(level_pitch, iview->vk.format);
@ -1243,7 +1244,7 @@ pvr_compute_generate_control_stream(struct pvr_csb *csb,
/* Compute kernel 1. */
pvr_csb_emit (csb, CDMCTRL_KERNEL1, kernel1) {
kernel1.data_addr.addr = info->pds_data_offset;
kernel1.data_addr = PVR_DEV_ADDR(info->pds_data_offset);
kernel1.sd_type = info->sd_type;
if (!info->is_fence)
@ -1252,7 +1253,7 @@ pvr_compute_generate_control_stream(struct pvr_csb *csb,
/* Compute kernel 2. */
pvr_csb_emit (csb, CDMCTRL_KERNEL2, kernel2) {
kernel2.code_addr.addr = info->pds_code_offset;
kernel2.code_addr = PVR_DEV_ADDR(info->pds_code_offset);
}
if (info->indirect_buffer_addr.addr) {
@ -1313,7 +1314,7 @@ pvr_compute_generate_fence(struct pvr_cmd_buffer *cmd_buffer,
struct pvr_csb *csb = &sub_cmd->control_stream;
struct pvr_compute_kernel_info info = {
.indirect_buffer_addr.addr = 0ULL,
.indirect_buffer_addr = PVR_DEV_ADDR_INVALID,
.global_offsets_present = false,
.usc_common_size = 0U,
.usc_unified_size = 0U,
@ -2569,10 +2570,11 @@ pvr_setup_vertex_buffers(struct pvr_cmd_buffer *cmd_buffer,
case PVR_PDS_CONST_MAP_ENTRY_TYPE_DOUTU_ADDRESS: {
const struct pvr_const_map_entry_doutu_address *const doutu_addr =
(struct pvr_const_map_entry_doutu_address *)entries;
pvr_dev_addr_t exec_addr = vertex_state->bo->vma->dev_addr;
const pvr_dev_addr_t exec_addr =
PVR_DEV_ADDR_OFFSET(vertex_state->bo->vma->dev_addr,
vertex_state->entry_offset);
uint64_t addr = 0ULL;
exec_addr.addr += vertex_state->entry_offset;
pvr_set_usc_execution_address64(&addr, exec_addr.addr);
PVR_WRITE(qword_buffer,
@ -2603,13 +2605,12 @@ pvr_setup_vertex_buffers(struct pvr_cmd_buffer *cmd_buffer,
(struct pvr_const_map_entry_vertex_attribute_address *)entries;
const struct pvr_vertex_binding *const binding =
&state->vertex_bindings[attribute->binding_index];
uint64_t addr = binding->buffer->dev_addr.addr;
addr += binding->offset;
addr += attribute->offset;
const pvr_dev_addr_t addr =
PVR_DEV_ADDR_OFFSET(binding->buffer->dev_addr,
binding->offset + attribute->offset);
PVR_WRITE(qword_buffer,
addr,
addr.addr,
attribute->const_offset,
pds_info->data_size_in_dwords);
@ -2728,8 +2729,9 @@ static VkResult pvr_setup_descriptor_mappings(
assert(descriptor->buffer_create_info_size ==
const_buffer_entry->size_in_dwords * sizeof(uint32_t));
buffer_addr = descriptor->buffer_dev_addr;
buffer_addr.addr += const_buffer_entry->offset * sizeof(uint32_t);
buffer_addr =
PVR_DEV_ADDR_OFFSET(descriptor->buffer_dev_addr,
const_buffer_entry->offset * sizeof(uint32_t));
PVR_WRITE(qword_buffer,
buffer_addr.addr,
@ -2791,18 +2793,22 @@ static VkResult pvr_setup_descriptor_mappings(
desc_set_addr = descriptor_set->pvr_bo->vma->dev_addr;
if (desc_set_entry->primary) {
desc_set_addr.addr +=
desc_set_addr = PVR_DEV_ADDR_OFFSET(
desc_set_addr,
descriptor_set->layout->memory_layout_in_dwords_per_stage[stage]
.primary_offset
<< 2U;
.primary_offset
<< 2U);
} else {
desc_set_addr.addr +=
desc_set_addr = PVR_DEV_ADDR_OFFSET(
desc_set_addr,
descriptor_set->layout->memory_layout_in_dwords_per_stage[stage]
.secondary_offset
<< 2U;
.secondary_offset
<< 2U);
}
desc_set_addr.addr += (uint64_t)desc_set_entry->offset_in_dwords << 2U;
desc_set_addr = PVR_DEV_ADDR_OFFSET(
desc_set_addr,
(uint64_t)desc_set_entry->offset_in_dwords << 2U);
PVR_WRITE(qword_buffer,
desc_set_addr.addr,
@ -2846,7 +2852,7 @@ static void pvr_compute_update_shared(struct pvr_cmd_buffer *cmd_buffer,
return;
info = (struct pvr_compute_kernel_info){
.indirect_buffer_addr.addr = 0ULL,
.indirect_buffer_addr = PVR_DEV_ADDR_INVALID,
.sd_type = PVRX(CDMCTRL_SD_TYPE_NONE),
.usc_target = PVRX(CDMCTRL_USC_TARGET_ALL),
@ -2937,7 +2943,7 @@ static void pvr_compute_update_kernel(
&pipeline->state.primary_program_info;
struct pvr_compute_kernel_info info = {
.indirect_buffer_addr.addr = 0ULL,
.indirect_buffer_addr = PVR_DEV_ADDR_INVALID,
.usc_target = PVRX(CDMCTRL_USC_TARGET_ANY),
.pds_temp_size =
DIV_ROUND_UP(program_info->temps_required << 2U,
@ -3154,12 +3160,13 @@ pvr_emit_dirty_pds_state(const struct pvr_cmd_buffer *const cmd_buffer,
}
pvr_csb_emit (csb, VDMCTRL_PDS_STATE1, state1) {
state1.pds_data_addr.addr = pds_vertex_uniform_data_offset;
state1.pds_data_addr = PVR_DEV_ADDR(pds_vertex_uniform_data_offset);
state1.sd_type = PVRX(VDMCTRL_SD_TYPE_NONE);
}
pvr_csb_emit (csb, VDMCTRL_PDS_STATE2, state2) {
state2.pds_code_addr.addr = vertex_uniform_state->pds_code.code_offset;
state2.pds_code_addr =
PVR_DEV_ADDR(vertex_uniform_state->pds_code.code_offset);
}
}
@ -3668,14 +3675,15 @@ pvr_setup_fragment_state_pointers(struct pvr_cmd_buffer *const cmd_buffer,
const struct pvr_pds_upload *const pds_upload =
&state->gfx_pipeline->fragment_shader_state.pds_fragment_program;
shader_base.addr.addr = pds_upload->data_offset;
shader_base.addr = PVR_DEV_ADDR(pds_upload->data_offset);
}
if (uniform_shader_state->pds_code.pvr_bo) {
pvr_csb_pack (&ppp_state->pds.texture_uniform_code_base,
TA_STATE_PDS_TEXUNICODEBASE,
tex_base) {
tex_base.addr.addr = uniform_shader_state->pds_code.code_offset;
tex_base.addr =
PVR_DEV_ADDR(uniform_shader_state->pds_code.code_offset);
}
} else {
ppp_state->pds.texture_uniform_code_base = 0U;
@ -3707,7 +3715,7 @@ pvr_setup_fragment_state_pointers(struct pvr_cmd_buffer *const cmd_buffer,
pvr_csb_pack (&ppp_state->pds.varying_base,
TA_STATE_PDS_VARYINGBASE,
base) {
base.addr.addr = pds_coeff_program->data_offset;
base.addr = PVR_DEV_ADDR(pds_coeff_program->data_offset);
}
} else {
ppp_state->pds.varying_base = 0U;
@ -3716,7 +3724,7 @@ pvr_setup_fragment_state_pointers(struct pvr_cmd_buffer *const cmd_buffer,
pvr_csb_pack (&ppp_state->pds.uniform_state_data_base,
TA_STATE_PDS_UNIFORMDATABASE,
base) {
base.addr.addr = state->pds_fragment_uniform_data_offset;
base.addr = PVR_DEV_ADDR(state->pds_fragment_uniform_data_offset);
}
emit_state->pds_fragment_stateptr0 = true;
@ -4270,7 +4278,8 @@ pvr_emit_dirty_vdm_state(const struct pvr_cmd_buffer *const cmd_buffer,
if (header.vs_data_addr_present) {
pvr_csb_emit (csb, VDMCTRL_VDM_STATE2, state2) {
state2.vs_pds_data_base_addr.addr = state->pds_vertex_attrib_offset;
state2.vs_pds_data_base_addr =
PVR_DEV_ADDR(state->pds_vertex_attrib_offset);
}
}
@ -4279,7 +4288,8 @@ pvr_emit_dirty_vdm_state(const struct pvr_cmd_buffer *const cmd_buffer,
gfx_pipeline->vertex_shader_state.vertex_input_size << 2;
pvr_csb_emit (csb, VDMCTRL_VDM_STATE3, state3) {
state3.vs_pds_code_base_addr.addr = state->pds_shader.code_offset;
state3.vs_pds_code_base_addr =
PVR_DEV_ADDR(state->pds_shader.code_offset);
}
pvr_csb_emit (csb, VDMCTRL_VDM_STATE4, state4) {
@ -4507,7 +4517,7 @@ static void pvr_emit_vdm_index_list(struct pvr_cmd_buffer *cmd_buffer,
struct pvr_csb *const csb = &sub_cmd->control_stream;
struct PVRX(VDMCTRL_INDEX_LIST0)
list_hdr = { pvr_cmd_header(VDMCTRL_INDEX_LIST0) };
pvr_dev_addr_t index_buffer_addr = { 0 };
pvr_dev_addr_t index_buffer_addr = PVR_DEV_ADDR_INVALID;
unsigned int index_stride = 0;
pvr_csb_emit (csb, VDMCTRL_INDEX_LIST0, list0) {
@ -4547,9 +4557,9 @@ static void pvr_emit_vdm_index_list(struct pvr_cmd_buffer *cmd_buffer,
}
list0.index_addr_present = true;
index_buffer_addr.addr = buffer->dev_addr.addr;
index_buffer_addr.addr += state->index_buffer_binding.offset;
index_buffer_addr.addr += first_index * index_stride;
index_buffer_addr = PVR_DEV_ADDR_OFFSET(
buffer->dev_addr,
state->index_buffer_binding.offset + first_index * index_stride);
list0.index_base_addrmsb = index_buffer_addr;
}

2
src/imagination/vulkan/pvr_csb.h
View File

@ -44,7 +44,7 @@
#define __pvr_address_type pvr_dev_addr_t
#define __pvr_get_address(pvr_dev_addr) (pvr_dev_addr).addr
/* clang-format off */
#define __pvr_make_address(addr_u64) (pvr_dev_addr_t){ .addr = addr_u64 }
#define __pvr_make_address(addr_u64) PVR_DEV_ADDR(addr_u64)
/* clang-format on */
#include "csbgen/rogue_hwdefs.h"

5
src/imagination/vulkan/pvr_descriptor_set.c
View File

@ -1352,13 +1352,14 @@ pvr_descriptor_update_buffer_info(const struct pvr_device *device,
PVR_FROM_HANDLE(pvr_buffer, buffer, buffer_info->buffer);
const uint32_t desc_idx =
binding->descriptor_index + write_set->dstArrayElement + i;
uint64_t addr = buffer->dev_addr.addr + buffer_info->offset;
const pvr_dev_addr_t addr =
PVR_DEV_ADDR_OFFSET(buffer->dev_addr, buffer_info->offset);
uint32_t range = (buffer_info->range == VK_WHOLE_SIZE)
? (buffer->size - buffer_info->offset)
: (buffer_info->range);
set->descriptors[desc_idx].type = write_set->descriptorType;
set->descriptors[desc_idx].buffer_dev_addr.addr = addr;
set->descriptors[desc_idx].buffer_dev_addr = addr;
set->descriptors[desc_idx].buffer_create_info_size = buffer->size;
set->descriptors[desc_idx].buffer_desc_range = range;

45
src/imagination/vulkan/pvr_job_context.c
View File

@ -726,7 +726,7 @@ pvr_rogue_get_vdmctrl_pds_state_words(struct pvr_pds_upload *pds_program,
};
pvr_csb_pack (state1_out, VDMCTRL_PDS_STATE1, state) {
state.pds_data_addr.addr = pds_program->data_offset;
state.pds_data_addr = PVR_DEV_ADDR(pds_program->data_offset);
state.sd_type = PVRX(VDMCTRL_SD_TYPE_PDS);
state.sd_next_type = PVRX(VDMCTRL_SD_TYPE_PDS);
}
@ -753,7 +753,7 @@ pvr_rogue_get_geom_state_stream_out_words(struct pvr_pds_upload *pds_program,
}
pvr_csb_pack (stream_out2_out, TA_STATE_STREAM_OUT2, state) {
state.pds_data_addr.addr = pds_program->data_offset;
state.pds_data_addr = PVR_DEV_ADDR(pds_program->data_offset);
}
}
@ -791,7 +791,8 @@ static void pvr_render_ctx_ws_static_state_init(
d_dst = &static_state->geom_state[i].vdm_ctx_store_task1;
pvr_csb_pack (d_dst, CR_VDM_CONTEXT_STORE_TASK1, task1) {
pvr_csb_pack (&task1.pds_state2, VDMCTRL_PDS_STATE2, state) {
state.pds_code_addr.addr = sr_prog->pds.store_program.code_offset;
state.pds_code_addr =
PVR_DEV_ADDR(sr_prog->pds.store_program.code_offset);
}
}
@ -815,7 +816,8 @@ static void pvr_render_ctx_ws_static_state_init(
d_dst = &static_state->geom_state[i].vdm_ctx_resume_task1;
pvr_csb_pack (d_dst, CR_VDM_CONTEXT_RESUME_TASK1, task1) {
pvr_csb_pack (&task1.pds_state2, VDMCTRL_PDS_STATE2, state) {
state.pds_code_addr.addr = sr_prog->pds.load_program.code_offset;
state.pds_code_addr =
PVR_DEV_ADDR(sr_prog->pds.load_program.code_offset);
}
}
@ -980,15 +982,19 @@ static void pvr_compute_ctx_ws_static_state_init(
pvr_csb_pack (&static_state->cdm_ctx_store_pds0,
CR_CDM_CONTEXT_PDS0,
state) {
state.data_addr.addr = ctx_switch->sr[0].pds.store_program.data_offset;
state.code_addr.addr = ctx_switch->sr[0].pds.store_program.code_offset;
state.data_addr =
PVR_DEV_ADDR(ctx_switch->sr[0].pds.store_program.data_offset);
state.code_addr =
PVR_DEV_ADDR(ctx_switch->sr[0].pds.store_program.code_offset);
}
pvr_csb_pack (&static_state->cdm_ctx_store_pds0_b,
CR_CDM_CONTEXT_PDS0,
state) {
state.data_addr.addr = ctx_switch->sr[1].pds.store_program.data_offset;
state.code_addr.addr = ctx_switch->sr[1].pds.store_program.code_offset;
state.data_addr =
PVR_DEV_ADDR(ctx_switch->sr[1].pds.store_program.data_offset);
state.code_addr =
PVR_DEV_ADDR(ctx_switch->sr[1].pds.store_program.code_offset);
}
pvr_csb_pack (&static_state->cdm_ctx_store_pds1,
@ -1020,8 +1026,10 @@ static void pvr_compute_ctx_ws_static_state_init(
pvr_csb_pack (&static_state->cdm_ctx_terminate_pds,
CR_CDM_TERMINATE_PDS,
state) {
state.data_addr.addr = ctx_switch->sr_fence_terminate_program.data_offset;
state.code_addr.addr = ctx_switch->sr_fence_terminate_program.code_offset;
state.data_addr =
PVR_DEV_ADDR(ctx_switch->sr_fence_terminate_program.data_offset);
state.code_addr =
PVR_DEV_ADDR(ctx_switch->sr_fence_terminate_program.code_offset);
}
pvr_csb_pack (&static_state->cdm_ctx_terminate_pds1,
@ -1053,15 +1061,19 @@ static void pvr_compute_ctx_ws_static_state_init(
pvr_csb_pack (&static_state->cdm_ctx_resume_pds0,
CR_CDM_CONTEXT_LOAD_PDS0,
state) {
state.data_addr.addr = ctx_switch->sr[0].pds.load_program.data_offset;
state.code_addr.addr = ctx_switch->sr[0].pds.load_program.code_offset;
state.data_addr =
PVR_DEV_ADDR(ctx_switch->sr[0].pds.load_program.data_offset);
state.code_addr =
PVR_DEV_ADDR(ctx_switch->sr[0].pds.load_program.code_offset);
}
pvr_csb_pack (&static_state->cdm_ctx_resume_pds0_b,
CR_CDM_CONTEXT_LOAD_PDS0,
state) {
state.data_addr.addr = ctx_switch->sr[1].pds.load_program.data_offset;
state.code_addr.addr = ctx_switch->sr[1].pds.load_program.code_offset;
state.data_addr =
PVR_DEV_ADDR(ctx_switch->sr[1].pds.load_program.data_offset);
state.code_addr =
PVR_DEV_ADDR(ctx_switch->sr[1].pds.load_program.code_offset);
}
}
@ -1207,8 +1219,9 @@ static VkResult pvr_transfer_ctx_setup_shaders(struct pvr_device *device,
STATIC_ASSERT(ARRAY_SIZE(pvr_transfer_eot_usc_offsets) ==
ARRAY_SIZE(ctx->transfer_mrts));
for (uint32_t i = 0U; i < ARRAY_SIZE(pvr_transfer_eot_usc_offsets); i++) {
ctx->transfer_mrts[i] = ctx->usc_eot_bo->vma->dev_addr;
ctx->transfer_mrts[i].addr += pvr_transfer_eot_usc_offsets[i];
ctx->transfer_mrts[i] =
PVR_DEV_ADDR_OFFSET(ctx->usc_eot_bo->vma->dev_addr,
pvr_transfer_eot_usc_offsets[i]);
}
return VK_SUCCESS;

16
src/imagination/vulkan/pvr_job_render.c
View File

@ -440,8 +440,8 @@ static VkResult pvr_rt_vheap_rtc_data_init(struct pvr_device *device,
rt_dataset->vheap_dev_addr = rt_dataset->vheap_rtc_bo->vma->dev_addr;
if (rtc_size > 0) {
rt_dataset->rtc_dev_addr.addr =
rt_dataset->vheap_dev_addr.addr + vheap_size;
rt_dataset->rtc_dev_addr =
PVR_DEV_ADDR_OFFSET(rt_dataset->vheap_dev_addr, vheap_size);
} else {
rt_dataset->rtc_dev_addr = PVR_DEV_ADDR_INVALID;
}
@ -645,19 +645,19 @@ pvr_rt_mta_mlist_data_init(struct pvr_device *device,
for (uint32_t i = 0; i < num_rt_datas; i++) {
if (mta_size != 0) {
rt_dataset->rt_datas[i].mta_dev_addr = dev_addr;
dev_addr.addr += mta_size;
dev_addr = PVR_DEV_ADDR_OFFSET(dev_addr, mta_size);
} else {
rt_dataset->rt_datas[i].mta_dev_addr = PVR_DEV_ADDR_INVALID;
}
}
dev_addr.addr =
rt_dataset->mta_mlist_bo->vma->dev_addr.addr + rt_datas_mta_size;
dev_addr = PVR_DEV_ADDR_OFFSET(rt_dataset->mta_mlist_bo->vma->dev_addr,
rt_datas_mta_size);
for (uint32_t i = 0; i < num_rt_datas; i++) {
if (mlist_size != 0) {
rt_dataset->rt_datas[i].mlist_dev_addr = dev_addr;
dev_addr.addr += mlist_size;
dev_addr = PVR_DEV_ADDR_OFFSET(dev_addr, mlist_size);
} else {
rt_dataset->rt_datas[i].mlist_dev_addr = PVR_DEV_ADDR_INVALID;
}
@ -707,7 +707,7 @@ pvr_rt_rgn_headers_data_init(struct pvr_device *device,
for (uint32_t i = 0; i < num_rt_datas; i++) {
rt_dataset->rt_datas[i].rgn_headers_dev_addr = dev_addr;
dev_addr.addr += rgn_headers_size;
dev_addr = PVR_DEV_ADDR_OFFSET(dev_addr, rgn_headers_size);
}
return VK_SUCCESS;
@ -1456,7 +1456,7 @@ pvr_render_job_ws_fragment_state_init(struct pvr_render_ctx *ctx,
pvr_csb_pack (&state->regs.event_pixel_pds_data,
CR_EVENT_PIXEL_PDS_DATA,
value) {
value.addr.addr = job->pds_pixel_event_data_offset;
value.addr = PVR_DEV_ADDR(job->pds_pixel_event_data_offset);
}
STATIC_ASSERT(ARRAY_SIZE(state->regs.pbe_word) ==

6
src/imagination/vulkan/pvr_tex_state.c
View File

@ -139,8 +139,7 @@ pvr_pack_tex_state(struct pvr_device *device,
word1.num_mip_levels = info->mip_levels;
word1.mipmaps_present = info->mipmaps_present;
word1.texaddr = info->addr;
word1.texaddr.addr += info->offset;
word1.texaddr = PVR_DEV_ADDR_OFFSET(info->addr, info->offset);
if (vk_format_is_alpha_on_msb(info->format))
word1.alpha_msb = true;
@ -178,8 +177,7 @@ pvr_pack_tex_state(struct pvr_device *device,
word1.depth = array_layers - 1;
}
word1.texaddr = info->addr;
word1.texaddr.addr += info->offset;
word1.texaddr = PVR_DEV_ADDR_OFFSET(info->addr, info->offset);
if (!PVR_HAS_FEATURE(dev_info, tpu_extended_integer_lookup) &&
!PVR_HAS_FEATURE(dev_info, tpu_image_state_v2)) {

13
src/imagination/vulkan/winsys/pvr_winsys_helper.c
View File

@ -78,9 +78,10 @@ VkResult pvr_winsys_helper_winsys_heap_init(
{
const bool reserved_area_bottom_of_heap = reserved_address.addr ==
base_address.addr;
const uint64_t vma_heap_begin_addr =
base_address.addr +
(uint64_t)reserved_area_bottom_of_heap * reserved_size;
const pvr_dev_addr_t vma_heap_begin_addr =
reserved_area_bottom_of_heap
? PVR_DEV_ADDR_OFFSET(base_address, reserved_size)
: base_address;
const uint64_t vma_heap_size = size - reserved_size;
assert(base_address.addr);
@ -106,7 +107,7 @@ VkResult pvr_winsys_helper_winsys_heap_init(
heap->page_size = 1 << log2_page_size;
heap->log2_page_size = log2_page_size;
util_vma_heap_init(&heap->vma_heap, vma_heap_begin_addr, vma_heap_size);
util_vma_heap_init(&heap->vma_heap, vma_heap_begin_addr.addr, vma_heap_size);
heap->vma_heap.alloc_high = false;
@ -157,8 +158,8 @@ bool pvr_winsys_helper_heap_alloc(struct pvr_winsys_heap *const heap,
vma.size = size;
pthread_mutex_lock(&heap->lock);
vma.dev_addr.addr =
util_vma_heap_alloc(&heap->vma_heap, size, heap->page_size);
vma.dev_addr =
PVR_DEV_ADDR(util_vma_heap_alloc(&heap->vma_heap, size, heap->page_size));
pthread_mutex_unlock(&heap->lock);
if (!vma.dev_addr.addr) {

15
src/imagination/vulkan/winsys/pvrsrvkm/pvr_srv_bo.c
View File

@ -371,7 +371,6 @@ pvr_srv_heap_alloc_reserved(struct pvr_winsys_heap *heap,
struct pvr_srv_winsys *srv_ws = to_pvr_srv_winsys(heap->ws);
struct pvr_srv_winsys_vma *srv_vma;
VkResult result;
uint64_t addr;
assert(util_is_power_of_two_nonzero(alignment));
@ -400,18 +399,16 @@ pvr_srv_heap_alloc_reserved(struct pvr_winsys_heap *heap,
reserved_dev_addr.addr & ((srv_ws->base.page_size) - 1))
goto err_vk_free_srv_vma;
addr = reserved_dev_addr.addr;
/* Reserve the virtual range in the MMU and create a mapping structure */
result = pvr_srv_int_reserve_addr(srv_ws->render_fd,
srv_heap->server_heap,
(pvr_dev_addr_t){ .addr = addr },
reserved_dev_addr,
size,
&srv_vma->reservation);
if (result != VK_SUCCESS)
goto err_vk_free_srv_vma;
srv_vma->base.dev_addr.addr = addr;
srv_vma->base.dev_addr = reserved_dev_addr;
srv_vma->base.bo = NULL;
srv_vma->base.heap = heap;
srv_vma->base.size = size;
@ -523,7 +520,7 @@ pvr_dev_addr_t pvr_srv_winsys_vma_map(struct pvr_winsys_vma *vma,
if (offset != 0 || bo->size != ALIGN_POT(size, srv_ws->base.page_size) ||
vma->size != bo->size) {
vk_error(NULL, VK_ERROR_MEMORY_MAP_FAILED);
return (pvr_dev_addr_t){ .addr = 0UL };
return PVR_DEV_ADDR_INVALID;
}
/* Map the requested pmr */
@ -544,7 +541,7 @@ pvr_dev_addr_t pvr_srv_winsys_vma_map(struct pvr_winsys_vma *vma,
if (ALIGN_POT(offset + size, vma->heap->page_size) > bo->size ||
aligned_virt_size > vma->size) {
vk_error(NULL, VK_ERROR_MEMORY_MAP_FAILED);
return (pvr_dev_addr_t){ .addr = 0UL };
return PVR_DEV_ADDR_INVALID;
}
/* Map the requested pages */
@ -558,7 +555,7 @@ pvr_dev_addr_t pvr_srv_winsys_vma_map(struct pvr_winsys_vma *vma,
}
if (result != VK_SUCCESS)
return (pvr_dev_addr_t){ .addr = 0UL };
return PVR_DEV_ADDR_INVALID;
buffer_acquire(srv_bo);
@ -566,7 +563,7 @@ pvr_dev_addr_t pvr_srv_winsys_vma_map(struct pvr_winsys_vma *vma,
vma->bo_offset = offset;
vma->mapped_size = aligned_virt_size;
return (pvr_dev_addr_t){ .addr = vma->dev_addr.addr + virt_offset };
return PVR_DEV_ADDR_OFFSET(vma->dev_addr, virt_offset);
}
void pvr_srv_winsys_vma_unmap(struct pvr_winsys_vma *vma)