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i965: Don't rely on nir for uses_texture_gather 

When a program is restored from the shader cache, prog->nir will be
NULL, but prog->info will be restored.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Jordan Justen 2017-07-28 15:46:02 -07:00
parent 0610a624a1
commit 1edf0fe612
3 changed files with 9 additions and 9 deletions
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2
src/mesa/drivers/dri/i965/brw_program.c
View File

@ -689,7 +689,7 @@ brw_assign_common_binding_table_offsets(const struct gen_device_info *devinfo,
stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
}
if (prog->nir->info.uses_texture_gather) {
if (prog->info.uses_texture_gather) {
if (devinfo->gen >= 8) {
stage_prog_data->binding_table.gather_texture_start =
stage_prog_data->binding_table.texture_start;

4
src/mesa/drivers/dri/i965/brw_wm.c
View File

@ -339,7 +339,7 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx,
}
/* gather4 for RG32* is broken in multiple ways on Gen7. */
if (devinfo->gen == 7 && prog->nir->info.uses_texture_gather) {
if (devinfo->gen == 7 && prog->info.uses_texture_gather) {
switch (img->InternalFormat) {
case GL_RG32I:
case GL_RG32UI: {
@ -377,7 +377,7 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx,
/* Gen6's gather4 is broken for UINT/SINT; we treat them as
* UNORM/FLOAT instead and fix it in the shader.
*/
if (devinfo->gen == 6 && prog->nir->info.uses_texture_gather) {
if (devinfo->gen == 6 && prog->info.uses_texture_gather) {
key->gen6_gather_wa[s] = gen6_gather_workaround(img->InternalFormat);
}

12
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
View File

@ -1199,15 +1199,15 @@ brw_update_texture_surfaces(struct brw_context *brw)
* allows the surface format to be overriden for only the
* gather4 messages. */
if (devinfo->gen < 8) {
if (vs && vs->nir->info.uses_texture_gather)
if (vs && vs->info.uses_texture_gather)
update_stage_texture_surfaces(brw, vs, &brw->vs.base, true, 0);
if (tcs && tcs->nir->info.uses_texture_gather)
if (tcs && tcs->info.uses_texture_gather)
update_stage_texture_surfaces(brw, tcs, &brw->tcs.base, true, 0);
if (tes && tes->nir->info.uses_texture_gather)
if (tes && tes->info.uses_texture_gather)
update_stage_texture_surfaces(brw, tes, &brw->tes.base, true, 0);
if (gs && gs->nir->info.uses_texture_gather)
if (gs && gs->info.uses_texture_gather)
update_stage_texture_surfaces(brw, gs, &brw->gs.base, true, 0);
if (fs && fs->nir->info.uses_texture_gather)
if (fs && fs->info.uses_texture_gather)
update_stage_texture_surfaces(brw, fs, &brw->wm.base, true, 0);
}
@ -1254,7 +1254,7 @@ brw_update_cs_texture_surfaces(struct brw_context *brw)
* gather4 messages.
*/
if (devinfo->gen < 8) {
if (cs && cs->nir->info.uses_texture_gather)
if (cs && cs->info.uses_texture_gather)
update_stage_texture_surfaces(brw, cs, &brw->cs.base, true, 0);
}