ac/surface: add a test of HtileAddrFromCoord prototype outside of addrlib
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10187>
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@ -47,8 +47,8 @@
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#include "ac_surface_test_common.h"
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/*
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* The main goal of this test is to validate that our dcc addressing functions
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* match addrlib behavior.
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* The main goal of this test is to validate that our dcc/htile addressing
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* functions match addrlib behavior.
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*/
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/* DCC address computation without mipmapping. */
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@ -109,22 +109,20 @@ static unsigned gfx9_dcc_addr_from_coord(const struct radeon_info *info,
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return (address >> 1) ^ (pipeXor << m_pipeInterleaveLog2);
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}
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/* DCC address computation without mipmapping and MSAA. */
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static unsigned gfx10_dcc_addr_from_coord(const struct radeon_info *info,
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/* DCC/HTILE address computation for GFX10. */
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static unsigned gfx10_meta_addr_from_coord(const struct radeon_info *info,
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/* Shader key inputs: */
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/* equation varies with bpp and pipe_aligned */
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const uint16_t *equation, unsigned bpp,
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const uint16_t *equation,
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unsigned meta_block_width, unsigned meta_block_height,
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unsigned blkSizeLog2,
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/* Shader inputs: */
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unsigned dcc_pitch, unsigned dcc_slice_size,
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unsigned meta_pitch, unsigned meta_slice_size,
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unsigned x, unsigned y, unsigned z,
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unsigned pipe_xor)
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{
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/* The compiled shader shouldn't be complicated considering there are a lot of constants here. */
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unsigned bpp_log2 = util_logbase2(bpp >> 3);
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unsigned meta_block_width_log2 = util_logbase2(meta_block_width);
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unsigned meta_block_height_log2 = util_logbase2(meta_block_height);
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unsigned blkSizeLog2 = meta_block_width_log2 + meta_block_height_log2 + bpp_log2 - 8;
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unsigned coord[] = {x, y, z, 0};
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unsigned address = 0;
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@ -150,15 +148,38 @@ static unsigned gfx10_dcc_addr_from_coord(const struct radeon_info *info,
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unsigned m_pipeInterleaveLog2 = 8 + G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config);
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unsigned xb = x >> meta_block_width_log2;
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unsigned yb = y >> meta_block_height_log2;
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unsigned pb = dcc_pitch >> meta_block_width_log2;
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unsigned pb = meta_pitch >> meta_block_width_log2;
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unsigned blkIndex = (yb * pb) + xb;
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unsigned pipeXor = ((pipe_xor & pipeMask) << m_pipeInterleaveLog2) & blkMask;
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return (dcc_slice_size * z) +
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return (meta_slice_size * z) +
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(blkIndex * (1 << blkSizeLog2)) +
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((address >> 1) ^ pipeXor);
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}
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/* DCC address computation without mipmapping and MSAA. */
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static unsigned gfx10_dcc_addr_from_coord(const struct radeon_info *info,
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/* Shader key inputs: */
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/* equation varies with bpp and pipe_aligned */
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const uint16_t *equation, unsigned bpp,
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unsigned meta_block_width, unsigned meta_block_height,
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/* Shader inputs: */
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unsigned dcc_pitch, unsigned dcc_slice_size,
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unsigned x, unsigned y, unsigned z,
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unsigned pipe_xor)
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{
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unsigned bpp_log2 = util_logbase2(bpp >> 3);
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unsigned meta_block_width_log2 = util_logbase2(meta_block_width);
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unsigned meta_block_height_log2 = util_logbase2(meta_block_height);
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unsigned blkSizeLog2 = meta_block_width_log2 + meta_block_height_log2 + bpp_log2 - 8;
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return gfx10_meta_addr_from_coord(info, equation,
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meta_block_width, meta_block_height,
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blkSizeLog2,
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dcc_pitch, dcc_slice_size,
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x, y, z, pipe_xor);
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}
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static bool one_dcc_address_test(const char *name, const char *test, ADDR_HANDLE addrlib,
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const struct radeon_info *info, unsigned width, unsigned height,
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unsigned depth, unsigned samples, unsigned bpp,
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@ -346,6 +367,139 @@ static void run_dcc_address_test(const char *name, const struct radeon_info *inf
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printf("%16s total: %u, fail: %u\n", name, total, fails);
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}
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/* HTILE address computation without mipmapping. */
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static unsigned gfx10_htile_addr_from_coord(const struct radeon_info *info,
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const uint16_t *equation,
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unsigned meta_block_width,
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unsigned meta_block_height,
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unsigned htile_pitch, unsigned htile_slice_size,
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unsigned x, unsigned y, unsigned z,
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unsigned pipe_xor)
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{
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unsigned meta_block_width_log2 = util_logbase2(meta_block_width);
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unsigned meta_block_height_log2 = util_logbase2(meta_block_height);
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unsigned blkSizeLog2 = meta_block_width_log2 + meta_block_height_log2 - 4;
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return gfx10_meta_addr_from_coord(info, equation,
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meta_block_width, meta_block_height,
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blkSizeLog2,
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htile_pitch, htile_slice_size,
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x, y, z, pipe_xor);
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}
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static bool one_htile_address_test(const char *name, const char *test, ADDR_HANDLE addrlib,
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const struct radeon_info *info,
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unsigned width, unsigned height, unsigned depth,
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unsigned bpp, unsigned swizzle_mode,
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unsigned start_x, unsigned start_y, unsigned start_z)
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{
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ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
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ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
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ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0};
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ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0};
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ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT in = {0};
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ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT out = {0};
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ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {0};
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hout.pMipInfo = meta_mip_info;
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/* Compute HTILE info. */
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hin.hTileFlags.pipeAligned = 1;
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hin.hTileFlags.rbAligned = 1;
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hin.depthFlags.depth = 1;
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hin.depthFlags.texture = 1;
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hin.depthFlags.opt4space = 1;
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hin.swizzleMode = in.swizzleMode = xin.swizzleMode = swizzle_mode;
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hin.unalignedWidth = in.unalignedWidth = width;
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hin.unalignedHeight = in.unalignedHeight = height;
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hin.numSlices = in.numSlices = depth;
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hin.numMipLevels = in.numMipLevels = 1; /* addrlib can't do HtileAddrFromCoord with mipmapping. */
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hin.firstMipIdInTail = 1;
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int ret = Addr2ComputeHtileInfo(addrlib, &hin, &hout);
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assert(ret == ADDR_OK);
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/* Compute xor. */
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static AddrFormat format[] = {
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ADDR_FMT_8, /* unused */
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ADDR_FMT_16,
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ADDR_FMT_32,
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};
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xin.flags = hin.depthFlags;
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xin.resourceType = ADDR_RSRC_TEX_2D;
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xin.format = format[util_logbase2(bpp / 8)];
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xin.numFrags = xin.numSamples = in.numSamples = 1;
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ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
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assert(ret == ADDR_OK);
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in.hTileFlags = hin.hTileFlags;
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in.depthflags = xin.flags;
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in.bpp = bpp;
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in.pipeXor = xout.pipeBankXor;
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for (in.x = start_x; in.x < width; in.x++) {
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for (in.y = start_y; in.y < height; in.y++) {
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for (in.slice = start_z; in.slice < depth; in.slice++) {
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int r = Addr2ComputeHtileAddrFromCoord(addrlib, &in, &out);
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if (r != ADDR_OK) {
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printf("%s addrlib error: %s\n", name, test);
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abort();
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}
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unsigned addr =
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gfx10_htile_addr_from_coord(info, hout.equation.gfx10_bits,
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hout.metaBlkWidth, hout.metaBlkHeight,
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hout.pitch, hout.sliceSize,
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in.x, in.y, in.slice, in.pipeXor);
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if (out.addr != addr) {
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printf("%s fail (%s) at %ux%ux%u: expected = %llu, got = %u\n",
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name, test, in.x, in.y, in.slice, out.addr, addr);
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return false;
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}
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}
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}
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}
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return true;
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}
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static void run_htile_address_test(const char *name, const struct radeon_info *info, bool full)
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{
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unsigned total = 0;
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unsigned fails = 0;
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unsigned first_size = 0, last_size = 6*6 - 1, max_bpp = 32;
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/* The test coverage is reduced for Gitlab CI because it timeouts. */
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if (!full) {
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first_size = last_size = 0;
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}
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#ifdef HAVE_OPENMP
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#pragma omp parallel for
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#endif
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for (unsigned size = first_size; size <= last_size; size++) {
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unsigned width = 8 + 379 * (size % 6);
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unsigned height = 8 + 379 * (size / 6);
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struct ac_addrlib *ac_addrlib = ac_addrlib_create(info, NULL);
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ADDR_HANDLE addrlib = ac_addrlib_get_handle(ac_addrlib);
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for (unsigned depth = 1; depth <= 2; depth *= 2) {
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for (unsigned bpp = 16; bpp <= max_bpp; bpp *= 2) {
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if (one_htile_address_test(name, name, addrlib, info, width, height, depth,
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bpp, ADDR_SW_64KB_Z_X, 0, 0, 0)) {
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} else {
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p_atomic_inc(&fails);
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}
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p_atomic_inc(&total);
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}
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}
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ac_addrlib_destroy(ac_addrlib);
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}
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printf("%16s total: %u, fail: %u\n", name, total, fails);
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}
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int main(int argc, char **argv)
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{
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bool full = false;
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else
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puts("Specify --full to run the full test.");
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puts("DCC:");
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for (unsigned i = 0; i < ARRAY_SIZE(testcases); ++i) {
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struct radeon_info info = get_radeon_info(&testcases[i]);
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run_dcc_address_test(testcases[i].name, &info, full);
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}
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puts("HTILE:");
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for (unsigned i = 0; i < ARRAY_SIZE(testcases); ++i) {
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struct radeon_info info = get_radeon_info(&testcases[i]);
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/* Only GFX10+ is currently supported. */
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if (info.chip_class < GFX10)
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continue;
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run_htile_address_test(testcases[i].name, &info, full);
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}
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return 0;
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}
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