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ir3: Handle special regs in regmask 

Use the same hack as post-RA scheduling.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>
This commit is contained in:
Connor Abbott 2021-09-29 16:17:31 +02:00 committed by Marge Bot
parent a37f9602b7
commit 1ed9a2f50c
1 changed files with 16 additions and 4 deletions
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20
src/freedreno/ir3/ir3.h
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@ -1147,6 +1147,15 @@ is_reg_special(const struct ir3_register *reg)
(reg_num(reg) == REG_P0);
}
/* Same as above but in cases where we don't have a register. r48.x and above
* are shared/special.
*/
static inline bool
is_reg_num_special(unsigned num)
{
return num >= 48 * 4;
}
/* returns defining instruction for reg */
/* TODO better name */
static inline struct ir3_instruction *
@ -2214,9 +2223,12 @@ __regmask_get(regmask_t *regmask, bool half, unsigned n)
if (regmask->mergedregs) {
/* a6xx+ case, with merged register file, we track things in terms
* of half-precision registers, with a full precisions register
* using two half-precision slots:
* using two half-precision slots.
*
* Pretend that special regs (a0.x, a1.x, etc.) are full registers to
* avoid having them alias normal full regs.
*/
if (half) {
if (half && !is_reg_num_special(n)) {
return BITSET_TEST(regmask->mask, n);
} else {
n *= 2;
@ -2241,7 +2253,7 @@ __regmask_set(regmask_t *regmask, bool half, unsigned n)
* of half-precision registers, with a full precisions register
* using two half-precision slots:
*/
if (half) {
if (half && !is_reg_num_special(n)) {
BITSET_SET(regmask->mask, n);
} else {
n *= 2;
@ -2266,7 +2278,7 @@ __regmask_clear(regmask_t *regmask, bool half, unsigned n)
* of half-precision registers, with a full precisions register
* using two half-precision slots:
*/
if (half) {
if (half && !is_reg_num_special(n)) {
BITSET_CLEAR(regmask->mask, n);
} else {
n *= 2;