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iris: Don't bother with PIPE_CONTROLs for CPU writes and no history 

If a buffer has no usage history, we don't have any read only cache
invalidates to do.  If we've written it with the CPU, we don't need
to flush the render cache.  The only bit remaining is the CS stall
from iris_flush_bits_for_history.  We can just skip the PIPE_CONTROL
in this case.

This is pretty common - an app creates a buffer, fills it with data,
and then binds it for some purpose.

Cuts 36% of the flushes in Manhattan 3.0 on Kabylake GT2.
This commit is contained in:
Kenneth Graunke 2019-06-19 23:30:52 -05:00
parent dfff6e10b4
commit 1d63af0f2c
1 changed files with 9 additions and 6 deletions
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15
src/gallium/drivers/iris/iris_resource.c
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@ -1479,12 +1479,15 @@ iris_transfer_flush_region(struct pipe_context *ctx,
(map->staging ? PIPE_CONTROL_RENDER_TARGET_FLUSH : 0);
}
for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
struct iris_batch *batch = &ice->batches[i];
if (batch->contains_draw || batch->cache.render->entries) {
iris_batch_maybe_flush(batch, 24);
iris_emit_pipe_control_flush(batch, "cache history: transfer flush",
history_flush);
if (history_flush & ~PIPE_CONTROL_CS_STALL) {
for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
struct iris_batch *batch = &ice->batches[i];
if (batch->contains_draw || batch->cache.render->entries) {
iris_batch_maybe_flush(batch, 24);
iris_emit_pipe_control_flush(batch,
"cache history: transfer flush",
history_flush);
}
}
}