nv50,nvc0: enable/disable seamless cubemap texturing as requested
In a situation where the seamless setting isn't available on a per-texture basis (G200+ Teslas, and all Fermis), assume that all samplers will have it identically set, and enable accordingly. This fixes arb_seamless_cubemap piglit test on Fermi and Tesla. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
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@ -153,6 +153,7 @@ struct nv50_context {
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uint32_t textures_coherent[3];
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uint32_t textures_coherent[3];
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struct nv50_tsc_entry *samplers[3][PIPE_MAX_SAMPLERS];
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struct nv50_tsc_entry *samplers[3][PIPE_MAX_SAMPLERS];
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unsigned num_samplers[3];
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unsigned num_samplers[3];
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bool seamless_cube_map;
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uint8_t num_so_targets;
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uint8_t num_so_targets;
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uint8_t so_targets_dirty;
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uint8_t so_targets_dirty;
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@ -565,7 +565,7 @@ nv50_screen_init_hwctx(struct nv50_screen *screen)
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if (screen->tesla->oclass >= NVA0_3D_CLASS) {
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if (screen->tesla->oclass >= NVA0_3D_CLASS) {
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BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
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BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
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PUSH_DATA (push, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
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PUSH_DATA (push, 0);
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}
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}
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BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
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BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
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@ -50,6 +50,7 @@ struct nv50_graph_state {
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uint8_t num_samplers[3];
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uint8_t num_samplers[3];
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uint8_t prim_size;
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uint8_t prim_size;
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uint16_t scissor;
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uint16_t scissor;
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bool seamless_cube_map;
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};
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};
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struct nv50_screen {
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struct nv50_screen {
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@ -516,6 +516,8 @@ nv50_sampler_state_create(struct pipe_context *pipe,
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so->tsc[1] |= GK104_TSC_1_CUBEMAP_INTERFACE_FILTERING;
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so->tsc[1] |= GK104_TSC_1_CUBEMAP_INTERFACE_FILTERING;
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if (!cso->normalized_coords)
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if (!cso->normalized_coords)
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so->tsc[1] |= GK104_TSC_1_FLOAT_COORD_NORMALIZATION_FORCE_UNNORMALIZED_COORDS;
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so->tsc[1] |= GK104_TSC_1_FLOAT_COORD_NORMALIZATION_FORCE_UNNORMALIZED_COORDS;
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} else {
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so->seamless_cube_map = cso->seamless_cube_map;
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}
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}
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if (cso->max_anisotropy >= 16)
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if (cso->max_anisotropy >= 16)
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@ -7,6 +7,7 @@
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struct nv50_tsc_entry {
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struct nv50_tsc_entry {
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int id;
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int id;
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uint32_t tsc[8];
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uint32_t tsc[8];
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bool seamless_cube_map;
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};
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};
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static inline struct nv50_tsc_entry *
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static inline struct nv50_tsc_entry *
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@ -361,6 +361,7 @@ nv50_validate_tsc(struct nv50_context *nv50, int s)
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PUSH_DATA (push, (i << 4) | 0);
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PUSH_DATA (push, (i << 4) | 0);
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continue;
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continue;
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}
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}
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nv50->seamless_cube_map = tsc->seamless_cube_map;
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if (tsc->id < 0) {
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if (tsc->id < 0) {
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tsc->id = nv50_screen_tsc_alloc(nv50->screen, tsc);
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tsc->id = nv50_screen_tsc_alloc(nv50->screen, tsc);
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@ -816,6 +816,13 @@ nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
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PUSH_DATA (push, 0x20);
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PUSH_DATA (push, 0x20);
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}
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}
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if (nv50->screen->base.class_3d >= NVA0_3D_CLASS &&
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nv50->seamless_cube_map != nv50->state.seamless_cube_map) {
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nv50->state.seamless_cube_map = nv50->seamless_cube_map;
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BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
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PUSH_DATA (push, nv50->seamless_cube_map ? NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP : 0);
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}
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if (nv50->vbo_fifo) {
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if (nv50->vbo_fifo) {
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nv50_push_vbo(nv50, info);
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nv50_push_vbo(nv50, info);
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push->kick_notify = nv50_default_kick_notify;
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push->kick_notify = nv50_default_kick_notify;
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@ -157,6 +157,7 @@ struct nvc0_context {
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struct nv50_tsc_entry *samplers[6][PIPE_MAX_SAMPLERS];
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struct nv50_tsc_entry *samplers[6][PIPE_MAX_SAMPLERS];
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unsigned num_samplers[6];
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unsigned num_samplers[6];
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uint16_t samplers_dirty[6];
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uint16_t samplers_dirty[6];
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bool seamless_cube_map;
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uint32_t tex_handles[6][PIPE_MAX_SAMPLERS]; /* for nve4 */
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uint32_t tex_handles[6][PIPE_MAX_SAMPLERS]; /* for nve4 */
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@ -876,8 +876,7 @@ nvc0_screen_create(struct nouveau_device *dev)
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BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
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BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
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PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
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PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
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if (screen->eng3d->oclass < NVE4_3D_CLASS) {
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if (screen->eng3d->oclass < NVE4_3D_CLASS) {
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BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
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IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
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PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
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} else {
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} else {
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BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
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BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
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PUSH_DATA (push, 15);
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PUSH_DATA (push, 15);
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@ -53,6 +53,7 @@ struct nvc0_graph_state {
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uint32_t clip_mode;
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uint32_t clip_mode;
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uint32_t uniform_buffer_bound[5];
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uint32_t uniform_buffer_bound[5];
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struct nvc0_transform_feedback_state *tfb;
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struct nvc0_transform_feedback_state *tfb;
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bool seamless_cube_map;
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};
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};
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struct nvc0_screen {
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struct nvc0_screen {
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@ -595,6 +595,7 @@ nvc0_validate_tsc(struct nvc0_context *nvc0, int s)
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commands[n++] = (i << 4) | 0;
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commands[n++] = (i << 4) | 0;
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continue;
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continue;
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}
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}
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nvc0->seamless_cube_map = tsc->seamless_cube_map;
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if (tsc->id < 0) {
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if (tsc->id < 0) {
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tsc->id = nvc0_screen_tsc_alloc(nvc0->screen, tsc);
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tsc->id = nvc0_screen_tsc_alloc(nvc0->screen, tsc);
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@ -984,6 +984,14 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
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}
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}
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}
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}
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if (nvc0->screen->base.class_3d < NVE4_3D_CLASS &&
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nvc0->seamless_cube_map != nvc0->state.seamless_cube_map) {
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nvc0->state.seamless_cube_map = nvc0->seamless_cube_map;
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PUSH_SPACE(push, 1);
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IMMED_NVC0(push, NVC0_3D(TEX_MISC),
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nvc0->seamless_cube_map ? NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP : 0);
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}
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push->kick_notify = nvc0_draw_vbo_kick_notify;
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push->kick_notify = nvc0_draw_vbo_kick_notify;
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for (s = 0; s < 5 && !nvc0->cb_dirty; ++s) {
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for (s = 0; s < 5 && !nvc0->cb_dirty; ++s) {
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