radeonsi/gfx10: emit GE_CNTL instead of IA_MULTI_VGT_PARAM for legacy mode
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
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1ce52c1e37
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@ -620,15 +620,14 @@ static inline bool si_prim_restart_index_changed(struct si_context *sctx,
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sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN);
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}
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static void si_emit_draw_registers(struct si_context *sctx,
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const struct pipe_draw_info *info,
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enum pipe_prim_type prim,
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unsigned num_patches,
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unsigned instance_count,
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bool primitive_restart)
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static void si_emit_ia_multi_vgt_param(struct si_context *sctx,
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const struct pipe_draw_info *info,
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enum pipe_prim_type prim,
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unsigned num_patches,
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unsigned instance_count,
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bool primitive_restart)
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{
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struct radeon_cmdbuf *cs = sctx->gfx_cs;
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unsigned vgt_prim = si_conv_pipe_prim(prim);
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unsigned ia_multi_vgt_param;
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ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, prim, num_patches,
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@ -647,6 +646,60 @@ static void si_emit_draw_registers(struct si_context *sctx,
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sctx->last_multi_vgt_param = ia_multi_vgt_param;
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}
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}
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/* GFX10 removed IA_MULTI_VGT_PARAM in exchange for GE_CNTL.
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* We overload last_multi_vgt_param.
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*/
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static void gfx10_emit_ge_cntl(struct si_context *sctx, unsigned num_patches)
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{
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if (sctx->ngg)
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return; /* set during PM4 emit */
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union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
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unsigned primgroup_size;
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unsigned vertgroup_size;
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if (sctx->tes_shader.cso) {
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primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
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vertgroup_size = 0;
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} else if (sctx->gs_shader.cso) {
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unsigned vgt_gs_onchip_cntl = sctx->gs_shader.current->ctx_reg.gs.vgt_gs_onchip_cntl;
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primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
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vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
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} else {
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primgroup_size = 128; /* recommended without a GS and tess */
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vertgroup_size = 0;
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}
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unsigned ge_cntl =
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S_03096C_PRIM_GRP_SIZE(primgroup_size) |
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S_03096C_VERT_GRP_SIZE(vertgroup_size) |
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S_03096C_PACKET_TO_ONE_PA(key.u.line_stipple_enabled) |
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S_03096C_BREAK_WAVE_AT_EOI(key.u.uses_tess && key.u.tess_uses_prim_id);
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if (ge_cntl != sctx->last_multi_vgt_param) {
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radeon_set_uconfig_reg(sctx->gfx_cs, R_03096C_GE_CNTL, ge_cntl);
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sctx->last_multi_vgt_param = ge_cntl;
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}
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}
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static void si_emit_draw_registers(struct si_context *sctx,
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const struct pipe_draw_info *info,
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enum pipe_prim_type prim,
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unsigned num_patches,
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unsigned instance_count,
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bool primitive_restart)
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{
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struct radeon_cmdbuf *cs = sctx->gfx_cs;
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unsigned vgt_prim = si_conv_pipe_prim(info->mode);
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if (sctx->chip_class >= GFX10)
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gfx10_emit_ge_cntl(sctx, num_patches);
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else
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si_emit_ia_multi_vgt_param(sctx, info, prim, num_patches,
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instance_count, primitive_restart);
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if (vgt_prim != sctx->last_prim) {
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if (sctx->chip_class >= GFX7)
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radeon_set_uconfig_reg_idx(cs, sctx->screen,
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