pan/mdg: Defer modifier packing until emit time
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
This commit is contained in:
Alyssa Rosenzweig
Marge Bot
parent
edf1479bea
commit
1cd65353c9
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@ -508,8 +508,7 @@ void mir_print_instruction(midgard_instruction *ins);
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void mir_print_bundle(midgard_bundle *ctx);
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void mir_print_block(midgard_block *block);
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void mir_print_shader(compiler_context *ctx);
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bool mir_nontrivial_source2_mod(midgard_instruction *ins);
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bool mir_nontrivial_source2_mod_simple(midgard_instruction *ins);
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bool mir_nontrivial_mod(midgard_instruction *ins, unsigned i, bool check_swizzle);
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bool mir_nontrivial_outmod(midgard_instruction *ins);
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void mir_insert_instruction_before_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
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@ -128,44 +128,6 @@ schedule_barrier(compiler_context *ctx)
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#define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
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#define M_STORE(name, T) M_LOAD_STORE(name, true, T)
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/* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
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* the corresponding Midgard source */
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static midgard_vector_alu_src
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vector_alu_modifiers(bool abs, bool neg, bool is_int,
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bool half, bool sext)
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{
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/* Figure out how many components there are so we can adjust.
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* Specifically we want to broadcast the last channel so things like
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* ball2/3 work.
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*/
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midgard_vector_alu_src alu_src = {
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.rep_low = 0,
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.rep_high = 0,
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.half = half
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};
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if (is_int) {
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alu_src.mod = midgard_int_normal;
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/* Sign/zero-extend if needed */
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if (half) {
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alu_src.mod = sext ?
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midgard_int_sign_extend
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: midgard_int_zero_extend;
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}
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/* These should have been lowered away */
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assert(!(abs || neg));
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} else {
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alu_src.mod = (abs << 0) | (neg << 1);
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}
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return alu_src;
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}
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M_LOAD(ld_attr_32, nir_type_uint32);
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M_LOAD(ld_vary_32, nir_type_uint32);
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M_LOAD(ld_ubo_int4, nir_type_uint32);
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@ -582,10 +544,7 @@ nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
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#define ALU_CHECK_CMP(sext) \
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if (src_bitsize == 16 && dst_bitsize == 32) { \
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half_1 = true; \
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half_2 = true; \
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sext_1 = sext; \
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sext_2 = sext; \
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/* inferred */ \
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} else { \
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assert(src_bitsize == dst_bitsize); \
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} \
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@ -766,11 +725,6 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
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midgard_dest_override dest_override =
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midgard_dest_override_none;
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/* Should we use a smaller respective source and sign-extend? */
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bool half_1 = false, sext_1 = false;
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bool half_2 = false, sext_2 = false;
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/* Should we swap arguments? */
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bool flip_src12 = false;
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@ -897,11 +851,6 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
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case nir_op_i2i16:
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case nir_op_i2i32:
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case nir_op_i2i64:
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/* If we end up upscale, we'll need a sign-extend on the
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* operand (the second argument) */
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sext_2 = true;
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/* fallthrough */
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case nir_op_u2u8:
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case nir_op_u2u16:
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case nir_op_u2u32:
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@ -916,8 +865,7 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
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op = midgard_alu_op_imov;
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if (dst_bitsize == (src_bitsize * 2)) {
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/* Converting up */
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half_2 = true;
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/* inferred */
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} else if (src_bitsize == (dst_bitsize * 2)) {
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/* Converting down */
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dest_override = midgard_dest_override_lower;
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@ -972,9 +920,6 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
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/* Midgard can perform certain modifiers on output of an ALU op */
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unsigned outmod = 0;
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bool abs[4] = { false };
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bool neg[4] = { false };
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bool is_int = midgard_is_integer_op(op);
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if (midgard_is_integer_out_op(op)) {
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@ -1030,7 +975,7 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
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if (quirk_flipped_r24) {
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ins.src[0] = ~0;
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mir_copy_src(&ins, instr, 0, 1, &abs[1], &neg[1], &ins.src_invert[1], is_int, broadcast_swizzle);
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mir_copy_src(&ins, instr, 0, 1, &ins.src_abs[1], &ins.src_neg[1], &ins.src_invert[1], is_int, broadcast_swizzle);
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} else {
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for (unsigned i = 0; i < nr_inputs; ++i) {
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unsigned to = i;
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@ -1051,7 +996,7 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
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to = 1 - to;
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}
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mir_copy_src(&ins, instr, i, to, &abs[to], &neg[to], &ins.src_invert[to], is_int, broadcast_swizzle);
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mir_copy_src(&ins, instr, i, to, &ins.src_abs[to], &ins.src_neg[to], &ins.src_invert[to], is_int, broadcast_swizzle);
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/* (!c) ? a : b = c ? b : a */
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if (instr->op == nir_op_b32csel && ins.src_invert[2]) {
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@ -1064,10 +1009,10 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
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if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
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/* Lowered to move */
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if (instr->op == nir_op_fneg)
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neg[1] = !neg[1];
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ins.src_neg[1] ^= true;
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if (instr->op == nir_op_fabs)
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abs[1] = true;
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ins.src_abs[1] = true;
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}
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ins.mask = mask_of(nr_components);
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@ -1077,9 +1022,6 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
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.reg_mode = reg_mode,
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.dest_override = dest_override,
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.outmod = outmod,
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.src1 = vector_alu_srco_unsigned(vector_alu_modifiers(abs[0], neg[0], is_int, half_1, sext_1)),
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.src2 = vector_alu_srco_unsigned(vector_alu_modifiers(abs[1], neg[1], is_int, half_2, sext_2)),
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};
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/* Apply writemask if non-SSA, keeping in mind that we can't write to
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@ -2242,12 +2184,9 @@ embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
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continue;
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}
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/* We don't know how to handle these with a constant */
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if (mir_nontrivial_source2_mod_simple(ins) || src->rep_low || src->rep_high) {
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DBG("Bailing inline constant...\n");
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/* Should've been const folded */
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if (ins->src_abs[1] || ins->src_neg[1])
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continue;
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}
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/* Make sure that the constant is not itself a vector
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* by checking if all accessed values are the same. */
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@ -24,6 +24,38 @@
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#include "compiler.h"
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#include "midgard_ops.h"
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static midgard_int_mod
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mir_get_imod(bool shift, nir_alu_type T, bool half, bool scalar)
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{
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if (!half) {
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assert(!shift);
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/* Sign-extension, really... */
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return scalar ? 0 : midgard_int_normal;
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}
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if (shift)
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return midgard_int_shift;
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if (nir_alu_type_get_base_type(T) == nir_type_int)
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return midgard_int_sign_extend;
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else
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return midgard_int_zero_extend;
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}
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static unsigned
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mir_pack_mod(midgard_instruction *ins, unsigned i, bool scalar)
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{
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bool integer = midgard_is_integer_op(ins->alu.op);
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unsigned base_size = (8 << ins->alu.reg_mode);
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unsigned sz = nir_alu_type_get_type_size(ins->src_types[i]);
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bool half = (sz == (base_size >> 1));
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return integer ?
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mir_get_imod(ins->src_shift[i], ins->src_types[i], half, scalar) :
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((ins->src_abs[i] << 0) |
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((ins->src_neg[i] << 1)));
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}
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/* Midgard IR only knows vector ALU types, but we sometimes need to actually
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* use scalar ALU instructions, for functional or performance reasons. To do
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* this, we just demote vector ALU payloads to scalar. */
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@ -41,39 +73,13 @@ component_from_mask(unsigned mask)
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}
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static unsigned
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vector_to_scalar_source(unsigned u, bool is_int, bool is_full,
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unsigned component)
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mir_pack_scalar_source(unsigned mod, bool is_full, unsigned component)
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{
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midgard_vector_alu_src v;
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memcpy(&v, &u, sizeof(v));
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/* TODO: Integers */
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midgard_scalar_alu_src s = { 0 };
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if (is_full) {
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/* For a 32-bit op, just check the source half flag */
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s.full = !v.half;
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} else if (!v.half) {
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/* For a 16-bit op that's not subdivided, never full */
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s.full = false;
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} else {
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/* We can't do 8-bit scalar, abort! */
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assert(0);
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}
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/* Component indexing takes size into account */
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if (s.full)
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s.component = component << 1;
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else
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s.component = component;
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if (is_int) {
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/* TODO */
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} else {
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s.mod = v.mod;
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}
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midgard_scalar_alu_src s = {
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.mod = mod,
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.full = is_full,
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.component = component << (is_full ? 1 : 0)
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};
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unsigned o;
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memcpy(&o, &s, sizeof(s));
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@ -84,17 +90,22 @@ vector_to_scalar_source(unsigned u, bool is_int, bool is_full,
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static midgard_scalar_alu
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vector_to_scalar_alu(midgard_vector_alu v, midgard_instruction *ins)
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{
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bool is_int = midgard_is_integer_op(v.op);
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bool is_full = v.reg_mode == midgard_reg_mode_32;
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bool is_inline_constant = ins->has_inline_constant;
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bool is_full = nir_alu_type_get_type_size(ins->dest_type) == 32;
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bool half_0 = nir_alu_type_get_type_size(ins->src_types[0]) == 16;
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bool half_1 = nir_alu_type_get_type_size(ins->src_types[1]) == 16;
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unsigned comp = component_from_mask(ins->mask);
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unsigned packed_src[2] = {
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mir_pack_scalar_source(mir_pack_mod(ins, 0, true), !half_0, ins->swizzle[0][comp]),
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mir_pack_scalar_source(mir_pack_mod(ins, 1, true), !half_1, ins->swizzle[1][comp])
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};
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/* The output component is from the mask */
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midgard_scalar_alu s = {
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.op = v.op,
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.src1 = vector_to_scalar_source(v.src1, is_int, is_full, ins->swizzle[0][comp]),
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.src2 = !is_inline_constant ? vector_to_scalar_source(v.src2, is_int, is_full, ins->swizzle[1][comp]) : 0,
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.src1 = packed_src[0],
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.src2 = packed_src[1],
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.unknown = 0,
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.outmod = v.outmod,
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.output_full = is_full,
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@ -175,96 +186,125 @@ mir_pack_mask_alu(midgard_instruction *ins)
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ins->alu.mask = effective;
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}
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static void
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mir_pack_swizzle_alu(midgard_instruction *ins)
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static unsigned
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mir_pack_swizzle(unsigned mask, unsigned *swizzle,
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nir_alu_type T, midgard_reg_mode reg_mode,
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bool op_channeled, bool *rep_low, bool *rep_high)
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{
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midgard_vector_alu_src src[] = {
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vector_alu_from_unsigned(ins->alu.src1),
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vector_alu_from_unsigned(ins->alu.src2)
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};
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unsigned packed = 0;
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unsigned sz = nir_alu_type_get_type_size(T);
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for (unsigned i = 0; i < 2; ++i) {
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unsigned packed = 0;
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if (reg_mode == midgard_reg_mode_64) {
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unsigned components = 64 / sz;
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if (ins->alu.reg_mode == midgard_reg_mode_64) {
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unsigned sz = nir_alu_type_get_type_size(ins->src_types[i]);
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unsigned components = 64 / sz;
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packed = mir_pack_swizzle_64(swizzle, components);
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packed = mir_pack_swizzle_64(ins->swizzle[i], components);
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if (sz == 32) {
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bool lo = swizzle[0] >= COMPONENT_Z;
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bool hi = swizzle[1] >= COMPONENT_Z;
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if (sz == 32) {
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bool lo = ins->swizzle[i][0] >= COMPONENT_Z;
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bool hi = ins->swizzle[i][1] >= COMPONENT_Z;
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unsigned mask = mir_bytemask(ins);
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if (mask & 0x1) {
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/* We can't mix halves... */
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if (mask & 2)
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assert(lo == hi);
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if (mask & 0xFF) {
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/* We can't mix halves... */
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if (mask & 0xFF00)
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assert(lo == hi);
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src[i].rep_low |= lo;
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} else {
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src[i].rep_low |= hi;
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}
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} else if (sz < 32) {
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unreachable("Cannot encode 8/16 swizzle in 64-bit");
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}
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} else {
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/* For 32-bit, swizzle packing is stupid-simple. For 16-bit,
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* the strategy is to check whether the nibble we're on is
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* upper or lower. We need all components to be on the same
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* "side"; that much is enforced by the ISA and should have
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* been lowered. TODO: 8-bit packing. TODO: vec8 */
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unsigned first = ins->mask ? ffs(ins->mask) - 1 : 0;
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bool upper = ins->swizzle[i][first] > 3;
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if (upper && ins->mask)
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assert(nir_alu_type_get_type_size(ins->src_types[i]) <= 16);
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bool dest_up =
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GET_CHANNEL_COUNT(alu_opcode_props[ins->alu.op].props) ? false :
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(first >= 4);
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for (unsigned c = (dest_up ? 4 : 0); c < (dest_up ? 8 : 4); ++c) {
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unsigned v = ins->swizzle[i][c];
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bool t_upper = v > 3;
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/* Ensure we're doing something sane */
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if (ins->mask & (1 << c)) {
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assert(t_upper == upper);
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assert(v <= 7);
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}
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/* Use the non upper part */
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v &= 0x3;
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packed |= v << (2 * (c % 4));
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}
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/* Replicate for now.. should really pick a side for
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* dot products */
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if (ins->alu.reg_mode == midgard_reg_mode_16) {
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src[i].rep_low = !upper;
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src[i].rep_high = upper;
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} else if (ins->alu.reg_mode == midgard_reg_mode_32) {
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src[i].rep_low = upper;
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*rep_low = lo;
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} else {
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unreachable("Unhandled reg mode");
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*rep_low = hi;
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}
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} else if (sz < 32) {
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unreachable("Cannot encode 8/16 swizzle in 64-bit");
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}
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} else {
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/* For 32-bit, swizzle packing is stupid-simple. For 16-bit,
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* the strategy is to check whether the nibble we're on is
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* upper or lower. We need all components to be on the same
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* "side"; that much is enforced by the ISA and should have
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* been lowered. TODO: 8-bit packing. TODO: vec8 */
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unsigned first = mask ? ffs(mask) - 1 : 0;
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bool upper = swizzle[first] > 3;
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if (upper && mask)
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assert(sz <= 16);
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bool dest_up = !op_channeled && (first >= 4);
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for (unsigned c = (dest_up ? 4 : 0); c < (dest_up ? 8 : 4); ++c) {
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unsigned v = swizzle[c];
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bool t_upper = v > 3;
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/* Ensure we're doing something sane */
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if (mask & (1 << c)) {
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assert(t_upper == upper);
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assert(v <= 7);
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}
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/* Use the non upper part */
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v &= 0x3;
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packed |= v << (2 * (c % 4));
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}
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src[i].swizzle = packed;
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/* Replicate for now.. should really pick a side for
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* dot products */
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if (reg_mode == midgard_reg_mode_16) {
|
||||
*rep_low = !upper;
|
||||
*rep_high = upper;
|
||||
} else if (reg_mode == midgard_reg_mode_32) {
|
||||
*rep_low = upper;
|
||||
} else {
|
||||
unreachable("Unhandled reg mode");
|
||||
}
|
||||
}
|
||||
|
||||
ins->alu.src1 = vector_alu_srco_unsigned(src[0]);
|
||||
return packed;
|
||||
}
|
||||
|
||||
if (!ins->has_inline_constant)
|
||||
ins->alu.src2 = vector_alu_srco_unsigned(src[1]);
|
||||
static void
|
||||
mir_pack_vector_srcs(midgard_instruction *ins)
|
||||
{
|
||||
bool channeled = GET_CHANNEL_COUNT(alu_opcode_props[ins->alu.op].props);
|
||||
|
||||
midgard_reg_mode mode = ins->alu.reg_mode;
|
||||
unsigned base_size = (8 << mode);
|
||||
|
||||
for (unsigned i = 0; i < 2; ++i) {
|
||||
if (ins->has_inline_constant && (i == 1))
|
||||
continue;
|
||||
|
||||
if (ins->src[i] == ~0)
|
||||
continue;
|
||||
|
||||
bool rep_lo = false, rep_hi = false;
|
||||
unsigned sz = nir_alu_type_get_type_size(ins->src_types[i]);
|
||||
bool half = (sz == (base_size >> 1));
|
||||
|
||||
assert((sz == base_size) || half);
|
||||
|
||||
unsigned swizzle = mir_pack_swizzle(ins->mask, ins->swizzle[i],
|
||||
ins->src_types[i], ins->alu.reg_mode,
|
||||
channeled, &rep_lo, &rep_hi);
|
||||
|
||||
midgard_vector_alu_src pack = {
|
||||
.mod = mir_pack_mod(ins, i, false),
|
||||
.rep_low = rep_lo,
|
||||
.rep_high = rep_hi,
|
||||
.half = half,
|
||||
.swizzle = swizzle
|
||||
};
|
||||
|
||||
unsigned p = vector_alu_srco_unsigned(pack);
|
||||
|
||||
if (i == 0)
|
||||
ins->alu.src1 = p;
|
||||
else
|
||||
ins->alu.src2 = p;
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
@ -421,7 +461,7 @@ emit_alu_bundle(compiler_context *ctx,
|
|||
|
||||
if (ins->unit & UNITS_ANY_VECTOR) {
|
||||
mir_pack_mask_alu(ins);
|
||||
mir_pack_swizzle_alu(ins);
|
||||
mir_pack_vector_srcs(ins);
|
||||
size = sizeof(midgard_vector_alu);
|
||||
source = &ins->alu;
|
||||
} else if (ins->unit == ALU_ENAB_BR_COMPACT) {
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@ midgard_opt_copy_prop_reg(compiler_context *ctx, midgard_block *block)
|
|||
|
||||
if (ins->has_inline_constant) continue;
|
||||
if (ins->has_constants) continue;
|
||||
if (mir_nontrivial_source2_mod(ins)) continue;
|
||||
if (mir_nontrivial_mod(ins, 1, true)) continue;
|
||||
if (mir_nontrivial_outmod(ins)) continue;
|
||||
if (!mir_single_use(ctx, from)) continue;
|
||||
|
||||
|
|
@ -82,7 +82,7 @@ midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block)
|
|||
if (ins->has_constants) continue;
|
||||
|
||||
/* Modifier propagation is not handled here */
|
||||
if (mir_nontrivial_source2_mod_simple(ins)) continue;
|
||||
if (mir_nontrivial_mod(ins, 1, false)) continue;
|
||||
if (mir_nontrivial_outmod(ins)) continue;
|
||||
|
||||
/* Shortened arguments (bias for textures, extra load/store
|
||||
|
|
|
|||
|
|
@ -106,53 +106,30 @@ mir_single_use(compiler_context *ctx, unsigned value)
|
|||
return mir_use_count(ctx, value) <= 1;
|
||||
}
|
||||
|
||||
static bool
|
||||
mir_nontrivial_raw_mod(midgard_vector_alu_src src, bool is_int)
|
||||
bool
|
||||
mir_nontrivial_mod(midgard_instruction *ins, unsigned i, bool check_swizzle)
|
||||
{
|
||||
if (is_int)
|
||||
return src.mod == midgard_int_shift;
|
||||
else
|
||||
return src.mod;
|
||||
}
|
||||
bool is_int = midgard_is_integer_op(ins->alu.op);
|
||||
|
||||
static bool
|
||||
mir_nontrivial_mod(midgard_vector_alu_src src, bool is_int, unsigned mask, unsigned *swizzle)
|
||||
{
|
||||
if (mir_nontrivial_raw_mod(src, is_int)) return true;
|
||||
if (is_int) {
|
||||
if (ins->src_shift[i]) return true;
|
||||
} else {
|
||||
if (ins->src_neg[i]) return true;
|
||||
if (ins->src_abs[i]) return true;
|
||||
}
|
||||
|
||||
/* size-conversion */
|
||||
if (src.half) return true;
|
||||
if (ins->dest_type != ins->src_types[i]) return true;
|
||||
|
||||
for (unsigned c = 0; c < 16; ++c) {
|
||||
if (!(mask & (1 << c))) continue;
|
||||
if (swizzle[c] != c) return true;
|
||||
if (check_swizzle) {
|
||||
for (unsigned c = 0; c < 16; ++c) {
|
||||
if (!(ins->mask & (1 << c))) continue;
|
||||
if (ins->swizzle[i][c] != c) return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
bool
|
||||
mir_nontrivial_source2_mod(midgard_instruction *ins)
|
||||
{
|
||||
bool is_int = midgard_is_integer_op(ins->alu.op);
|
||||
|
||||
midgard_vector_alu_src src2 =
|
||||
vector_alu_from_unsigned(ins->alu.src2);
|
||||
|
||||
return mir_nontrivial_mod(src2, is_int, ins->mask, ins->swizzle[1]);
|
||||
}
|
||||
|
||||
bool
|
||||
mir_nontrivial_source2_mod_simple(midgard_instruction *ins)
|
||||
{
|
||||
bool is_int = midgard_is_integer_op(ins->alu.op);
|
||||
|
||||
midgard_vector_alu_src src2 =
|
||||
vector_alu_from_unsigned(ins->alu.src2);
|
||||
|
||||
return mir_nontrivial_raw_mod(src2, is_int) || src2.half;
|
||||
}
|
||||
|
||||
bool
|
||||
mir_nontrivial_outmod(midgard_instruction *ins)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in New Issue