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radeonsi/gfx10: set the correct value for OFFCHIP_BUFFERING 

Copied from PAL. Higher values break tessellation, which I was only able
to reproduce with register shadowing enabled.

Fixes: 0bf3e6fae7 "radeonsi/gfx10: double the number of tessellation offchip buffers per SE"

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>
This commit is contained in:
Marek Olšák 2020-07-06 23:51:25 -04:00
parent d244a25c07
commit 1c6eca23fd
1 changed files with 1 additions and 1 deletions
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2
src/gallium/drivers/radeonsi/si_pipe.c
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@ -1081,7 +1081,7 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws,
unsigned max_offchip_buffers_per_se;
if (sscreen->info.chip_class >= GFX10)
max_offchip_buffers_per_se = 256;
max_offchip_buffers_per_se = 128;
/* Only certain chips can use the maximum value. */
else if (sscreen->info.family == CHIP_VEGA12 || sscreen->info.family == CHIP_VEGA20)
max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;