ir3/legalize: Switch to srcs/dsts arrays
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
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@ -147,7 +147,7 @@ legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block)
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continue;
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if (is_input(n)) {
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struct ir3_register *inloc = n->regs[1];
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struct ir3_register *inloc = n->srcs[0];
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assert(inloc->flags & IR3_REG_IMMED);
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ctx->max_bary = MAX2(ctx->max_bary, inloc->iim_val);
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}
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@ -172,8 +172,12 @@ legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block)
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* that writes the same register can race w/ the sam instr
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* resulting in undefined results:
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*/
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for (i = 0; i < n->regs_count; i++) {
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struct ir3_register *reg = n->regs[i];
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for (i = 0; i < n->dsts_count + n->srcs_count; i++) {
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struct ir3_register *reg;
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if (i < n->dsts_count)
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reg = n->dsts[i];
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else
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reg = n->srcs[i - n->dsts_count];
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if (reg_gpr(reg)) {
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@ -202,8 +206,8 @@ legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block)
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last_rel = n;
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}
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if (n->regs_count > 0) {
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struct ir3_register *reg = n->regs[0];
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if (n->dsts_count > 0) {
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struct ir3_register *reg = n->dsts[0];
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if (regmask_get(&state->needs_ss_war, reg)) {
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n->flags |= IR3_INSTR_SS;
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last_input_needs_ss = false;
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@ -251,14 +255,14 @@ legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block)
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}
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if (is_sfu(n))
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regmask_set(&state->needs_ss, n->regs[0]);
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regmask_set(&state->needs_ss, n->dsts[0]);
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if (is_tex_or_prefetch(n)) {
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regmask_set(&state->needs_sy, n->regs[0]);
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regmask_set(&state->needs_sy, n->dsts[0]);
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if (n->opc == OPC_META_TEX_PREFETCH)
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has_tex_prefetch = true;
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} else if (n->opc == OPC_RESINFO) {
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regmask_set(&state->needs_ss, n->regs[0]);
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regmask_set(&state->needs_ss, n->dsts[0]);
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ir3_NOP(block)->flags |= IR3_INSTR_SS;
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last_input_needs_ss = false;
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} else if (is_load(n)) {
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@ -266,19 +270,19 @@ legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block)
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* makes a bunch of flat-varying tests start working on a4xx.
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*/
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if ((n->opc == OPC_LDLV) || (n->opc == OPC_LDL) || (n->opc == OPC_LDLW))
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regmask_set(&state->needs_ss, n->regs[0]);
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regmask_set(&state->needs_ss, n->dsts[0]);
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else
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regmask_set(&state->needs_sy, n->regs[0]);
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regmask_set(&state->needs_sy, n->dsts[0]);
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} else if (is_atomic(n->opc)) {
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if (n->flags & IR3_INSTR_G) {
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if (ctx->compiler->gpu_id >= 600) {
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/* New encoding, returns result via second src: */
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regmask_set(&state->needs_sy, n->regs[3]);
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regmask_set(&state->needs_sy, n->srcs[2]);
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} else {
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regmask_set(&state->needs_sy, n->regs[0]);
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regmask_set(&state->needs_sy, n->dsts[0]);
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}
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} else {
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regmask_set(&state->needs_ss, n->regs[0]);
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regmask_set(&state->needs_ss, n->dsts[0]);
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}
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}
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@ -321,7 +325,7 @@ legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block)
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last_input = baryf;
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}
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last_input->regs[0]->flags |= IR3_REG_EI;
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last_input->dsts[0]->flags |= IR3_REG_EI;
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if (last_input_needs_ss) {
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last_input->flags |= IR3_INSTR_SS;
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regmask_init(&state->needs_ss_war, mergedregs);
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@ -629,14 +633,14 @@ block_sched(struct ir3 *ir)
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*/
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br = ir3_instr_create(block, OPC_B, 1, 1);
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ir3_dst_create(br, INVALID_REG, 0);
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ir3_src_create(br, regid(REG_P0, 0), 0)->def = block->condition->regs[0];
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ir3_src_create(br, regid(REG_P0, 0), 0)->def = block->condition->dsts[0];
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br->cat0.inv1 = true;
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br->cat0.target = block->successors[1];
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/* "then" branch: */
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br = ir3_instr_create(block, OPC_B, 1, 1);
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ir3_dst_create(br, INVALID_REG, 0);
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ir3_src_create(br, regid(REG_P0, 0), 0)->def = block->condition->regs[0];
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ir3_src_create(br, regid(REG_P0, 0), 0)->def = block->condition->dsts[0];
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br->cat0.target = block->successors[0];
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} else if (block->successors[0]) {
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@ -692,7 +696,7 @@ kill_sched(struct ir3 *ir, struct ir3_shader_variant *so)
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struct ir3_instruction *br = ir3_instr_create(block, OPC_B, 1, 1);
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ir3_dst_create(br, INVALID_REG, 0);
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ir3_src_create(br, instr->regs[1]->num, instr->regs[1]->flags)->wrmask = 1;
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ir3_src_create(br, instr->srcs[0]->num, instr->srcs[0]->flags)->wrmask = 1;
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br->cat0.target =
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list_last_entry(&ir->block_list, struct ir3_block, node);
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