zink: implement streamout and xfb handling in ntv
this translates streamout info into xfb decorations and adds some workaround handling for spurious gl_PointSize values partly based on patches originally written by Dave Airlie <airlied@redhat.com> Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5163>
This commit is contained in:
Mike Blumenkrantz
Marge Bot
parent
c3f6a59d57
commit
1b130c42b8
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@ -111,6 +111,10 @@ struct ntv_context {
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size_t num_regs;
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struct hash_table *vars; /* nir_variable -> SpvId */
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struct hash_table *so_outputs; /* pipe_stream_output -> SpvId */
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unsigned outputs[VARYING_SLOT_MAX];
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const struct glsl_type *so_output_gl_types[VARYING_SLOT_MAX];
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SpvId so_output_types[VARYING_SLOT_MAX];
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const SpvId *block_ids;
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size_t num_blocks;
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@ -353,7 +357,6 @@ emit_output(struct ntv_context *ctx, struct nir_variable *var)
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if (ctx->stage == MESA_SHADER_VERTEX) {
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unsigned slot = var->data.location;
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switch (slot) {
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HANDLE_EMIT_BUILTIN(POS, Position);
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@ -368,6 +371,10 @@ emit_output(struct ntv_context *ctx, struct nir_variable *var)
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case VARYING_SLOT_CLIP_DIST0:
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assert(glsl_type_is_array(var->type));
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spirv_builder_emit_builtin(&ctx->builder, var_id, SpvBuiltInClipDistance);
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/* this can be as large as 2x vec4, which requires 2 slots */
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ctx->outputs[VARYING_SLOT_CLIP_DIST1] = var_id;
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ctx->so_output_gl_types[VARYING_SLOT_CLIP_DIST1] = var->type;
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ctx->so_output_types[VARYING_SLOT_CLIP_DIST1] = var_type;
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break;
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default:
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@ -383,6 +390,9 @@ emit_output(struct ntv_context *ctx, struct nir_variable *var)
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* use driver_location for non-builtins with defined slots to avoid overlap
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*/
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}
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ctx->outputs[var->data.location] = var_id;
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ctx->so_output_gl_types[var->data.location] = var->type;
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ctx->so_output_types[var->data.location] = var_type;
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} else if (ctx->stage == MESA_SHADER_FRAGMENT) {
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if (var->data.location >= FRAG_RESULT_DATA0)
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spirv_builder_emit_location(&ctx->builder, var_id,
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@ -823,6 +833,167 @@ emit_unop(struct ntv_context *ctx, SpvOp op, SpvId type, SpvId src)
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return spirv_builder_emit_unop(&ctx->builder, op, type, src);
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}
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/* return the intended xfb output vec type based on base type and vector size */
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static SpvId
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get_output_type(struct ntv_context *ctx, unsigned register_index, unsigned num_components)
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{
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const struct glsl_type *out_type = ctx->so_output_gl_types[register_index];
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enum glsl_base_type base_type = glsl_get_base_type(out_type);
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if (base_type == GLSL_TYPE_ARRAY)
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base_type = glsl_get_base_type(glsl_without_array(out_type));
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switch (base_type) {
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case GLSL_TYPE_BOOL:
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return get_bvec_type(ctx, num_components);
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case GLSL_TYPE_FLOAT:
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return get_fvec_type(ctx, 32, num_components);
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case GLSL_TYPE_INT:
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return get_ivec_type(ctx, 32, num_components);
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case GLSL_TYPE_UINT:
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return get_uvec_type(ctx, 32, num_components);
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default:
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break;
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}
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unreachable("unknown type");
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return 0;
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}
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/* for streamout create new outputs, as streamout can be done on individual components,
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from complete outputs, so we just can't use the created packed outputs */
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static void
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emit_so_info(struct ntv_context *ctx, unsigned max_output_location,
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const struct pipe_stream_output_info *so_info, struct pipe_stream_output_info *local_so_info)
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{
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for (unsigned i = 0; i < local_so_info->num_outputs; i++) {
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struct pipe_stream_output so_output = local_so_info->output[i];
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SpvId out_type = get_output_type(ctx, so_output.register_index, so_output.num_components);
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SpvId pointer_type = spirv_builder_type_pointer(&ctx->builder,
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SpvStorageClassOutput,
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out_type);
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SpvId var_id = spirv_builder_emit_var(&ctx->builder, pointer_type,
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SpvStorageClassOutput);
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char name[10];
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snprintf(name, 10, "xfb%d", i);
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spirv_builder_emit_name(&ctx->builder, var_id, name);
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spirv_builder_emit_offset(&ctx->builder, var_id, (so_output.dst_offset * 4));
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spirv_builder_emit_xfb_buffer(&ctx->builder, var_id, so_output.output_buffer);
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spirv_builder_emit_xfb_stride(&ctx->builder, var_id, so_info->stride[so_output.output_buffer] * 4);
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/* output location is incremented by VARYING_SLOT_VAR0 for non-builtins in vtn,
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* so we need to ensure that the new xfb location slot doesn't conflict with any previously-emitted
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* outputs.
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*
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* if there's no previous outputs that take up user slots (VAR0+) then we can start right after the
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* glsl builtin reserved slots, otherwise we start just after the adjusted user output slot
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*/
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uint32_t location = NTV_MIN_RESERVED_SLOTS + i;
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if (max_output_location >= VARYING_SLOT_VAR0)
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location = max_output_location - VARYING_SLOT_VAR0 + 1 + i;
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assert(location < VARYING_SLOT_VAR0);
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spirv_builder_emit_location(&ctx->builder, var_id, location);
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/* note: gl_ClipDistance[4] can the 0-indexed member of VARYING_SLOT_CLIP_DIST1 here,
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* so this is still the 0 component
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*/
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if (so_output.start_component)
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spirv_builder_emit_component(&ctx->builder, var_id, so_output.start_component);
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uint32_t *key = ralloc_size(NULL, sizeof(uint32_t));
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*key = (uint32_t)so_output.register_index << 2 | so_output.start_component;
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_mesa_hash_table_insert(ctx->so_outputs, key, (void *)(intptr_t)var_id);
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assert(ctx->num_entry_ifaces < ARRAY_SIZE(ctx->entry_ifaces));
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ctx->entry_ifaces[ctx->num_entry_ifaces++] = var_id;
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}
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}
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static void
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emit_so_outputs(struct ntv_context *ctx,
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const struct pipe_stream_output_info *so_info, struct pipe_stream_output_info *local_so_info)
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{
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SpvId loaded_outputs[VARYING_SLOT_MAX] = {};
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for (unsigned i = 0; i < local_so_info->num_outputs; i++) {
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uint32_t components[NIR_MAX_VEC_COMPONENTS];
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struct pipe_stream_output so_output = local_so_info->output[i];
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uint32_t so_key = (uint32_t) so_output.register_index << 2 | so_output.start_component;
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struct hash_entry *he = _mesa_hash_table_search(ctx->so_outputs, &so_key);
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assert(he);
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SpvId so_output_var_id = (SpvId)(intptr_t)he->data;
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SpvId type = get_output_type(ctx, so_output.register_index, so_output.num_components);
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SpvId output = ctx->outputs[so_output.register_index];
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SpvId output_type = ctx->so_output_types[so_output.register_index];
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const struct glsl_type *out_type = ctx->so_output_gl_types[so_output.register_index];
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if (!loaded_outputs[so_output.register_index])
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loaded_outputs[so_output.register_index] = spirv_builder_emit_load(&ctx->builder, output_type, output);
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SpvId src = loaded_outputs[so_output.register_index];
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SpvId result;
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for (unsigned c = 0; c < so_output.num_components; c++) {
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components[c] = so_output.start_component + c;
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/* this is the second half of a 2 * vec4 array */
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if (ctx->stage == MESA_SHADER_VERTEX && so_output.register_index == VARYING_SLOT_CLIP_DIST1)
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components[c] += 4;
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}
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/* if we're emitting a scalar or the type we're emitting matches the output's original type and we're
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* emitting the same number of components, then we can skip any sort of conversion here
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*/
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if (glsl_type_is_scalar(out_type) || (type == output_type && glsl_get_length(out_type) == so_output.num_components))
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result = src;
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else {
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if (ctx->stage == MESA_SHADER_VERTEX && so_output.register_index == VARYING_SLOT_POS) {
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/* gl_Position was modified by nir_lower_clip_halfz, so we need to reverse that for streamout here:
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*
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* opengl gl_Position.z = (vulkan gl_Position.z * 2.0) - vulkan gl_Position.w
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*
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* to do this, we extract the z and w components, perform the multiply and subtract ops, then reinsert
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*/
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uint32_t z_component[] = {2};
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uint32_t w_component[] = {3};
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SpvId ftype = spirv_builder_type_float(&ctx->builder, 32);
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SpvId z = spirv_builder_emit_composite_extract(&ctx->builder, ftype, src, z_component, 1);
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SpvId w = spirv_builder_emit_composite_extract(&ctx->builder, ftype, src, w_component, 1);
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SpvId new_z = emit_binop(ctx, SpvOpFMul, ftype, z, spirv_builder_const_float(&ctx->builder, 32, 2.0));
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new_z = emit_binop(ctx, SpvOpFSub, ftype, new_z, w);
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src = spirv_builder_emit_vector_insert(&ctx->builder, type, src, new_z, 2);
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}
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/* OpCompositeExtract can only extract scalars for our use here */
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if (so_output.num_components == 1) {
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result = spirv_builder_emit_composite_extract(&ctx->builder, type, src, components, so_output.num_components);
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} else if (glsl_type_is_vector(out_type)) {
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/* OpVectorShuffle can select vector members into a differently-sized vector */
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result = spirv_builder_emit_vector_shuffle(&ctx->builder, type,
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src, src,
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components, so_output.num_components);
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result = emit_unop(ctx, SpvOpBitcast, type, result);
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} else {
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/* for arrays, we need to manually extract each desired member
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* and re-pack them into the desired output type
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*/
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for (unsigned c = 0; c < so_output.num_components; c++) {
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uint32_t member[] = { so_output.start_component + c };
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SpvId base_type = get_glsl_type(ctx, glsl_without_array(out_type));
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if (ctx->stage == MESA_SHADER_VERTEX && so_output.register_index == VARYING_SLOT_CLIP_DIST1)
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member[0] += 4;
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components[c] = spirv_builder_emit_composite_extract(&ctx->builder, base_type, src, member, 1);
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}
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result = spirv_builder_emit_composite_construct(&ctx->builder, type, components, so_output.num_components);
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}
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}
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spirv_builder_emit_store(&ctx->builder, so_output_var_id, result);
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}
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}
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static SpvId
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emit_binop(struct ntv_context *ctx, SpvOp op, SpvId type,
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SpvId src0, SpvId src1)
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@ -1988,7 +2159,7 @@ emit_cf_list(struct ntv_context *ctx, struct exec_list *list)
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}
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struct spirv_shader *
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nir_to_spirv(struct nir_shader *s)
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nir_to_spirv(struct nir_shader *s, const struct pipe_stream_output_info *so_info, struct pipe_stream_output_info *local_so_info)
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{
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struct spirv_shader *ret = NULL;
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@ -2061,12 +2232,17 @@ nir_to_spirv(struct nir_shader *s)
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ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
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_mesa_key_pointer_equal);
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ctx.so_outputs = _mesa_hash_table_create(NULL, _mesa_hash_u32,
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_mesa_key_u32_equal);
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nir_foreach_variable(var, &s->inputs)
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emit_input(&ctx, var);
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nir_foreach_variable(var, &s->outputs)
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emit_output(&ctx, var);
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if (so_info)
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emit_so_info(&ctx, util_last_bit64(s->info.outputs_written), so_info, local_so_info);
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nir_foreach_variable(var, &s->uniforms)
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emit_uniform(&ctx, var);
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@ -2078,6 +2254,11 @@ nir_to_spirv(struct nir_shader *s)
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SpvExecutionModeDepthReplacing);
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}
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if (so_info && so_info->num_outputs) {
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spirv_builder_emit_cap(&ctx.builder, SpvCapabilityTransformFeedback);
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spirv_builder_emit_exec_mode(&ctx.builder, entry_point,
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SpvExecutionModeXfb);
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}
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spirv_builder_function(&ctx.builder, entry_point, type_void,
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SpvFunctionControlMaskNone,
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@ -2124,6 +2305,9 @@ nir_to_spirv(struct nir_shader *s)
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free(ctx.defs);
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if (so_info)
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emit_so_outputs(&ctx, so_info, local_so_info);
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spirv_builder_return(&ctx.builder); // doesn't belong here, but whatevz
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spirv_builder_function_end(&ctx.builder);
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@ -2154,6 +2338,9 @@ fail:
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if (ctx.vars)
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_mesa_hash_table_destroy(ctx.vars, NULL);
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if (ctx.so_outputs)
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_mesa_hash_table_destroy(ctx.so_outputs, NULL);
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return NULL;
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}
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@ -36,9 +36,10 @@ struct spirv_shader {
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};
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struct nir_shader;
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struct pipe_stream_output_info;
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struct spirv_shader *
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nir_to_spirv(struct nir_shader *s);
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nir_to_spirv(struct nir_shader *s, const struct pipe_stream_output_info *so_info, struct pipe_stream_output_info *local_so_info);
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void
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spirv_shader_delete(struct spirv_shader *s);
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@ -132,15 +132,55 @@ optimize_nir(struct nir_shader *s)
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} while (progress);
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}
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/* check for a genuine gl_PointSize output vs one from nir_lower_point_size_mov */
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static bool
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check_psiz(struct nir_shader *s)
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{
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nir_foreach_variable(var, &s->outputs) {
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if (var->data.location == VARYING_SLOT_PSIZ) {
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/* genuine PSIZ outputs will have this set */
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return !!var->data.explicit_location;
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}
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}
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return false;
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}
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/* semi-copied from iris */
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static void
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update_so_info(struct pipe_stream_output_info *so_info,
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uint64_t outputs_written, bool have_psiz)
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{
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uint8_t reverse_map[64] = {};
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unsigned slot = 0;
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while (outputs_written) {
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int bit = u_bit_scan64(&outputs_written);
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/* PSIZ from nir_lower_point_size_mov breaks stream output, so always skip it */
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if (bit == VARYING_SLOT_PSIZ && !have_psiz)
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continue;
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reverse_map[slot++] = bit;
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}
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for (unsigned i = 0; i < so_info->num_outputs; i++) {
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struct pipe_stream_output *output = &so_info->output[i];
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/* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
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output->register_index = reverse_map[output->register_index];
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}
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}
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struct zink_shader *
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zink_compile_nir(struct zink_screen *screen, struct nir_shader *nir)
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zink_compile_nir(struct zink_screen *screen, struct nir_shader *nir,
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const struct pipe_stream_output_info *so_info)
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{
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struct zink_shader *ret = CALLOC_STRUCT(zink_shader);
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bool have_psiz = false;
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ret->programs = _mesa_pointer_set_create(NULL);
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NIR_PASS_V(nir, nir_lower_uniforms_to_ubo, 1);
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NIR_PASS_V(nir, nir_lower_clip_halfz);
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if (nir->info.stage == MESA_SHADER_VERTEX)
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have_psiz = check_psiz(nir);
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NIR_PASS_V(nir, nir_lower_regs_to_ssa);
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optimize_nir(nir);
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NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_function_temp, NULL);
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@ -189,8 +229,12 @@ zink_compile_nir(struct zink_screen *screen, struct nir_shader *nir)
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}
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ret->info = nir->info;
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if (so_info) {
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memcpy(&ret->stream_output, so_info, sizeof(ret->stream_output));
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update_so_info(&ret->stream_output, nir->info.outputs_written, have_psiz);
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}
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struct spirv_shader *spirv = nir_to_spirv(nir);
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struct spirv_shader *spirv = nir_to_spirv(nir, so_info, so_info ? &ret->stream_output : NULL);
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assert(spirv);
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if (zink_debug & ZINK_DEBUG_SPIRV) {
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@ -65,7 +65,8 @@ struct zink_shader {
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};
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struct zink_shader *
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zink_compile_nir(struct zink_screen *screen, struct nir_shader *nir);
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zink_compile_nir(struct zink_screen *screen, struct nir_shader *nir,
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const struct pipe_stream_output_info *so_info);
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void
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zink_shader_free(struct zink_screen *screen, struct zink_shader *shader);
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@ -296,7 +296,7 @@ zink_create_vs_state(struct pipe_context *pctx,
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else
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nir = (struct nir_shader *)shader->ir.nir;
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return zink_compile_nir(zink_screen(pctx->screen), nir);
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return zink_compile_nir(zink_screen(pctx->screen), nir, &shader->stream_output);
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}
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static void
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@ -332,7 +332,7 @@ zink_create_fs_state(struct pipe_context *pctx,
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else
|
||||
nir = (struct nir_shader *)shader->ir.nir;
|
||||
|
||||
return zink_compile_nir(zink_screen(pctx->screen), nir);
|
||||
return zink_compile_nir(zink_screen(pctx->screen), nir, NULL);
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
|
|||
Loading…
Reference in New Issue