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radeonsi: disable CE by default 

It makes performance worse by a very small (hard to measure) amount.
We've done extensive profiling of this feature internally.

Cc: 17.1 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Christian König <christian.koenig@amd.com>
This commit is contained in:
Marek Olšák 2017-08-13 19:22:06 +02:00
parent e0edfadec8
commit 1ab7fed707
3 changed files with 21 additions and 8 deletions
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1
src/gallium/drivers/radeon/r600_pipe_common.c
View File

@ -775,6 +775,7 @@ static const struct debug_named_value common_debug_options[] = {
{ "norbplus", DBG_NO_RB_PLUS, "Disable RB+." },
{ "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
{ "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders compiled on demand" },
{ "ce", DBG_CE, "Force enable the constant engine" },
{ "noce", DBG_NO_CE, "Disable the constant engine"},
{ "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
{ "nodccfb", DBG_NO_DCC_FB, "Disable separate DCC on the main framebuffer" },

4
src/gallium/drivers/radeon/r600_pipe_common.h
View File

@ -65,12 +65,12 @@
#define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
/* Debug flags. */
/* logging */
/* logging and features */
#define DBG_TEX (1 << 0)
#define DBG_NIR (1 << 1)
#define DBG_COMPUTE (1 << 2)
#define DBG_VM (1 << 3)
/* gap - reuse */
#define DBG_CE (1 << 4)
/* shader logging */
#define DBG_FS (1 << 5)
#define DBG_VS (1 << 6)

24
src/gallium/drivers/radeonsi/si_pipe.c
View File

@ -201,12 +201,24 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
si_context_gfx_flush, sctx);
/* SI + AMDGPU + CE = GPU hang */
if (!(sscreen->b.debug_flags & DBG_NO_CE) && ws->cs_add_const_ib &&
sscreen->b.chip_class != SI &&
/* These can't use CE due to a power gating bug in the kernel. */
sscreen->b.family != CHIP_CARRIZO &&
sscreen->b.family != CHIP_STONEY) {
bool enable_ce = sscreen->b.chip_class != SI && /* SI hangs */
/* These can't use CE due to a power gating bug in the kernel. */
sscreen->b.family != CHIP_CARRIZO &&
sscreen->b.family != CHIP_STONEY;
/* CE is currently disabled by default, because it makes s_load latency
* worse, because CE IB doesn't run in lockstep with DE.
* Remove this line after that performance issue has been resolved.
*/
enable_ce = false;
/* Apply CE overrides. */
if (sscreen->b.debug_flags & DBG_NO_CE)
enable_ce = false;
else if (sscreen->b.debug_flags & DBG_CE)
enable_ce = true;
if (ws->cs_add_const_ib && enable_ce) {
sctx->ce_ib = ws->cs_add_const_ib(sctx->b.gfx.cs);
if (!sctx->ce_ib)
goto fail;