mesa, i965: prepare for more than 8 texture targets

3-bit fields are used store texture target in several places.  That will fail
when TEXTURE_EXTERNAL_INDEX, which happends to be the 9th texture target, is
added.  Make them 4-bit fields.

Reviewed-by: Brian Paul <brianp@vmware.com>
Acked-by: Jakob Bornecrantz <jakob@vmware.com>

src/mesa/drivers/dri/i965/brw_wm.h

@@ -156,7 +156,7 @@ struct brw_wm_instruction {
    GLuint saturate:1;
    GLuint writemask:4;
    GLuint tex_unit:4;   /* texture unit for TEX, TXD, TXP instructions */
-   GLuint tex_idx:3;    /* TEXTURE_1D,2D,3D,CUBE,RECT_INDEX source target */
+   GLuint tex_idx:4;    /* TEXTURE_1D,2D,3D,CUBE,RECT_INDEX source target */
    GLuint tex_shadow:1; /* do shadow comparison? */
    GLuint eot:1;    	/* End of thread indicator for FB_WRITE*/
    GLuint target:10;    /* target binding table index for FB_WRITE*/

src/mesa/main/ff_fragment_shader.cpp

@@ -108,7 +108,7 @@ struct state_key {
    /* NOTE: This array of structs must be last! (see "keySize" below) */
    struct {
       GLuint enabled:1;
-      GLuint source_index:3;   /**< TEXTURE_x_INDEX */
+      GLuint source_index:4;   /**< TEXTURE_x_INDEX */
       GLuint shadow:1;
       GLuint ScaleShiftRGB:2;
       GLuint ScaleShiftA:2;

src/mesa/program/prog_instruction.h

@@ -392,7 +392,7 @@ struct prog_instruction
    GLuint TexSrcUnit:5;
 
    /** Source texture target, one of TEXTURE_{1D,2D,3D,CUBE,RECT}_INDEX */
-   GLuint TexSrcTarget:3;
+   GLuint TexSrcTarget:4;
 
    /** True if tex instruction should do shadow comparison */
    GLuint TexShadow:1;

src/mesa/program/program.c

@@ -78,7 +78,7 @@ _mesa_init_program(struct gl_context *ctx)
    ASSERT(MAX_TEXTURE_UNITS <= (1 << 5));
 
    /* If this fails, increase prog_instruction::TexSrcTarget size */
-   ASSERT(NUM_TEXTURE_TARGETS <= (1 << 3));
+   ASSERT(NUM_TEXTURE_TARGETS <= (1 << 4));
 
    ctx->Program.ErrorPos = -1;
    ctx->Program.ErrorString = _mesa_strdup("");