radv: remove useless push constants data when resolving ds attachments
Depth/stencil resolves are only allowed inside a subpass, which means the offset is always 0 and the draw/dispatch covers the whole image. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8127>
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@ -181,12 +181,9 @@ build_depth_stencil_resolve_compute_shader(struct radv_device *dev, int samples,
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nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
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nir_ssa_def *layer_id = nir_channel(&b, wg_id, 2);
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nir_ssa_def *src_offset = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), .range=16);
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nir_ssa_def *dst_offset = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 8), .range=16);
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nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, global_id, src_offset), 0x3);
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img_coord = nir_vec3(&b, nir_channel(&b, img_coord, 0),
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nir_channel(&b, img_coord, 1), layer_id);
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nir_ssa_def *img_coord = nir_vec3(&b, nir_channel(&b, global_id, 0),
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nir_channel(&b, global_id, 1),
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layer_id);
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nir_ssa_def *input_img_deref = &nir_build_deref_var(&b, input_img)->dest.ssa;
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@ -254,11 +251,10 @@ build_depth_stencil_resolve_compute_shader(struct radv_device *dev, int samples,
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outval = nir_fdiv(&b, outval, nir_imm_float(&b, samples));
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}
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nir_ssa_def *coord = nir_channels(&b, nir_iadd(&b, global_id, dst_offset), 0x3);
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coord = nir_vec4(&b, nir_channel(&b, coord, 0),
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nir_channel(&b, coord, 1),
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layer_id,
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nir_imm_int(&b, 0));
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nir_ssa_def *coord = nir_vec4(&b, nir_channel(&b, img_coord, 0),
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nir_channel(&b, img_coord, 1),
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nir_channel(&b, img_coord, 2),
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nir_imm_int(&b, 0));
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nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa,
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coord, nir_ssa_undef(&b, 1, 32), outval, nir_imm_int(&b, 0));
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return b.shader;
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@ -666,8 +662,6 @@ static void
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emit_depth_stencil_resolve(struct radv_cmd_buffer *cmd_buffer,
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struct radv_image_view *src_iview,
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struct radv_image_view *dest_iview,
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const VkOffset2D *src_offset,
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const VkOffset2D *dest_offset,
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const VkExtent3D *resolve_extent,
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VkImageAspectFlags aspects,
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VkResolveModeFlagBits resolve_mode)
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@ -755,16 +749,6 @@ emit_depth_stencil_resolve(struct radv_cmd_buffer *cmd_buffer,
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radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
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VK_PIPELINE_BIND_POINT_COMPUTE, *pipeline);
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unsigned push_constants[4] = {
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src_offset->x,
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src_offset->y,
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dest_offset->x,
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dest_offset->y,
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};
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radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
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device->meta_state.resolve_compute.p_layout,
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VK_SHADER_STAGE_COMPUTE_BIT, 0, 16,
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push_constants);
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radv_unaligned_dispatch(cmd_buffer, resolve_extent->width,
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resolve_extent->height, resolve_extent->depth);
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@ -945,7 +929,6 @@ radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
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radv_meta_save(&saved_state, cmd_buffer,
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RADV_META_SAVE_COMPUTE_PIPELINE |
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RADV_META_SAVE_CONSTANTS |
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RADV_META_SAVE_DESCRIPTORS);
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struct radv_subpass_attachment src_att = *subpass->depth_stencil_attachment;
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@ -992,8 +975,6 @@ radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
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}, NULL);
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emit_depth_stencil_resolve(cmd_buffer, &tsrc_iview, &tdst_iview,
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&(VkOffset2D) { 0, 0 },
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&(VkOffset2D) { 0, 0 },
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&(VkExtent3D) { fb->width, fb->height, layer_count },
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aspects, resolve_mode);
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@ -370,11 +370,9 @@ build_depth_stencil_resolve_fragment_shader(struct radv_device *dev, int samples
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nir_ssa_def *pos_in = nir_channels(&b, nir_load_frag_coord(&b), 0x3);
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nir_ssa_def *src_offset = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), 0, 8);
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nir_ssa_def *pos_int = nir_f2i32(&b, pos_in);
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nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, pos_int, src_offset), 0x3);
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nir_ssa_def *img_coord = nir_channels(&b, pos_int, 0x3);
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nir_ssa_def *input_img_deref = &nir_build_deref_var(&b, input_img)->dest.ssa;
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@ -898,8 +896,6 @@ static void
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emit_depth_stencil_resolve(struct radv_cmd_buffer *cmd_buffer,
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struct radv_image_view *src_iview,
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struct radv_image_view *dst_iview,
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const VkOffset2D *src_offset,
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const VkOffset2D *dst_offset,
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const VkExtent2D *resolve_extent,
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VkImageAspectFlags aspects,
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VkResolveModeFlagBits resolve_mode)
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@ -931,15 +927,6 @@ emit_depth_stencil_resolve(struct radv_cmd_buffer *cmd_buffer,
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},
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});
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unsigned push_constants[2] = {
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src_offset->x - dst_offset->x,
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src_offset->y - dst_offset->y,
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};
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radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
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device->meta_state.resolve_fragment.p_layout,
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VK_SHADER_STAGE_FRAGMENT_BIT, 0, 8,
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push_constants);
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switch (resolve_mode) {
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case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR:
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if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT)
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@ -983,8 +970,8 @@ emit_depth_stencil_resolve(struct radv_cmd_buffer *cmd_buffer,
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VK_PIPELINE_BIND_POINT_GRAPHICS, *pipeline);
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radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
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.x = dst_offset->x,
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.y = dst_offset->y,
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.x = 0,
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.y = 0,
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.width = resolve_extent->width,
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.height = resolve_extent->height,
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.minDepth = 0.0f,
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@ -992,7 +979,7 @@ emit_depth_stencil_resolve(struct radv_cmd_buffer *cmd_buffer,
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});
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radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
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.offset = *dst_offset,
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.offset = (VkOffset2D) { 0, 0 },
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.extent = *resolve_extent,
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});
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@ -1212,7 +1199,6 @@ radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
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radv_meta_save(&saved_state, cmd_buffer,
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RADV_META_SAVE_GRAPHICS_PIPELINE |
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RADV_META_SAVE_CONSTANTS |
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RADV_META_SAVE_DESCRIPTORS);
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struct radv_subpass_attachment src_att = *subpass->depth_stencil_attachment;
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@ -1249,8 +1235,6 @@ radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
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}, NULL);
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emit_depth_stencil_resolve(cmd_buffer, &tsrc_iview, dst_iview,
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&(VkOffset2D) { 0, 0 },
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&(VkOffset2D) { 0, 0 },
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&(VkExtent2D) { fb->width, fb->height },
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aspects,
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resolve_mode);
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