KonstantinSeurer
/
mesa
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

tu: Fix resolving d32s8 into s8 on fast path 

The code assumed that if the source was d32s8 then the destination would
also be d32s8, in particular that depth_base_addr/stencil_base_addr
would also be filled out. Move the destination and source handling into
two different ifs with different conditions.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17684>
This commit is contained in:
Connor Abbott 2022-07-21 17:25:41 +02:00 committed by Marge Bot
parent d426ee6a99
commit 19a2353446
2 changed files with 7 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/freedreno/ci/freedreno-a618-fails.txt
View File

@ -2,15 +2,9 @@
gmem-dEQP-VK.spirv_assembly.instruction.graphics.variable_pointers.graphics.writes_two_buffers_geom,Fail
gmem-dEQP-VK.spirv_assembly.instruction.graphics.variable_pointers.graphics.writes_two_buffers_vert,Fail
# VK-GL-CTS 1.3.2.0 uprev
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d32_sfloat_s8_uint_separate_layouts.compatibility_depth_zero_stencil_zero_testing_stencil,Fail
gmem-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d32_sfloat_s8_uint.compatibility_depth_zero_stencil_zero_testing_stencil,Fail
# https://gitlab.khronos.org/Tracker/vk-gl-cts/-/issues/3590
dEQP-VK.api.info.get_physical_device_properties2.memory_properties,Fail
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d32_sfloat_s8_uint.compatibility_depth_zero_stencil_zero_testing_stencil,Fail
# https://gitlab.khronos.org/Tracker/vk-gl-cts/-/issues/3759
# deqp-vk: ../src/freedreno/vulkan/tu_pipeline.c:3894: tu_pipeline_builder_init_graphics: Assertion `subpass->color_count == 0 || !create_info->pColorBlendState || subpass->color_count == create_info->pColorBlendState->attachmentCount' failed
dEQP-VK.pipeline.monolithic.color_write_enable_maxa.cwe_after_bind.attachments4_more0,Crash

15
src/freedreno/vulkan/tu_clear_blit.c
View File

@ -2958,7 +2958,7 @@ tu_emit_blit(struct tu_cmd_buffer *cmd,
vk_format_is_depth_or_stencil(attachment->format)));
tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 4);
if (attachment->format == VK_FORMAT_D32_SFLOAT_S8_UINT) {
if (iview->image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT) {
if (!separate_stencil) {
tu_cs_emit(cs, tu_image_view_depth(iview, RB_BLIT_DST_INFO));
tu_cs_emit_qw(cs, iview->depth_base_addr);
@ -2966,16 +2966,10 @@ tu_emit_blit(struct tu_cmd_buffer *cmd,
tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_FLAG_DST, 3);
tu_cs_image_flag_ref(cs, &iview->view, 0);
tu_cs_emit_regs(cs,
A6XX_RB_BLIT_BASE_GMEM(attachment->gmem_offset));
} else {
tu_cs_emit(cs, tu_image_view_stencil(iview, RB_BLIT_DST_INFO) & ~A6XX_RB_BLIT_DST_INFO_FLAGS);
tu_cs_emit_qw(cs, iview->stencil_base_addr);
tu_cs_emit(cs, iview->stencil_PITCH);
tu_cs_emit_regs(cs,
A6XX_RB_BLIT_BASE_GMEM(attachment->gmem_offset_stencil));
}
} else {
tu_cs_emit(cs, iview->view.RB_BLIT_DST_INFO);
@ -2983,9 +2977,14 @@ tu_emit_blit(struct tu_cmd_buffer *cmd,
tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_FLAG_DST, 3);
tu_cs_image_flag_ref(cs, &iview->view, 0);
}
if (attachment->format == VK_FORMAT_D32_SFLOAT_S8_UINT && separate_stencil) {
tu_cs_emit_regs(cs,
A6XX_RB_BLIT_BASE_GMEM(attachment->gmem_offset_stencil));
} else {
tu_cs_emit_regs(cs,
A6XX_RB_BLIT_BASE_GMEM(attachment->gmem_offset));
A6XX_RB_BLIT_BASE_GMEM(attachment->gmem_offset));
}
tu6_emit_event_write(cmd, cs, BLIT);