ilo: make ilo_render_emit_flush() direct
Remove emit_flush() and ILO_RENDER_FLUSH indirections. Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
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e3451552d2
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18cbd3cc34
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@ -323,10 +323,8 @@ draw_vbo(struct ilo_context *ilo, const struct ilo_state_vector *vec)
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/* make sure there is enough room first */
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max_len = ilo_render_estimate_size(ilo->render,
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ILO_RENDER_DRAW, vec);
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if (need_flush) {
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max_len += ilo_render_estimate_size(ilo->render,
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ILO_RENDER_FLUSH, NULL);
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}
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if (need_flush)
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max_len += ilo_render_get_flush_len(ilo->render);
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if (max_len > ilo_cp_space(ilo->cp)) {
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ilo_cp_submit(ilo->cp, "out of space");
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@ -380,8 +378,7 @@ ilo_draw_rectlist(struct ilo_context *ilo)
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max_len = ilo_render_estimate_size(ilo->render,
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ILO_RENDER_RECTLIST, ilo->blitter);
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max_len += ilo_render_estimate_size(ilo->render,
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ILO_RENDER_FLUSH, NULL) * 2;
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max_len += ilo_render_get_flush_len(ilo->render) * 2;
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if (max_len > ilo_cp_space(ilo->cp)) {
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ilo_cp_submit(ilo->cp, "out of space");
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@ -25,9 +25,11 @@
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* Chia-I Wu <olv@lunarg.com>
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*/
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#include "genhw/genhw.h"
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#include "intel_winsys.h"
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#include "ilo_builder.h"
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#include "ilo_builder_render.h"
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#include "ilo_render_gen.h"
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#include "ilo_render_gen7.h"
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#include "ilo_render.h"
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@ -179,3 +181,46 @@ ilo_render_invalidate_builder(struct ilo_render *render)
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/* Kernel flushes everything. Shouldn't we set all bits here? */
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render->state.current_pipe_control_dw1 = 0;
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}
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/**
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* Return the command length of ilo_render_emit_flush().
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*/
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int
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ilo_render_get_flush_len(const struct ilo_render *render)
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{
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int len;
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ILO_DEV_ASSERT(render->dev, 6, 7.5);
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len = GEN6_PIPE_CONTROL__SIZE;
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/* plus gen6_wa_pre_pipe_control() */
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if (ilo_dev_gen(render->dev) == ILO_GEN(6))
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len *= 3;
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return len;
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}
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/**
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* Emit PIPE_CONTROLs to flush all caches.
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*/
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void
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ilo_render_emit_flush(struct ilo_render *render)
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{
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const uint32_t dw1 = GEN6_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE |
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GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH |
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GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH |
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GEN6_PIPE_CONTROL_VF_CACHE_INVALIDATE |
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GEN6_PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
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GEN6_PIPE_CONTROL_CS_STALL;
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ILO_DEV_ASSERT(render->dev, 6, 7.5);
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if (ilo_dev_gen(render->dev) == ILO_GEN(6))
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gen6_wa_pre_pipe_control(render, dw1);
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gen6_PIPE_CONTROL(render->builder, dw1, NULL, 0, false);
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render->state.current_pipe_control_dw1 |= dw1;
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render->state.deferred_pipe_control_dw1 &= ~dw1;
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}
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@ -39,7 +39,6 @@ struct ilo_state_vector;
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enum ilo_render_action {
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ILO_RENDER_DRAW,
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ILO_RENDER_FLUSH,
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ILO_RENDER_QUERY,
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ILO_RENDER_RECTLIST,
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};
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@ -64,8 +63,6 @@ struct ilo_render {
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void (*emit_draw)(struct ilo_render *render,
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const struct ilo_state_vector *vec);
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void (*emit_flush)(struct ilo_render *render);
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void (*emit_query)(struct ilo_render *render,
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struct ilo_query *q, uint32_t offset);
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@ -172,15 +169,6 @@ ilo_render_emit_draw(struct ilo_render *render,
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render->emit_draw(render, vec);
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}
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/**
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* Emit PIPE_CONTROL to flush all caches.
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*/
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static inline void
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ilo_render_emit_flush(struct ilo_render *render)
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{
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render->emit_flush(render);
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}
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/**
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* Emit PIPE_CONTROL or MI_STORE_REGISTER_MEM to save register values.
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*/
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@ -210,4 +198,10 @@ ilo_render_invalidate_hw(struct ilo_render *render);
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void
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ilo_render_invalidate_builder(struct ilo_render *render);
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int
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ilo_render_get_flush_len(const struct ilo_render *render);
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void
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ilo_render_emit_flush(struct ilo_render *render);
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#endif /* ILO_RENDER_H */
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@ -75,6 +75,9 @@ struct gen6_rectlist_session {
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uint32_t CC_VIEWPORT;
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};
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void
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gen6_wa_pre_pipe_control(struct ilo_render *r, uint32_t dw1);
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void
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gen6_draw_prepare(struct ilo_render *r,
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const struct ilo_state_vector *ilo,
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@ -148,9 +151,6 @@ int
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gen6_render_estimate_query_size(const struct ilo_render *render,
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const struct ilo_query *q);
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void
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ilo_render_emit_flush_gen6(struct ilo_render *r);
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void
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ilo_render_emit_query_gen6(struct ilo_render *r,
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struct ilo_query *q, uint32_t offset);
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@ -60,7 +60,7 @@ gen6_pipe_control(struct ilo_render *r, uint32_t dw1)
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/**
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* This should be called before PIPE_CONTROL.
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*/
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static void
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void
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gen6_wa_pre_pipe_control(struct ilo_render *r, uint32_t dw1)
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{
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/*
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@ -366,7 +366,7 @@ gen6_draw_common_urb(struct ilo_render *r,
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* be taking over GS URB space."
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*/
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if (r->state.gs.active && !gs_active)
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ilo_render_emit_flush_gen6(r);
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ilo_render_emit_flush(r);
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r->state.gs.active = gs_active;
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}
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@ -1471,27 +1471,6 @@ ilo_render_emit_draw_gen6(struct ilo_render *render,
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gen6_draw_end(render, vec, &session);
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}
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void
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ilo_render_emit_flush_gen6(struct ilo_render *r)
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{
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const uint32_t dw1 = GEN6_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE |
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GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH |
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GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH |
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GEN6_PIPE_CONTROL_VF_CACHE_INVALIDATE |
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GEN6_PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
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GEN6_PIPE_CONTROL_CS_STALL;
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ILO_DEV_ASSERT(r->dev, 6, 7.5);
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if (ilo_dev_gen(r->dev) == ILO_GEN(6))
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gen6_wa_pre_pipe_control(r, dw1);
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gen6_PIPE_CONTROL(r->builder, dw1, NULL, 0, false);
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r->state.current_pipe_control_dw1 |= dw1;
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r->state.deferred_pipe_control_dw1 &= ~dw1;
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}
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void
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ilo_render_emit_query_gen6(struct ilo_render *r,
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struct ilo_query *q, uint32_t offset)
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@ -1561,7 +1540,7 @@ ilo_render_emit_query_gen6(struct ilo_render *r,
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if (!reg_count)
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return;
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r->emit_flush(r);
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ilo_render_emit_flush(r);
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for (i = 0; i < reg_count; i++) {
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if (regs[i]) {
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@ -1688,7 +1667,7 @@ gen6_rectlist_commands(struct ilo_render *r,
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r->dev->urb_size, 0, blitter->ve.count * 4 * sizeof(float), 0);
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/* 3DSTATE_URB workaround */
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if (r->state.gs.active) {
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ilo_render_emit_flush_gen6(r);
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ilo_render_emit_flush(r);
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r->state.gs.active = false;
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}
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@ -1973,9 +1952,6 @@ ilo_render_estimate_size_gen6(struct ilo_render *render,
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gen6_render_estimate_state_size(render, ilo);
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}
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break;
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case ILO_RENDER_FLUSH:
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size = GEN6_PIPE_CONTROL__SIZE * 3;
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break;
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case ILO_RENDER_QUERY:
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size = gen6_render_estimate_query_size(render,
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(const struct ilo_query *) arg);
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@ -1997,7 +1973,6 @@ ilo_render_init_gen6(struct ilo_render *render)
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{
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render->estimate_size = ilo_render_estimate_size_gen6;
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render->emit_draw = ilo_render_emit_draw_gen6;
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render->emit_flush = ilo_render_emit_flush_gen6;
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render->emit_query = ilo_render_emit_query_gen6;
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render->emit_rectlist = ilo_render_emit_rectlist_gen6;
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}
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@ -991,9 +991,6 @@ ilo_render_estimate_size_gen7(struct ilo_render *render,
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gen6_render_estimate_state_size(render, ilo);
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}
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break;
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case ILO_RENDER_FLUSH:
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size = GEN6_PIPE_CONTROL__SIZE;
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break;
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case ILO_RENDER_QUERY:
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size = gen6_render_estimate_query_size(render,
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(const struct ilo_query *) arg);
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@ -1015,7 +1012,6 @@ ilo_render_init_gen7(struct ilo_render *render)
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{
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render->estimate_size = ilo_render_estimate_size_gen7;
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render->emit_draw = ilo_render_emit_draw_gen7;
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render->emit_flush = ilo_render_emit_flush_gen6;
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render->emit_query = ilo_render_emit_query_gen6;
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render->emit_rectlist = ilo_render_emit_rectlist_gen7;
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}
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