radeonsi: always set FLUSH_ON_BINNING_TRANSITION
The hardware does the right thing automatically. Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
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@ -503,7 +503,6 @@ void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs)
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ctx->last_tes_sh_base = -1;
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ctx->last_num_tcs_input_cp = -1;
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ctx->last_ls_hs_config = -1; /* impossible value */
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ctx->last_binning_enabled = -1;
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if (has_clear_state) {
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si_set_tracked_regs_to_clear_state(ctx);
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@ -1146,7 +1146,6 @@ struct si_context {
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unsigned last_prim;
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unsigned last_multi_vgt_param;
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unsigned last_gs_out_prim;
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int last_binning_enabled;
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unsigned current_vs_state;
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unsigned last_vs_state;
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enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
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@ -424,20 +424,17 @@ static void si_emit_dpbb_disable(struct si_context *sctx)
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S_028C44_BIN_SIZE_X(bin_size.x == 16) | S_028C44_BIN_SIZE_Y(bin_size.y == 16) |
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S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend.x) |
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S_028C44_BIN_SIZE_Y_EXTEND(bin_size_extend.y) | S_028C44_DISABLE_START_OF_PRIM(1) |
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S_028C44_FLUSH_ON_BINNING_TRANSITION(sctx->last_binning_enabled != 0));
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S_028C44_FLUSH_ON_BINNING_TRANSITION(1));
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} else {
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radeon_opt_set_context_reg(
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sctx, R_028C44_PA_SC_BINNER_CNTL_0, SI_TRACKED_PA_SC_BINNER_CNTL_0,
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S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
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S_028C44_DISABLE_START_OF_PRIM(1) |
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S_028C44_FLUSH_ON_BINNING_TRANSITION((sctx->family == CHIP_VEGA12 ||
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S_028C44_FLUSH_ON_BINNING_TRANSITION(sctx->family == CHIP_VEGA12 ||
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sctx->family == CHIP_VEGA20 ||
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sctx->family >= CHIP_RAVEN2) &&
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sctx->last_binning_enabled != 0));
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sctx->family >= CHIP_RAVEN2));
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}
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radeon_end_update_context_roll(sctx);
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sctx->last_binning_enabled = false;
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}
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void si_emit_dpbb_state(struct si_context *sctx)
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@ -513,11 +510,8 @@ void si_emit_dpbb_state(struct si_context *sctx)
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S_028C44_PERSISTENT_STATES_PER_BIN(sscreen->pbb_persistent_states_per_bin - 1) |
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S_028C44_DISABLE_START_OF_PRIM(1) |
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S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) | S_028C44_OPTIMAL_BIN_SELECTION(1) |
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S_028C44_FLUSH_ON_BINNING_TRANSITION((sctx->family == CHIP_VEGA12 ||
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S_028C44_FLUSH_ON_BINNING_TRANSITION(sctx->family == CHIP_VEGA12 ||
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sctx->family == CHIP_VEGA20 ||
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sctx->family >= CHIP_RAVEN2) &&
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sctx->last_binning_enabled != 1));
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sctx->family >= CHIP_RAVEN2));
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radeon_end_update_context_roll(sctx);
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sctx->last_binning_enabled = true;
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}
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