winsys/amdgpu: enable chaining for compute IBs
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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@ -384,12 +384,12 @@ static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context *cs)
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static bool amdgpu_cs_has_chaining(struct amdgpu_cs *cs)
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{
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return cs->ctx->ws->info.chip_class >= CIK &&
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cs->ring_type == RING_GFX;
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(cs->ring_type == RING_GFX || cs->ring_type == RING_COMPUTE);
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}
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static unsigned amdgpu_cs_epilog_dws(enum ring_type ring_type)
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static unsigned amdgpu_cs_epilog_dws(struct amdgpu_cs *cs)
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{
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if (ring_type == RING_GFX)
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if (amdgpu_cs_has_chaining(cs))
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return 4; /* for chaining */
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return 0;
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@ -787,7 +787,7 @@ static bool amdgpu_get_new_ib(struct radeon_winsys *ws, struct amdgpu_cs *cs,
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ib->base.current.buf = (uint32_t*)(ib->ib_mapped + ib->used_ib_space);
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ib_size = ib->big_ib_buffer->size - ib->used_ib_space;
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ib->base.current.max_dw = ib_size / 4 - amdgpu_cs_epilog_dws(cs->ring_type);
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ib->base.current.max_dw = ib_size / 4 - amdgpu_cs_epilog_dws(cs);
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assert(ib->base.current.max_dw >= ib->max_check_space_size / 4);
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ib->base.gpu_address = info->va_start;
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return true;
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@ -985,7 +985,7 @@ static bool amdgpu_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw)
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struct amdgpu_ib *ib = amdgpu_ib(rcs);
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struct amdgpu_cs *cs = amdgpu_cs_from_ib(ib);
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unsigned requested_size = rcs->prev_dw + rcs->current.cdw + dw;
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unsigned cs_epilog_dw = amdgpu_cs_epilog_dws(cs->ring_type);
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unsigned cs_epilog_dw = amdgpu_cs_epilog_dws(cs);
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unsigned need_byte_size = (dw + cs_epilog_dw) * 4;
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uint64_t va;
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uint32_t *new_ptr_ib_size;
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@ -1518,7 +1518,7 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs,
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struct amdgpu_winsys *ws = cs->ctx->ws;
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int error_code = 0;
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rcs->current.max_dw += amdgpu_cs_epilog_dws(cs->ring_type);
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rcs->current.max_dw += amdgpu_cs_epilog_dws(cs);
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switch (cs->ring_type) {
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case RING_DMA:
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