i965/fs: Set pixel/sample mask for compute shaders atomic ops
For fragment programs, we pull this mask from the payload header. The same mask doesn't exist for compute shaders, so we set all bits to enabled. Previously we were setting 0xff to support SIMD8 VS, but with CS we support SIMD16, and therefore we change this to 0xffff. Related commits for SIMD8 VS: commitd9cd982d55
Author: Ben Widawsky <benjamin.widawsky@intel.com> Date: Sun Feb 15 20:06:59 2015 -0800 i965/simd8vs: Fix SIMD8 atomics commit4a95be9772
Author: Jordan Justen <jordan.l.justen@intel.com> Date: Tue Feb 17 09:57:35 2015 -0800 i965/simd8vs: Fix SIMD8 atomics (read-only) Note: this mask is ANDed with the execution mask, so some channels may not end up issuing the atomic operation. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Francisco Jerez <currojerez@riseup.net>
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@ -3014,9 +3014,9 @@ fs_visitor::emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
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* mask sent in the header to compute the actual set of channels that execute
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* the atomic operation.
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*/
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assert(stage == MESA_SHADER_VERTEX);
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assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE);
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emit(MOV(component(sources[0], 7),
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brw_imm_ud(0xff)))->force_writemask_all = true;
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brw_imm_ud(0xffff)))->force_writemask_all = true;
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}
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length++;
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@ -3077,9 +3077,9 @@ fs_visitor::emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
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* mask sent in the header to compute the actual set of channels that execute
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* the atomic operation.
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*/
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assert(stage == MESA_SHADER_VERTEX);
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assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE);
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emit(MOV(component(sources[0], 7),
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brw_imm_ud(0xff)))->force_writemask_all = true;
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brw_imm_ud(0xffff)))->force_writemask_all = true;
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}
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/* Set the surface read offset. */
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