r600: add ABS support for source regs to assembler
use it in tex cube instruction sequence
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50ab51101e
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@ -2350,8 +2350,8 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm)
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{
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alu_instruction_ptr->m_Word1_OP2.f6.alu_inst = pAsm->D.dst.opcode;
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alu_instruction_ptr->m_Word1_OP2.f6.src0_abs = 0x0;
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alu_instruction_ptr->m_Word1_OP2.f6.src1_abs = 0x0;
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alu_instruction_ptr->m_Word1_OP2.f6.src0_abs = pAsm->S[0].src.abs;
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alu_instruction_ptr->m_Word1_OP2.f6.src1_abs = pAsm->S[1].src.abs;
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//alu_instruction_ptr->m_Word1_OP2.f6.update_execute_mask = 0x0;
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//alu_instruction_ptr->m_Word1_OP2.f6.update_pred = 0x0;
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@ -2379,8 +2379,8 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm)
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{
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alu_instruction_ptr->m_Word1_OP2.f.alu_inst = pAsm->D.dst.opcode;
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alu_instruction_ptr->m_Word1_OP2.f.src0_abs = 0x0;
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alu_instruction_ptr->m_Word1_OP2.f.src1_abs = 0x0;
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alu_instruction_ptr->m_Word1_OP2.f.src0_abs = pAsm->S[0].src.abs;
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alu_instruction_ptr->m_Word1_OP2.f.src1_abs = pAsm->S[1].src.abs;
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//alu_instruction_ptr->m_Word1_OP2.f.update_execute_mask = 0x0;
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//alu_instruction_ptr->m_Word1_OP2.f.update_pred = 0x0;
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@ -4721,24 +4721,6 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm)
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return GL_FALSE;
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}
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/* tmp1.z = ABS(tmp1.z) dont have abs support in assembler currently
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* have to do explicit instruction
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*/
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pAsm->D.dst.opcode = SQ_OP2_INST_MAX;
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setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
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pAsm->D.dst.rtype = DST_REG_TEMPORARY;
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pAsm->D.dst.reg = tmp1;
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pAsm->D.dst.writez = 1;
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setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
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pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
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pAsm->S[0].src.reg = tmp1;
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noswizzle_PVSSRC(&(pAsm->S[0].src));
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pAsm->S[1].bits = pAsm->S[0].bits;
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flipneg_PVSSRC(&(pAsm->S[1].src));
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next_ins(pAsm);
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/* tmp1.z = RCP_e(|tmp1.z|) */
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pAsm->D.dst.opcode = SQ_OP2_INST_RECIP_IEEE;
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pAsm->D.dst.math = 1;
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@ -4751,6 +4733,7 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm)
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pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
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pAsm->S[0].src.reg = tmp1;
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pAsm->S[0].src.swizzlex = SQ_SEL_Z;
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pAsm->S[0].src.abs = 1;
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next_ins(pAsm);
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@ -120,14 +120,15 @@ typedef struct PVSINSTtag
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typedef struct PVSSRCtag
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{
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BITS rtype:4;
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BITS rtype:3;
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BITS addrmode0:1;
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BITS reg:10; //15 (8)
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BITS reg:10; //14 (8)
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BITS swizzlex:3;
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BITS swizzley:3;
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BITS swizzlez:3;
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BITS swizzlew:3; //27
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BITS swizzlew:3; //26
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BITS abs:1;
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BITS negx:1;
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BITS negy:1;
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BITS negz:1;
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