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i965/tcs/scalar: only update imm_offset for second message in 64bit input loads 

Our indirect URB read messages take both a direct and an indirect offset
so when we emit the second message for a 64-bit input load we can just
always incremement the immediate offset, even for the indirect case.

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
This commit is contained in:
Iago Toral Quiroga 2016-07-15 10:48:03 +02:00
parent 18f67c8a69
commit 1737e75bfb
1 changed files with 1 additions and 7 deletions
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8
src/mesa/drivers/dri/i965/brw_fs_nir.cpp
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@ -2509,13 +2509,7 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
*/
if (num_iterations > 1) {
num_components = instr->num_components - 2;
if (indirect_offset.file == BAD_FILE) {
imm_offset++;
} else {
fs_reg new_indirect = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
bld.ADD(new_indirect, indirect_offset, brw_imm_ud(1u));
indirect_offset = new_indirect;
}
imm_offset++;
}
}
break;