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i965: Eliminate brw->wm.prog_data pointer. 

Just say no to:

-   brw->wm.base.prog_data = &brw->wm.prog_data->base.base;

We'll just use the brw_stage_prog_data pointer in brw_stage_state
and downcast it to brw_wm_prog_data as needed.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arcero@collabora.com>
This commit is contained in:
Kenneth Graunke 2016-09-08 23:48:53 -07:00
parent ff366f3db4
commit 16d5536e55
14 changed files with 68 additions and 50 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mesa/drivers/dri/i965/brw_context.h
View File

@ -1180,7 +1180,6 @@ struct brw_context
struct {
struct brw_stage_state base;
struct brw_wm_prog_data *prog_data;
GLuint render_surf;

6
src/mesa/drivers/dri/i965/brw_curbe.c
View File

@ -76,7 +76,7 @@ static void calculate_curbe_offsets( struct brw_context *brw )
{
struct gl_context *ctx = &brw->ctx;
/* BRW_NEW_FS_PROG_DATA */
const GLuint nr_fp_regs = (brw->wm.prog_data->base.nr_params + 15) / 16;
const GLuint nr_fp_regs = (brw->wm.base.prog_data->nr_params + 15) / 16;
/* BRW_NEW_VS_PROG_DATA */
const GLuint nr_vp_regs = (brw->vs.base.prog_data->nr_params + 15) / 16;
@ -219,8 +219,8 @@ brw_upload_constant_buffer(struct brw_context *brw)
GLuint offset = brw->curbe.wm_start * 16;
/* BRW_NEW_FS_PROG_DATA | _NEW_PROGRAM_CONSTANTS: copy uniform values */
for (i = 0; i < brw->wm.prog_data->base.nr_params; i++) {
buf[offset + i] = *brw->wm.prog_data->base.param[i];
for (i = 0; i < brw->wm.base.prog_data->nr_params; i++) {
buf[offset + i] = *brw->wm.base.prog_data->param[i];
}
}

1
src/mesa/drivers/dri/i965/brw_state_cache.c
View File

@ -402,7 +402,6 @@ brw_clear_cache(struct brw_context *brw, struct brw_cache *cache)
brw->tcs.base.prog_data = NULL;
brw->tes.base.prog_data = NULL;
brw->gs.base.prog_data = NULL;
brw->wm.prog_data = NULL;
brw->wm.base.prog_data = NULL;
brw->cs.prog_data = NULL;
brw->cs.base.prog_data = NULL;

10
src/mesa/drivers/dri/i965/brw_wm.c
View File

@ -182,7 +182,7 @@ brw_codegen_wm_prog(struct brw_context *brw,
key, sizeof(struct brw_wm_prog_key),
program, program_size,
&prog_data, sizeof(prog_data),
&brw->wm.base.prog_offset, &brw->wm.prog_data);
&brw->wm.base.prog_offset, &brw->wm.base.prog_data);
ralloc_free(mem_ctx);
@ -578,12 +578,12 @@ brw_upload_wm_prog(struct brw_context *brw)
if (!brw_search_cache(&brw->cache, BRW_CACHE_FS_PROG,
&key, sizeof(key),
&brw->wm.base.prog_offset, &brw->wm.prog_data)) {
&brw->wm.base.prog_offset,
&brw->wm.base.prog_data)) {
bool success = brw_codegen_wm_prog(brw, current, fp, &key);
(void) success;
assert(success);
}
brw->wm.base.prog_data = &brw->wm.prog_data->base;
}
bool
@ -628,12 +628,12 @@ brw_fs_precompile(struct gl_context *ctx,
key.coherent_fb_fetch = ctx->Extensions.MESA_shader_framebuffer_fetch;
uint32_t old_prog_offset = brw->wm.base.prog_offset;
struct brw_wm_prog_data *old_prog_data = brw->wm.prog_data;
struct brw_stage_prog_data *old_prog_data = brw->wm.base.prog_data;
bool success = brw_codegen_wm_prog(brw, shader_prog, bfp, &key);
brw->wm.base.prog_offset = old_prog_offset;
brw->wm.prog_data = old_prog_data;
brw->wm.base.prog_data = old_prog_data;
return success;
}

3
src/mesa/drivers/dri/i965/brw_wm_state.c
View File

@ -80,7 +80,8 @@ brw_upload_wm_unit(struct brw_context *brw)
/* BRW_NEW_FRAGMENT_PROGRAM */
const struct gl_fragment_program *fp = brw->fragment_program;
/* BRW_NEW_FS_PROG_DATA */
const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
const struct brw_wm_prog_data *prog_data =
brw_wm_prog_data(brw->wm.base.prog_data);
struct brw_wm_unit_state *wm;
wm = brw_state_batch(brw, AUB_TRACE_WM_STATE,

21
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
View File

@ -832,7 +832,7 @@ brw_upload_wm_pull_constants(struct brw_context *brw)
struct brw_fragment_program *fp =
(struct brw_fragment_program *) brw->fragment_program;
/* BRW_NEW_FS_PROG_DATA */
struct brw_stage_prog_data *prog_data = &brw->wm.prog_data->base;
struct brw_stage_prog_data *prog_data = brw->wm.base.prog_data;
_mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_FRAGMENT);
/* _NEW_PROGRAM_CONSTANTS */
@ -1099,11 +1099,15 @@ update_renderbuffer_surfaces(struct brw_context *brw)
{
const struct gl_context *ctx = &brw->ctx;
/* BRW_NEW_FS_PROG_DATA */
const struct brw_wm_prog_data *wm_prog_data =
brw_wm_prog_data(brw->wm.base.prog_data);
/* _NEW_BUFFERS | _NEW_COLOR */
const struct gl_framebuffer *fb = ctx->DrawBuffer;
brw_update_renderbuffer_surfaces(
brw, fb,
brw->wm.prog_data->binding_table.render_target_start,
wm_prog_data->binding_table.render_target_start,
brw->wm.base.surf_offset);
brw->ctx.NewDriverState |= BRW_NEW_SURFACES;
}
@ -1133,6 +1137,10 @@ update_renderbuffer_read_surfaces(struct brw_context *brw)
{
const struct gl_context *ctx = &brw->ctx;
/* BRW_NEW_FS_PROG_DATA */
const struct brw_wm_prog_data *wm_prog_data =
brw_wm_prog_data(brw->wm.base.prog_data);
/* BRW_NEW_FRAGMENT_PROGRAM */
if (!ctx->Extensions.MESA_shader_framebuffer_fetch &&
brw->fragment_program &&
@ -1143,9 +1151,8 @@ update_renderbuffer_read_surfaces(struct brw_context *brw)
for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) {
struct gl_renderbuffer *rb = fb->_ColorDrawBuffers[i];
const struct intel_renderbuffer *irb = intel_renderbuffer(rb);
/* BRW_NEW_FS_PROG_DATA */
const unsigned surf_index =
brw->wm.prog_data->binding_table.render_target_read_start + i;
wm_prog_data->binding_table.render_target_read_start + i;
uint32_t *surf_offset = &brw->wm.base.surf_offset[surf_index];
if (irb) {
@ -1430,7 +1437,7 @@ brw_upload_wm_ubo_surfaces(struct brw_context *brw)
/* BRW_NEW_FS_PROG_DATA */
brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_FRAGMENT],
&brw->wm.base, &brw->wm.prog_data->base);
&brw->wm.base, brw->wm.base.prog_data);
}
const struct brw_tracked_state brw_wm_ubo_surfaces = {
@ -1509,7 +1516,7 @@ brw_upload_wm_abo_surfaces(struct brw_context *brw)
if (prog) {
/* BRW_NEW_FS_PROG_DATA */
brw_upload_abo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_FRAGMENT],
&brw->wm.base, &brw->wm.prog_data->base);
&brw->wm.base, brw->wm.base.prog_data);
}
}
@ -1803,7 +1810,7 @@ brw_upload_wm_image_surfaces(struct brw_context *brw)
if (prog) {
/* BRW_NEW_FS_PROG_DATA, BRW_NEW_IMAGE_UNITS, _NEW_TEXTURE */
brw_upload_image_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_FRAGMENT],
&brw->wm.base, &brw->wm.prog_data->base);
&brw->wm.base, brw->wm.base.prog_data);
}
}

2
src/mesa/drivers/dri/i965/gen6_clip_state.c
View File

@ -99,7 +99,7 @@ upload_clip_state(struct brw_context *brw)
struct gl_framebuffer *fb = ctx->DrawBuffer;
/* BRW_NEW_FS_PROG_DATA */
if (brw->wm.prog_data->barycentric_interp_modes &
if (brw_wm_prog_data(brw->wm.base.prog_data)->barycentric_interp_modes &
BRW_BARYCENTRIC_NONPERSPECTIVE_BITS) {
dw2 |= GEN6_CLIP_NON_PERSPECTIVE_BARYCENTRIC_ENABLE;
}

12
src/mesa/drivers/dri/i965/gen6_sf_state.c
View File

@ -158,6 +158,9 @@ calculate_attr_overrides(const struct brw_context *brw,
uint32_t *urb_entry_read_length,
uint32_t *urb_entry_read_offset)
{
/* BRW_NEW_FS_PROG_DATA */
const struct brw_wm_prog_data *wm_prog_data =
brw_wm_prog_data(brw->wm.base.prog_data);
uint32_t max_source_attr = 0;
*point_sprite_enables = 0;
@ -203,8 +206,7 @@ calculate_attr_overrides(const struct brw_context *brw,
memset(attr_overrides, 0, 16*sizeof(*attr_overrides));
for (int attr = 0; attr < VARYING_SLOT_MAX; attr++) {
/* BRW_NEW_FS_PROG_DATA */
int input_index = brw->wm.prog_data->urb_setup[attr];
int input_index = wm_prog_data->urb_setup[attr];
if (input_index < 0)
continue;
@ -267,7 +269,9 @@ upload_sf_state(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
/* BRW_NEW_FS_PROG_DATA */
uint32_t num_outputs = brw->wm.prog_data->num_varying_inputs;
const struct brw_wm_prog_data *wm_prog_data =
brw_wm_prog_data(brw->wm.base.prog_data);
uint32_t num_outputs = wm_prog_data->num_varying_inputs;
uint32_t dw1, dw2, dw3, dw4;
uint32_t point_sprite_enables;
int i;
@ -430,7 +434,7 @@ upload_sf_state(struct brw_context *brw)
OUT_BATCH(attr_overrides[i * 2] | attr_overrides[i * 2 + 1] << 16);
}
OUT_BATCH(point_sprite_enables); /* dw16 */
OUT_BATCH(brw->wm.prog_data->flat_inputs);
OUT_BATCH(wm_prog_data->flat_inputs);
OUT_BATCH(0); /* wrapshortest enables 0-7 */
OUT_BATCH(0); /* wrapshortest enables 8-15 */
ADVANCE_BATCH();

7
src/mesa/drivers/dri/i965/gen6_wm_state.c
View File

@ -45,11 +45,11 @@ gen6_upload_wm_push_constants(struct brw_context *brw)
const struct brw_fragment_program *fp =
brw_fragment_program_const(brw->fragment_program);
/* BRW_NEW_FS_PROG_DATA */
const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
const struct brw_stage_prog_data *prog_data = brw->wm.base.prog_data;
_mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_FRAGMENT);
gen6_upload_push_constants(brw, &fp->program.Base, &prog_data->base,
gen6_upload_push_constants(brw, &fp->program.Base, prog_data,
stage_state, AUB_TRACE_WM_CONSTANTS);
if (brw->gen >= 7) {
@ -241,7 +241,8 @@ upload_wm_state(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
/* BRW_NEW_FS_PROG_DATA */
const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
const struct brw_wm_prog_data *prog_data =
brw_wm_prog_data(brw->wm.base.prog_data);
/* _NEW_BUFFERS */
const bool multisampled_fbo = _mesa_geometric_samples(ctx->DrawBuffer) > 1;

6
src/mesa/drivers/dri/i965/gen7_sf_state.c
View File

@ -35,7 +35,9 @@ upload_sbe_state(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
/* BRW_NEW_FS_PROG_DATA */
uint32_t num_outputs = brw->wm.prog_data->num_varying_inputs;
const struct brw_wm_prog_data *wm_prog_data =
brw_wm_prog_data(brw->wm.base.prog_data);
uint32_t num_outputs = wm_prog_data->num_varying_inputs;
uint32_t dw1;
uint32_t point_sprite_enables;
int i;
@ -81,7 +83,7 @@ upload_sbe_state(struct brw_context *brw)
}
OUT_BATCH(point_sprite_enables); /* dw10 */
OUT_BATCH(brw->wm.prog_data->flat_inputs);
OUT_BATCH(wm_prog_data->flat_inputs);
OUT_BATCH(0); /* wrapshortest enables 0-7 */
OUT_BATCH(0); /* wrapshortest enables 8-15 */
ADVANCE_BATCH();

6
src/mesa/drivers/dri/i965/gen7_wm_state.c
View File

@ -38,7 +38,8 @@ upload_wm_state(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
/* BRW_NEW_FS_PROG_DATA */
const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
const struct brw_wm_prog_data *prog_data =
brw_wm_prog_data(brw->wm.base.prog_data);
bool writes_depth = prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF;
uint32_t dw1, dw2;
@ -251,7 +252,8 @@ static void
upload_ps_state(struct brw_context *brw)
{
/* BRW_NEW_FS_PROG_DATA */
const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
const struct brw_wm_prog_data *prog_data =
brw_wm_prog_data(brw->wm.base.prog_data);
const struct gl_context *ctx = &brw->ctx;
/* BRW_NEW_FS_PROG_DATA | _NEW_COLOR */
const bool enable_dual_src_blend = prog_data->dual_src_blend &&

19
src/mesa/drivers/dri/i965/gen8_depth_state.c
View File

@ -236,6 +236,9 @@ static bool
pma_fix_enable(const struct brw_context *brw)
{
const struct gl_context *ctx = &brw->ctx;
/* BRW_NEW_FS_PROG_DATA */
const struct brw_wm_prog_data *wm_prog_data =
brw_wm_prog_data(brw->wm.base.prog_data);
/* _NEW_BUFFERS */
struct intel_renderbuffer *depth_irb =
intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
@ -252,10 +255,8 @@ pma_fix_enable(const struct brw_context *brw)
*/
const bool hiz_enabled = depth_irb && intel_renderbuffer_has_hiz(depth_irb);
/* BRW_NEW_FS_PROG_DATA:
* 3DSTATE_WM::Early Depth/Stencil Control != EDSC_PREPS (2).
*/
const bool edsc_not_preps = !brw->wm.prog_data->early_fragment_tests;
/* 3DSTATE_WM::Early Depth/Stencil Control != EDSC_PREPS (2). */
const bool edsc_not_preps = !wm_prog_data->early_fragment_tests;
/* 3DSTATE_PS_EXTRA::PixelShaderValid is always true. */
const bool pixel_shader_valid = true;
@ -288,11 +289,9 @@ pma_fix_enable(const struct brw_context *brw)
*/
const bool stencil_writes_enabled = ctx->Stencil._WriteEnabled;
/* BRW_NEW_FS_PROG_DATA:
* 3DSTATE_PS_EXTRA::Pixel Shader Computed Depth Mode != PSCDEPTH_OFF
*/
/* 3DSTATE_PS_EXTRA::Pixel Shader Computed Depth Mode != PSCDEPTH_OFF */
const bool ps_computes_depth =
brw->wm.prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF;
wm_prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF;
/* BRW_NEW_FS_PROG_DATA: 3DSTATE_PS_EXTRA::PixelShaderKillsPixels
* BRW_NEW_FS_PROG_DATA: 3DSTATE_PS_EXTRA::oMask Present to RenderTarget
@ -303,8 +302,8 @@ pma_fix_enable(const struct brw_context *brw)
* 3DSTATE_WM::ForceKillPix != ForceOff is always true.
*/
const bool kill_pixel =
brw->wm.prog_data->uses_kill ||
brw->wm.prog_data->uses_omask ||
wm_prog_data->uses_kill ||
wm_prog_data->uses_omask ||
(_mesa_is_multisample_enabled(ctx) && ctx->Multisample.SampleAlphaToCoverage) ||
ctx->Color.AlphaEnabled;

18
src/mesa/drivers/dri/i965/gen8_ps_state.c
View File

@ -113,9 +113,7 @@ static void
upload_ps_extra(struct brw_context *brw)
{
/* BRW_NEW_FS_PROG_DATA */
const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
gen8_upload_ps_extra(brw, prog_data);
gen8_upload_ps_extra(brw, brw_wm_prog_data(brw->wm.base.prog_data));
}
const struct brw_tracked_state gen8_ps_extra = {
@ -135,6 +133,10 @@ upload_wm_state(struct brw_context *brw)
struct gl_context *ctx = &brw->ctx;
uint32_t dw1 = 0;
/* BRW_NEW_FS_PROG_DATA */
const struct brw_wm_prog_data *wm_prog_data =
brw_wm_prog_data(brw->wm.base.prog_data);
dw1 |= GEN7_WM_STATISTICS_ENABLE;
dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
@ -148,14 +150,13 @@ upload_wm_state(struct brw_context *brw)
if (ctx->Polygon.StippleFlag)
dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
/* BRW_NEW_FS_PROG_DATA */
dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
dw1 |= wm_prog_data->barycentric_interp_modes <<
GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
/* BRW_NEW_FS_PROG_DATA */
if (brw->wm.prog_data->early_fragment_tests)
if (wm_prog_data->early_fragment_tests)
dw1 |= GEN7_WM_EARLY_DS_CONTROL_PREPS;
else if (brw->wm.prog_data->has_side_effects)
else if (wm_prog_data->has_side_effects)
dw1 |= GEN7_WM_EARLY_DS_CONTROL_PSEXEC;
BEGIN_BATCH(2);
@ -274,7 +275,8 @@ static void
upload_ps_state(struct brw_context *brw)
{
/* BRW_NEW_FS_PROG_DATA */
const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
const struct brw_wm_prog_data *prog_data =
brw_wm_prog_data(brw->wm.base.prog_data);
gen8_upload_ps_state(brw, &brw->wm.base, prog_data, brw->wm.fast_clear_op);
}

6
src/mesa/drivers/dri/i965/gen8_sf_state.c
View File

@ -34,7 +34,9 @@ upload_sbe(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
/* BRW_NEW_FS_PROG_DATA */
uint32_t num_outputs = brw->wm.prog_data->num_varying_inputs;
const struct brw_wm_prog_data *wm_prog_data =
brw_wm_prog_data(brw->wm.base.prog_data);
uint32_t num_outputs = wm_prog_data->num_varying_inputs;
uint16_t attr_overrides[VARYING_SLOT_MAX];
uint32_t urb_entry_read_length;
uint32_t urb_entry_read_offset;
@ -109,7 +111,7 @@ upload_sbe(struct brw_context *brw)
OUT_BATCH(_3DSTATE_SBE << 16 | (sbe_cmd_length - 2));
OUT_BATCH(dw1);
OUT_BATCH(point_sprite_enables);
OUT_BATCH(brw->wm.prog_data->flat_inputs);
OUT_BATCH(wm_prog_data->flat_inputs);
if (sbe_cmd_length >= 6) {
OUT_BATCH(dw4);
OUT_BATCH(dw5);