r600/sfn: add lowering passes to get 64 bit ops lowered to 32 bit vec2

The lower_double and lower_int64 don't lower all 64 bit IO ops and merging
to and splitting fromn 64 bit values. So here goes a bunch of lowering
passes that takes care of this and also of merging IO that might have been
split.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7824>

src/gallium/drivers/r600/meson.build

@@ -149,6 +149,7 @@ files_r600 = files(
   'sfn/sfn_liverange.h',
   'sfn/sfn_nir.cpp',
   'sfn/sfn_nir.h',
+  'sfn/sfn_nir_lower_64bit.cpp',
   'sfn/sfn_nir_lower_fs_out_to_vector.cpp',
   'sfn/sfn_nir_lower_fs_out_to_vector.h',
   'sfn/sfn_nir_lower_tess_io.cpp',

src/gallium/drivers/r600/sfn/sfn_nir.h

@@ -60,6 +60,12 @@ bool r600_lower_scratch_addresses(nir_shader *shader);
 
 bool r600_lower_ubo_to_align16(nir_shader *shader);
 
+bool r600_nir_split_64bit_io(nir_shader *sh);
+
+bool r600_nir_64_to_vec2(nir_shader *sh);
+
+bool r600_merge_vec2_stores(nir_shader *shader);
+
 class Shader {
 public:
    std::vector<InstructionBlock>& m_ir;