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freedreno: Disable UBWC on z24s8 on a630. 

Stencil texture sampling (such as what we have to do for BlitFramebuffer)
is broken with UBWC enabled.  We can't just take the
fd_resource_uncompress() path, because that's a blit just like
BlitFramebuffer.

Fixes failure in dEQP-GLES3.functional.fbo.msaa.2_samples.stencil_index8,
but also the uncaught rendering fails of 4_samples.stencil_index8 and
depth24_stencil8.

Prior to "911ce374caf0 freedreno/a6xx: Fix MSAA clear" we would usually
pass and sometimes flake fail on this test occasionally, thus it being
listed as a flake (though the rendering was actually broken).  Since that
commit, though, we consistently fail on a pixel of the broken rendering,
and thus this was brought to my attention by the #freedreno-ci channel
spam.

Rob took a look at the performance impact of this, and the worst was maybe
up to .5% fps hit on trex.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8319>
This commit is contained in:
Eric Anholt 2020-12-17 17:07:48 -08:00 committed by Marge Bot
parent 6a8601fb24
commit 1633c9735a
3 changed files with 14 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.gitlab-ci/deqp-freedreno-a630-fails.txt
View File

@ -1,4 +1,3 @@
KHR-GL33.packed_depth_stencil.blit.depth24_stencil8,Fail
KHR-GL33.packed_depth_stencil.verify_get_tex_image.depth24_stencil8,Fail
KHR-GL33.packed_depth_stencil.verify_read_pixels.depth24_stencil8,Fail
KHR-GL33.transform_feedback.api_errors_test,Fail

1
.gitlab-ci/deqp-freedreno-a630-flakes.txt
View File

@ -30,7 +30,6 @@ dEQP-VK.memory_model.write_after_read.core11.u32.coherent.fence_fence.atomicwrit
# Undiagnosed flakes appearing more than once in the last 2 months as
# of 2020-08-19, in descending order of frequency.
dEQP-GLES3.functional.fbo.msaa.2_samples.stencil_index8
dEQP-GLES3.functional.fragment_out.random.39
dEQP-VK.subgroups.shuffle.framebuffer.subgroupshufflexor_bvec3_tess_eval
dEQP-VK.image.texel_view_compatible.graphic.extended.2d_image.texture_read.astc_10x6_unorm_block.r32g32b32a32_uint

33
src/gallium/drivers/freedreno/a6xx/fd6_resource.c
View File

@ -39,28 +39,23 @@
static bool
ok_ubwc_format(struct fd_resource *rsc, enum pipe_format pfmt)
{
/* NOTE: both x24s8 and z24s8 map to RB6_X8Z24_UNORM, but UBWC
* does not seem to work properly when sampling x24s8.. possibly
* because we sample it as TFMT6_8_8_8_8_UINT.
*
* This could possibly be a hw limitation, or maybe something
* else wrong somewhere (although z24s8 blits and sampling with
* UBWC seem fine). Recheck on a later revision of a6xx
*/
if (pfmt == PIPE_FORMAT_X24S8_UINT)
return false;
switch (pfmt) {
case PIPE_FORMAT_X24S8_UINT:
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
/* We can't sample stencil with UBWC on a630, and we may need to be able
* to sample stencil at some point. We can't just use
* fd_resource_uncompress() at the point of stencil sampling because
* that itself uses stencil sampling in the fd_blitter_blit path.
*/
return fd_screen(rsc->base.screen)->info.a6xx.has_z24uint_s8uint;
/* We don't fully understand what's going wrong with this combination, but
* we haven't been able to make it work. It's enough of a corner-case
* that we can just disable UBWC for these resources.
*/
if (rsc->base.target != PIPE_TEXTURE_2D &&
pfmt == PIPE_FORMAT_Z24_UNORM_S8_UINT)
return false;
if (pfmt == PIPE_FORMAT_R8_G8B8_420_UNORM)
case PIPE_FORMAT_R8_G8B8_420_UNORM:
return true;
default:
break;
}
switch (fd6_pipe2color(pfmt)) {
case FMT6_10_10_10_2_UINT:
case FMT6_10_10_10_2_UNORM_DEST: