etnaviv: set output mode and saturate bits

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
This commit is contained in:
Jonathan Marek 2019-08-12 14:19:59 -04:00
parent b7730c54a9
commit 15e9704ccb
5 changed files with 30 additions and 3 deletions

View File

@ -449,7 +449,8 @@ etna_emit_state(struct etna_context *ctx)
ctx->framebuffer.msaa_mode
? ctx->shader_state.PS_TEMP_REGISTER_CONTROL_MSAA
: ctx->shader_state.PS_TEMP_REGISTER_CONTROL);
/*01010*/ EMIT_STATE(PS_CONTROL, ctx->shader_state.PS_CONTROL);
/*01010*/ EMIT_STATE(PS_CONTROL, ctx->framebuffer.PS_CONTROL);
/*01030*/ EMIT_STATE(PS_CONTROL_EXT, ctx->framebuffer.PS_CONTROL_EXT);
}
if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_SHADER))) {
/*01400*/ EMIT_STATE(PE_DEPTH_CONFIG, (etna_zsa_state(ctx->zsa)->PE_DEPTH_CONFIG |

View File

@ -216,6 +216,8 @@ struct compiled_framebuffer_state {
struct etna_reloc TS_COLOR_STATUS_BASE;
struct etna_reloc TS_COLOR_SURFACE_BASE;
uint32_t PE_LOGIC_OP;
uint32_t PS_CONTROL;
uint32_t PS_CONTROL_EXT;
bool msaa_mode; /* adds input (and possible temp) to PS */
};
@ -256,7 +258,6 @@ struct compiled_shader_state {
uint32_t PS_INPUT_COUNT_MSAA; /* Adds an input */
uint32_t PS_TEMP_REGISTER_CONTROL;
uint32_t PS_TEMP_REGISTER_CONTROL_MSAA; /* Adds a temporary if needed to make space for extra input */
uint32_t PS_CONTROL;
uint32_t PS_START_PC;
uint32_t PE_DEPTH_CONFIG;
uint32_t GL_VARYING_TOTAL_COMPONENTS;

View File

@ -165,7 +165,6 @@ etna_link_shaders(struct etna_context *ctx, struct compiled_shader_state *cs,
VIVS_PS_INPUT_COUNT_UNK8(fs->input_count_unk8);
cs->PS_TEMP_REGISTER_CONTROL =
VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS(MAX2(fs->num_temps, link.num_varyings + 1));
cs->PS_CONTROL = VIVS_PS_CONTROL_SATURATE_RT0; /* XXX when can we set BYPASS? */
cs->PS_START_PC = 0;
/* Precompute PS_INPUT_COUNT and TEMP_REGISTER_CONTROL in the case of MSAA

View File

@ -213,6 +213,10 @@ etna_set_framebuffer_state(struct pipe_context *pctx,
if (util_format_is_srgb(cbuf->base.format))
pe_logic_op |= VIVS_PE_LOGIC_OP_SRGB;
cs->PS_CONTROL = COND(util_format_is_unorm(cbuf->base.format), VIVS_PS_CONTROL_SATURATE_RT0);
cs->PS_CONTROL_EXT =
VIVS_PS_CONTROL_EXT_OUTPUT_MODE0(translate_output_mode(cbuf->base.format, ctx->specs.halti >= 5));
} else {
/* Clearing VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK and
* VIVS_PE_COLOR_FORMAT_OVERWRITE prevents us from overwriting the

View File

@ -306,6 +306,28 @@ translate_vertex_format_normalize(enum pipe_format fmt)
: VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF;
}
static inline uint32_t
translate_output_mode(enum pipe_format fmt, bool halti5)
{
const unsigned bits =
util_format_get_component_bits(fmt, UTIL_FORMAT_COLORSPACE_RGB, 0);
if (bits == 32)
return COLOR_OUTPUT_MODE_UIF32;
if (!util_format_is_pure_integer(fmt))
return COLOR_OUTPUT_MODE_NORMAL;
/* generic integer output mode pre-halti5 (?) */
if (bits == 10 || !halti5)
return COLOR_OUTPUT_MODE_A2B10G10R10UI;
if (util_format_is_pure_sint(fmt))
return bits == 8 ? COLOR_OUTPUT_MODE_I8 : COLOR_OUTPUT_MODE_I16;
return bits == 8 ? COLOR_OUTPUT_MODE_U8 : COLOR_OUTPUT_MODE_U16;
}
static inline uint32_t
translate_index_size(unsigned index_size)
{