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i965/miptree: Replace is_lossless_compressed with mt->aux_usage checks 

Now that we have an actual aux_usage field, we no longer need the
complex logic of is_lossless_compressed in order to figure out if a
miptree is CCS_E compressed.  As a side-effect, there is not longer any
need to overload MSAA_LAYOUT_CMS for CCS_E and we can stop doing so.

Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
This commit is contained in:
Jason Ekstrand 2017-07-12 19:20:22 -07:00
parent 67143a5037
commit 14570ecf63
5 changed files with 10 additions and 41 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mesa/drivers/dri/i965/brw_blorp.c
View File

@ -792,7 +792,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
/* If the MCS buffer hasn't been allocated yet, we need to allocate it now.
*/
if (can_fast_clear && !irb->mt->mcs_buf) {
assert(!intel_miptree_is_lossless_compressed(brw, irb->mt));
assert(irb->mt->aux_usage == ISL_AUX_USAGE_CCS_D);
if (!intel_miptree_alloc_ccs(brw, irb->mt)) {
/* There are a few reasons in addition to out-of-memory, that can
* cause intel_miptree_alloc_non_msrt_mcs to fail. Try to recover by

2
src/mesa/drivers/dri/i965/brw_draw.c
View File

@ -414,7 +414,7 @@ brw_predraw_resolve_inputs(struct brw_context *brw)
if (tex_obj && tex_obj->mt) {
intel_miptree_prepare_image(brw, tex_obj->mt);
if (intel_miptree_is_lossless_compressed(brw, tex_obj->mt) &&
if (tex_obj->mt->aux_usage == ISL_AUX_USAGE_CCS_E &&
intel_disable_rb_aux_buffer(brw, tex_obj->mt->bo)) {
perf_debug("Using renderbuffer as shader image - turning "
"off lossless compression");

4
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
View File

@ -451,7 +451,7 @@ brw_texture_view_sane(const struct brw_context *brw,
const struct isl_view *view)
{
/* There are special cases only for lossless compression. */
if (!intel_miptree_is_lossless_compressed(brw, mt))
if (mt->aux_usage != ISL_AUX_USAGE_CCS_E)
return true;
if (isl_format_supports_ccs_e(&brw->screen->devinfo, view->format))
@ -493,7 +493,7 @@ brw_disable_aux_surface(const struct brw_context *brw,
view->base_array_layer, view->array_len);
/* There are special cases only for lossless compression. */
if (!intel_miptree_is_lossless_compressed(brw, mt))
if (mt->aux_usage != ISL_AUX_USAGE_CCS_E)
return !is_unresolved;
const struct gl_framebuffer *fb = brw->ctx.DrawBuffer;

39
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
View File

@ -240,34 +240,6 @@ intel_miptree_supports_hiz(struct brw_context *brw,
}
}
/* On Gen9 support for color buffer compression was extended to single
* sampled surfaces. This is a helper considering both auxiliary buffer
* type and number of samples telling if the given miptree represents
* the new single sampled case - also called lossless compression.
*/
bool
intel_miptree_is_lossless_compressed(const struct brw_context *brw,
const struct intel_mipmap_tree *mt)
{
/* Only available from Gen9 onwards. */
if (brw->gen < 9)
return false;
/* Compression always requires auxiliary buffer. */
if (!mt->mcs_buf)
return false;
/* Single sample compression is represented re-using msaa compression
* layout type: "Compressed Multisampled Surfaces".
*/
if (mt->msaa_layout != INTEL_MSAA_LAYOUT_CMS)
return false;
/* And finally distinguish between msaa and single sample case. */
return mt->num_samples <= 1;
}
static bool
intel_miptree_supports_ccs_e(struct brw_context *brw,
const struct intel_mipmap_tree *mt)
@ -1906,7 +1878,6 @@ intel_miptree_alloc_ccs(struct brw_context *brw,
* Software needs to initialize MCS with zeros."
*/
intel_miptree_init_mcs(brw, mt, 0);
mt->msaa_layout = INTEL_MSAA_LAYOUT_CMS;
}
return true;
@ -2205,10 +2176,11 @@ intel_miptree_prepare_ccs_access(struct brw_context *brw,
enum isl_aux_state aux_state = intel_miptree_get_aux_state(mt, level, layer);
enum blorp_fast_clear_op resolve_op;
if (intel_miptree_is_lossless_compressed(brw, mt)) {
if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
resolve_op = get_ccs_e_resolve_op(aux_state, aux_supported,
fast_clear_supported);
} else {
assert(mt->aux_usage == ISL_AUX_USAGE_CCS_D);
resolve_op = get_ccs_d_resolve_op(aux_state, aux_supported,
fast_clear_supported);
}
@ -2246,7 +2218,7 @@ intel_miptree_finish_ccs_write(struct brw_context *brw,
{
enum isl_aux_state aux_state = intel_miptree_get_aux_state(mt, level, layer);
if (intel_miptree_is_lossless_compressed(brw, mt)) {
if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
switch (aux_state) {
case ISL_AUX_STATE_CLEAR:
assert(written_with_ccs);
@ -2273,6 +2245,7 @@ intel_miptree_finish_ccs_write(struct brw_context *brw,
unreachable("Invalid aux state for CCS_E");
}
} else {
assert(mt->aux_usage == ISL_AUX_USAGE_CCS_D);
/* CCS_D is a bit simpler */
switch (aux_state) {
case ISL_AUX_STATE_CLEAR:
@ -2594,7 +2567,7 @@ can_texture_with_ccs(struct brw_context *brw,
struct intel_mipmap_tree *mt,
mesa_format view_format)
{
if (!intel_miptree_is_lossless_compressed(brw, mt))
if (mt->aux_usage != ISL_AUX_USAGE_CCS_E)
return false;
enum isl_format isl_mt_format = brw_isl_format_for_mesa_format(mt->format);
@ -2694,7 +2667,7 @@ intel_miptree_prepare_render(struct brw_context *brw,
/* Lossless compression is not supported for SRGB formats, it
* should be impossible to get here with such surfaces.
*/
assert(!intel_miptree_is_lossless_compressed(brw, mt));
assert(mt->aux_usage != ISL_AUX_USAGE_CCS_E);
intel_miptree_prepare_access(brw, mt, level, 1, start_layer, layer_count,
false, false);
}

4
src/mesa/drivers/dri/i965/intel_mipmap_tree.h
View File

@ -641,10 +641,6 @@ struct intel_mipmap_tree
GLuint refcount;
};
bool
intel_miptree_is_lossless_compressed(const struct brw_context *brw,
const struct intel_mipmap_tree *mt);
bool
intel_miptree_alloc_ccs(struct brw_context *brw,
struct intel_mipmap_tree *mt);