asahi: Add some magic IOGPU routines
These turned out to be software defined structures consumed by the macOS kernel (specifically, by IOGPUCommandQueue). I'm a bit bothered by the sheer amount of random hex flying about, though Hector made some progress on deciphering the structure. Nevertheless there's some comfort knowing it's not actual hardware magic. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
This commit is contained in:
Alyssa Rosenzweig
Alyssa Rosenzweig
parent
7949fa4f9f
commit
13f5b17078
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#include <stdint.h>
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#include "agx_state.h"
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#include "magic.h"
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/* magic code lifted from ./demo ... a lot more reveng needed */
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struct cmdbuf {
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uint32_t *map;
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unsigned offset;
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};
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static void
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EMIT32(struct cmdbuf *cmdbuf, uint32_t val)
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{
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cmdbuf->map[cmdbuf->offset++] = val;
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}
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static void
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EMIT64(struct cmdbuf *cmdbuf, uint64_t val)
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{
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EMIT32(cmdbuf, (val & 0xFFFFFFFF));
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EMIT32(cmdbuf, (val >> 32));
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}
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static void
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EMIT_ZERO_WORDS(struct cmdbuf *cmdbuf, size_t words)
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{
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memset(cmdbuf->map + cmdbuf->offset, 0, words * 4);
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cmdbuf->offset += words;
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}
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/* Odd pattern */
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static uint64_t
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demo_unk6(struct agx_pool *pool)
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{
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struct agx_ptr ptr = agx_pool_alloc_aligned(pool, 0x4000 * sizeof(uint64_t), 64);
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uint64_t *buf = ptr.cpu;
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memset(buf, 0, sizeof(*buf));
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for (unsigned i = 1; i < 0x3ff; ++i)
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buf[i] = (i + 1);
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return ptr.gpu;
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}
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static uint64_t
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demo_zero(struct agx_pool *pool, unsigned count)
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{
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struct agx_ptr ptr = agx_pool_alloc_aligned(pool, count, 64);
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memset(ptr.cpu, 0, count);
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return ptr.gpu;
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}
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void
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demo_cmdbuf(uint64_t *buf, size_t size,
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struct agx_pool *pool,
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uint64_t encoder_ptr,
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unsigned width, unsigned height,
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uint32_t pipeline_null,
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uint32_t pipeline_clear,
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uint32_t pipeline_store,
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uint64_t rt0)
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{
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struct cmdbuf _cmdbuf = {
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.map = (uint32_t *) buf,
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.offset = 0
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};
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struct cmdbuf *cmdbuf = &_cmdbuf;
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/* Vertex stuff */
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EMIT32(cmdbuf, 0x10000);
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EMIT32(cmdbuf, 0x780); // Compute: 0x188
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EMIT32(cmdbuf, 0x7);
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EMIT_ZERO_WORDS(cmdbuf, 5);
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EMIT32(cmdbuf, 0x758); // Compute: 0x180
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EMIT32(cmdbuf, 0x18); // Compute: 0x0
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EMIT32(cmdbuf, 0x758); // Compute: 0x0
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EMIT32(cmdbuf, 0x728); // Compute: 0x150
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EMIT32(cmdbuf, 0x30); /* 0x30 */
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EMIT32(cmdbuf, 0x01); /* 0x34. Compute: 0x03 */
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EMIT64(cmdbuf, encoder_ptr);
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EMIT_ZERO_WORDS(cmdbuf, 20);
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EMIT64(cmdbuf, 0); /* 0x90, compute blob - some zero */
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EMIT64(cmdbuf, 0); // blob - 0x540 bytes of zero, compute blob - null
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EMIT64(cmdbuf, 0); // blob - 0x280 bytes of zero
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EMIT64(cmdbuf, 0); // a8, compute blob - zero pointer
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EMIT64(cmdbuf, 0); // compute blob - zero pointer
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EMIT64(cmdbuf, 0); // compute blob - zero pointer
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EMIT64(cmdbuf, 0); // compute blob - zero pointer
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// while zero for vertex, used to include the odd unk6 pattern for compute
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EMIT64(cmdbuf, 0); // compute blob - 0x1
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EMIT64(cmdbuf, 0); // d0, ompute blob - pointer to odd pattern, compare how it's done later for frag
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// compute 8 bytes of zero, then reconverge at *
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EMIT32(cmdbuf, 0x6b0003); // d8
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EMIT32(cmdbuf, 0x3a0012); // dc
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/* Possibly the funny pattern but not actually pointed to for vertex */
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EMIT64(cmdbuf, 1); // e0
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EMIT64(cmdbuf, 0); // e8
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EMIT_ZERO_WORDS(cmdbuf, 44);
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EMIT64(cmdbuf, 0); // blob - 0x20 bytes of zero
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EMIT64(cmdbuf, 1); // 1a8
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// * compute reconverges here at 0xe0 in my trace
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EMIT32(cmdbuf, 0x1c); // 1b0
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// compute 0xe4: [encoder ID -- from selector6 + 2 with blob], 0, 0, 0xffffffff, done for a while
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// compute 0x120: 0x9 | 0x128: 0x40
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EMIT32(cmdbuf, 0); // 1b0 - compute: 0x10000
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EMIT64(cmdbuf, 0x0); // 1b8 -- compute 0x10000
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EMIT32(cmdbuf, 0xffffffff); // note we can zero!
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EMIT32(cmdbuf, 0xffffffff); // note we can zero! compute 0
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EMIT32(cmdbuf, 0xffffffff); // note we can zero! compute 0
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EMIT32(cmdbuf, 0);
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EMIT_ZERO_WORDS(cmdbuf, 40);
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EMIT32(cmdbuf, 0xffff8002); // 0x270
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EMIT32(cmdbuf, 0);
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EMIT64(cmdbuf, pipeline_clear | 0x4);
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EMIT32(cmdbuf, 0);
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EMIT32(cmdbuf, 0);
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EMIT32(cmdbuf, 0);
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EMIT32(cmdbuf, 0x12);
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EMIT64(cmdbuf, pipeline_store | 0x4);
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EMIT64(cmdbuf, demo_zero(pool, 0x1000)); // Pointer to scissor descriptor
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EMIT64(cmdbuf, demo_zero(pool, 0x1000));
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EMIT64(cmdbuf, 0);
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EMIT_ZERO_WORDS(cmdbuf, 48);
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EMIT64(cmdbuf, 4);
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EMIT64(cmdbuf, 0xc000);
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/* Note: making these smallers scissors polygons but not clear colour */
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EMIT32(cmdbuf, width);
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EMIT32(cmdbuf, height);
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EMIT64(cmdbuf, demo_zero(pool, 0x8000));
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EMIT_ZERO_WORDS(cmdbuf, 48);
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float depth_clear = 1.0;
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uint8_t stencil_clear = 0;
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EMIT64(cmdbuf, 0); // 0x450
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EMIT32(cmdbuf, fui(depth_clear));
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EMIT32(cmdbuf, (0x3 << 8) | stencil_clear);
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EMIT64(cmdbuf, 0);
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EMIT64(cmdbuf, 0x1000000);
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EMIT32(cmdbuf, 0xffffffff);
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EMIT32(cmdbuf, 0xffffffff);
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EMIT32(cmdbuf, 0xffffffff);
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EMIT32(cmdbuf, 0);
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EMIT_ZERO_WORDS(cmdbuf, 8);
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EMIT64(cmdbuf, 0); // 0x4a0
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EMIT32(cmdbuf, 0xffff8212);
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EMIT32(cmdbuf, 0);
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EMIT64(cmdbuf, pipeline_null | 0x4);
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EMIT64(cmdbuf, 0);
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EMIT32(cmdbuf, 0);
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EMIT32(cmdbuf, 0x12);
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EMIT32(cmdbuf, pipeline_store | 0x4);
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EMIT32(cmdbuf, 0);
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EMIT_ZERO_WORDS(cmdbuf, 44);
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EMIT64(cmdbuf, 1); // 0x580
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EMIT64(cmdbuf, 0);
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EMIT_ZERO_WORDS(cmdbuf, 4);
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/* Compare compute case ,which has a bit of reordering, but we can swap */
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EMIT32(cmdbuf, 0x1c); // 0x5a0
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EMIT32(cmdbuf, 0);
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EMIT64(cmdbuf, 0xCAFECAFE); // encoder ID XXX: don't fix
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EMIT32(cmdbuf, 0);
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EMIT32(cmdbuf, 0xffffffff);
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// remark: opposite order for compute, but we can swap the orders
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EMIT32(cmdbuf, 1);
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EMIT32(cmdbuf, 0);
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EMIT64(cmdbuf, 0);
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EMIT64(cmdbuf, demo_unk6(pool));
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/* note: width/height act like scissor, but changing the 0s doesn't
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* seem to affect (maybe scissor enable bit missing), _and this affects
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* the clear_ .. bbox maybe */
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EMIT32(cmdbuf, 0);
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EMIT32(cmdbuf, 0);
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EMIT32(cmdbuf, width * 2); // can increase up to 16384
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EMIT32(cmdbuf, height);
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EMIT32(cmdbuf, 1);
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EMIT32(cmdbuf, 8);
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EMIT32(cmdbuf, 8);
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EMIT32(cmdbuf, 0);
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EMIT_ZERO_WORDS(cmdbuf, 12);
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EMIT32(cmdbuf, 0); // 0x620
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EMIT32(cmdbuf, 8);
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EMIT32(cmdbuf, 0x20);
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EMIT32(cmdbuf, 0x20);
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EMIT32(cmdbuf, 0x1);
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EMIT32(cmdbuf, 0);
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EMIT64(cmdbuf, 0);
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EMIT_ZERO_WORDS(cmdbuf, 72);
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EMIT32(cmdbuf, 0); // 0x760
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EMIT32(cmdbuf, 0x1); // number of attachments (includes depth/stencil) stored to
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/* A single attachment follows, depth/stencil have their own attachments */
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{
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EMIT64(cmdbuf, 0x100 | (rt0 << 16));
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EMIT32(cmdbuf, 0xa0000);
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EMIT32(cmdbuf, 0x4c000000); // 80000000 also observed, and 8c000 and.. offset into the tilebuffer I imagine
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EMIT32(cmdbuf, 0x0c001d); // C0020 also observed
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EMIT32(cmdbuf, 0x640000);
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}
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}
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static struct agx_map_header
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demo_map_header(uint64_t cmdbuf_id, uint64_t encoder_id, unsigned count)
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{
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return (struct agx_map_header) {
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.cmdbuf_id = cmdbuf_id,
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.unk2 = 0x1,
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.unk3 = 0x528, // 1320
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.encoder_id = encoder_id,
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.unk6 = 0x0,
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.unk7 = 0x780, // 1920 -- same as above..
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/* +1 for the sentinel ending */
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.nr_entries_1 = count + 1,
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.nr_entries_2 = count + 1,
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.unka = 0x0b,
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};
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}
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void
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demo_mem_map(void *map, size_t size, unsigned *handles, unsigned count,
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uint64_t cmdbuf_id, uint64_t encoder_id)
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{
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struct agx_map_header *header = map;
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struct agx_map_entry *entries = (struct agx_map_entry *) (((uint8_t *) map) + 0x40);
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struct agx_map_entry *end = (struct agx_map_entry *) (((uint8_t *) map) + size);
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/* Header precedes the entry */
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*header = demo_map_header(cmdbuf_id, encoder_id, count);
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/* Add an entry for each BO mapped */
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for (unsigned i = 0; i < count; ++i) {
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assert((entries + i) < end);
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entries[i] = (struct agx_map_entry) {
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.unkAAA = 0x20,
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.unkBBB = 0x1,
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.unka = 0x1ffff,
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.index = handles[i]
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};
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}
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/* Final entry is a sentinel */
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assert((entries + count) < end);
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entries[count] = (struct agx_map_entry) {
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.unkAAA = 0x40,
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.unkBBB = 0x1,
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.unka = 0x1ffff,
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.index = 0
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};
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}
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#define AGX_STOP \
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0x88, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, \
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0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00 \
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#define AGX_BLEND \
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0x09, 0x00, 0x00, 0x04, 0xf0, 0xfc, 0x80, 0x03
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/* Clears the tilebuffer, where u6-u7 are preloaded with the FP16 clear colour
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0: 7e018c098040 bitop_mov r0, u6
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6: 7e058e098000 bitop_mov r1, u7
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c: 09000004f0fc8003 TODO.blend
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*/
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uint8_t shader_clear[] = {
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0x7e, 0x01, 0x8c, 0x09, 0x80, 0x40,
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0x7e, 0x05, 0x8e, 0x09, 0x80, 0x00,
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AGX_BLEND,
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AGX_STOP
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};
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uint8_t shader_store[] = {
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0x7e, 0x00, 0x04, 0x09, 0x80, 0x00,
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0xb1, 0x80, 0x00, 0x80, 0x00, 0x4a, 0x00, 0x00, 0x0a, 0x00,
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AGX_STOP
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};
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void
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agx_internal_shaders(struct agx_device *dev)
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{
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unsigned clear_offset = 0;
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unsigned store_offset = 1024;
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struct agx_bo *bo = agx_bo_create(dev, 4096, AGX_MEMORY_TYPE_SHADER);
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memcpy(((uint8_t *) bo->ptr.cpu) + clear_offset, shader_clear, sizeof(shader_clear));
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memcpy(((uint8_t *) bo->ptr.cpu) + store_offset, shader_store, sizeof(shader_store));
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dev->internal.bo = bo;
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dev->internal.clear = bo->ptr.gpu + clear_offset;
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dev->internal.store = bo->ptr.gpu + store_offset;
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}
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@ -0,0 +1,17 @@
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void
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demo_cmdbuf(uint64_t *buf, size_t size,
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struct agx_pool *pool,
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uint64_t encoder_ptr,
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unsigned width, unsigned height,
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uint32_t pipeline_null,
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uint32_t pipeline_clear,
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uint32_t pipeline_store,
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uint64_t rt0);
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void
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demo_mem_map(void *map, size_t size, unsigned *handles,
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unsigned count, uint64_t cmdbuf_id, uint64_t
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encoder_id);
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void
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agx_internal_shaders(struct agx_device *dev);
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@ -20,4 +20,5 @@
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files_asahi = files(
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'agx_uniforms.c',
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'magic.c',
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)
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