radeonsi: only emit compute shader state when switching shaders
v2: - Do check if anything changed earlier - Use emitted_program instead of emitted_bo to prevent shaders with shader->bo = NULL confusing the check - Use radeon_set_sh_reg* Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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@ -185,6 +185,7 @@ static void si_initialize_compute(struct si_context *sctx)
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0x190 /* Default value */);
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0x190 /* Default value */);
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}
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}
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sctx->cs_shader_state.emitted_program = NULL;
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sctx->cs_shader_state.initialized = true;
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sctx->cs_shader_state.initialized = true;
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}
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}
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@ -226,6 +227,83 @@ static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
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return true;
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return true;
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}
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}
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static bool si_switch_compute_shader(struct si_context *sctx,
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struct si_compute *program,
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struct si_shader *shader, unsigned offset)
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{
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struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
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struct si_shader_config inline_config = {0};
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struct si_shader_config *config;
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uint64_t shader_va;
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if (sctx->cs_shader_state.emitted_program == program &&
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sctx->cs_shader_state.offset == offset)
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return true;
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if (program->ir_type == PIPE_SHADER_IR_TGSI) {
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config = &shader->config;
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} else {
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unsigned lds_blocks;
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config = &inline_config;
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si_shader_binary_read_config(&shader->binary, config, offset);
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lds_blocks = config->lds_size;
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/* XXX: We are over allocating LDS. For SI, the shader reports
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* LDS in blocks of 256 bytes, so if there are 4 bytes lds
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* allocated in the shader and 4 bytes allocated by the state
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* tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
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*/
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if (sctx->b.chip_class <= SI) {
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lds_blocks += align(program->local_size, 256) >> 8;
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} else {
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lds_blocks += align(program->local_size, 512) >> 9;
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}
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assert(lds_blocks <= 0xFF);
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config->rsrc2 &= C_00B84C_LDS_SIZE;
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config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
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}
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if (!si_setup_compute_scratch_buffer(sctx, shader, config))
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return false;
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if (shader->scratch_bo) {
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COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
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"Total Scratch: %u bytes\n", sctx->scratch_waves,
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config->scratch_bytes_per_wave,
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config->scratch_bytes_per_wave *
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sctx->scratch_waves);
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
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shader->scratch_bo, RADEON_USAGE_READWRITE,
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RADEON_PRIO_SCRATCH_BUFFER);
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}
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shader_va = shader->bo->gpu_address + offset;
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, shader->bo,
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RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
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radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
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radeon_emit(cs, shader_va >> 8);
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radeon_emit(cs, shader_va >> 40);
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radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
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radeon_emit(cs, config->rsrc1);
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radeon_emit(cs, config->rsrc2);
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radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
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S_00B860_WAVES(sctx->scratch_waves)
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| S_00B860_WAVESIZE(config->scratch_bytes_per_wave >> 10));
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sctx->cs_shader_state.emitted_program = program;
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sctx->cs_shader_state.offset = offset;
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return true;
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}
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static void si_upload_compute_input(struct si_context *sctx,
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static void si_upload_compute_input(struct si_context *sctx,
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const struct pipe_grid_info *info)
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const struct pipe_grid_info *info)
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{
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{
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@ -282,10 +360,7 @@ static void si_launch_grid(
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struct si_context *sctx = (struct si_context*)ctx;
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struct si_context *sctx = (struct si_context*)ctx;
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struct si_compute *program = sctx->cs_shader_state.program;
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struct si_compute *program = sctx->cs_shader_state.program;
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struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
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struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
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uint64_t shader_va;
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unsigned i;
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unsigned i;
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struct si_shader *shader = &program->shader;
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unsigned lds_blocks;
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si_need_cs_space(sctx);
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si_need_cs_space(sctx);
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@ -302,29 +377,12 @@ static void si_launch_grid(
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pm4->compute_pkt = true;
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pm4->compute_pkt = true;
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/* Read the config information */
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if (!si_switch_compute_shader(sctx, program, &program->shader, info->pc))
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si_shader_binary_read_config(&shader->binary, &shader->config, info->pc);
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if (!si_setup_compute_scratch_buffer(sctx, shader, &shader->config))
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return;
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return;
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if (program->input_size || program->ir_type == PIPE_SHADER_IR_NATIVE)
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if (program->input_size || program->ir_type == PIPE_SHADER_IR_NATIVE)
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si_upload_compute_input(sctx, info);
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si_upload_compute_input(sctx, info);
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if (shader->config.scratch_bytes_per_wave > 0) {
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COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
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"Total Scratch: %u bytes\n", sctx->scratch_waves,
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shader->config.scratch_bytes_per_wave,
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shader->config.scratch_bytes_per_wave *
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sctx->scratch_waves);
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
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shader->scratch_bo,
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RADEON_USAGE_READWRITE,
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RADEON_PRIO_SCRATCH_BUFFER);
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}
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si_pm4_set_reg(pm4, R_00B81C_COMPUTE_NUM_THREAD_X,
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si_pm4_set_reg(pm4, R_00B81C_COMPUTE_NUM_THREAD_X,
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S_00B81C_NUM_THREAD_FULL(info->block[0]));
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S_00B81C_NUM_THREAD_FULL(info->block[0]));
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si_pm4_set_reg(pm4, R_00B820_COMPUTE_NUM_THREAD_Y,
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si_pm4_set_reg(pm4, R_00B820_COMPUTE_NUM_THREAD_Y,
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@ -344,44 +402,6 @@ static void si_launch_grid(
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RADEON_PRIO_COMPUTE_GLOBAL);
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RADEON_PRIO_COMPUTE_GLOBAL);
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}
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}
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shader_va = shader->bo->gpu_address;
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shader_va += info->pc;
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, shader->bo,
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RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
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si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, shader_va >> 8);
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si_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, shader_va >> 40);
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si_pm4_set_reg(pm4, R_00B848_COMPUTE_PGM_RSRC1, shader->config.rsrc1);
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lds_blocks = shader->config.lds_size;
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/* XXX: We are over allocating LDS. For SI, the shader reports LDS in
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* blocks of 256 bytes, so if there are 4 bytes lds allocated in
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* the shader and 4 bytes allocated by the state tracker, then
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* we will set LDS_SIZE to 512 bytes rather than 256.
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*/
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if (sctx->b.chip_class <= SI) {
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lds_blocks += align(program->local_size, 256) >> 8;
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} else {
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lds_blocks += align(program->local_size, 512) >> 9;
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}
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assert(lds_blocks <= 0xFF);
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shader->config.rsrc2 &= C_00B84C_LDS_SIZE;
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shader->config.rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
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si_pm4_set_reg(pm4, R_00B84C_COMPUTE_PGM_RSRC2, shader->config.rsrc2);
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si_pm4_set_reg(pm4, R_00B860_COMPUTE_TMPRING_SIZE,
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/* The maximum value for WAVES is 32 * num CU.
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* If you program this value incorrectly, the GPU will hang if
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* COMPUTE_PGM_RSRC2.SCRATCH_EN is enabled.
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*/
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S_00B860_WAVES(sctx->scratch_waves)
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| S_00B860_WAVESIZE(shader->config.scratch_bytes_per_wave >> 10))
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;
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si_pm4_cmd_begin(pm4, PKT3_DISPATCH_DIRECT);
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si_pm4_cmd_begin(pm4, PKT3_DISPATCH_DIRECT);
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si_pm4_cmd_add(pm4, info->grid[0]); /* Thread groups DIM_X */
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si_pm4_cmd_add(pm4, info->grid[0]); /* Thread groups DIM_X */
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si_pm4_cmd_add(pm4, info->grid[1]); /* Thread groups DIM_Y */
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si_pm4_cmd_add(pm4, info->grid[1]); /* Thread groups DIM_Y */
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@ -412,11 +432,18 @@ static void si_launch_grid(
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static void si_delete_compute_state(struct pipe_context *ctx, void* state){
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static void si_delete_compute_state(struct pipe_context *ctx, void* state){
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struct si_compute *program = (struct si_compute *)state;
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struct si_compute *program = (struct si_compute *)state;
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struct si_context *sctx = (struct si_context*)ctx;
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if (!state) {
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if (!state) {
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return;
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return;
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}
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}
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if (program == sctx->cs_shader_state.program)
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sctx->cs_shader_state.program = NULL;
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if (program == sctx->cs_shader_state.emitted_program)
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sctx->cs_shader_state.emitted_program = NULL;
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si_shader_destroy(&program->shader);
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si_shader_destroy(&program->shader);
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FREE(program);
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FREE(program);
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}
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}
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@ -133,6 +133,8 @@ struct si_sampler_state {
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struct si_cs_shader_state {
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struct si_cs_shader_state {
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struct si_compute *program;
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struct si_compute *program;
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struct si_compute *emitted_program;
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unsigned offset;
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bool initialized;
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bool initialized;
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};
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};
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