r300g: add support for 3D NPOT textures without mipmapping
The driver actually creates a 3D texture aligned to POT and does all the magic with texture coordinates in the fragment shader. It first emulates REPEAT and MIRRORED wrap modes in the fragment shader to get the coordinates into the range [0, 1]. (already done for 2D NPOT) Then it scales them to get the coordinates of the NPOT subtexture. NPOT textures are now less of a lie and we can at least display something meaningful even for the 3D ones. Supported wrap modes: - REPEAT - MIRRORED_REPEAT - CLAMP_TO_EDGE (NEAREST filtering only) - MIRROR_CLAMP_TO_EDGE (NEAREST filtering only) - The behavior of other CLAMP modes is undefined on borders, but they usually give results very close to CLAMP_TO_EDGE with mirroring working perfectly. This fixes: - piglit/fbo-3d - piglit/tex3d-npot
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@ -336,6 +336,13 @@ struct r300_texture_desc {
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/* Parent class. */
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struct u_resource b;
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/* Width, height, and depth.
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* Most of the time, these are equal to pipe_texture::width0, height0,
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* and depth0. However, NPOT 3D textures must have dimensions aligned
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* to POT, and this is the only case when these variables differ from
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* pipe_texture. */
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unsigned width0, height0, depth0;
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/* Buffer tiling.
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* Macrotiling is specified per-level because small mipmaps cannot
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* be macrotiled. */
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@ -89,7 +89,7 @@ static const float * get_rc_constant_state(
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{
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struct r300_textures_state* texstate = r300->textures_state.state;
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static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
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struct pipe_resource *tex;
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struct r300_texture *tex;
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assert(constant->Type == RC_CONSTANT_STATE);
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@ -97,9 +97,17 @@ static const float * get_rc_constant_state(
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/* Factor for converting rectangle coords to
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* normalized coords. Should only show up on non-r500. */
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case RC_STATE_R300_TEXRECT_FACTOR:
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tex = texstate->sampler_views[constant->u.State[1]]->base.texture;
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vec[0] = 1.0 / tex->width0;
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vec[1] = 1.0 / tex->height0;
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tex = r300_texture(texstate->sampler_views[constant->u.State[1]]->base.texture);
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vec[0] = 1.0 / tex->desc.width0;
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vec[1] = 1.0 / tex->desc.height0;
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break;
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case RC_STATE_R300_TEXSCALE_FACTOR:
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tex = r300_texture(texstate->sampler_views[constant->u.State[1]]->base.texture);
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/* Add a small number to the texture size to work around rounding errors in hw. */
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vec[0] = tex->desc.b.b.width0 / (tex->desc.width0 + 0.001f);
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vec[1] = tex->desc.b.b.height0 / (tex->desc.height0 + 0.001f);
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vec[2] = tex->desc.b.b.depth0 / (tex->desc.depth0 + 0.001f);
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break;
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case RC_STATE_R300_VIEWPORT_SCALE:
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@ -200,6 +200,9 @@ static void get_external_state(
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default:
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state->unit[i].wrap_mode = RC_WRAP_NONE;
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}
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if (t->desc.b.b.target == PIPE_TEXTURE_3D)
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state->unit[i].clamp_and_scale_before_fetch = TRUE;
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}
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}
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}
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@ -556,18 +556,15 @@ void r300_texture_setup_format_state(struct r300_screen *screen,
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out->tile_config = 0;
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/* Set sampler state. */
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out->format0 = R300_TX_WIDTH((u_minify(pt->width0, level) - 1) & 0x7ff) |
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R300_TX_HEIGHT((u_minify(pt->height0, level) - 1) & 0x7ff);
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out->format0 =
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R300_TX_WIDTH((u_minify(desc->width0, level) - 1) & 0x7ff) |
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R300_TX_HEIGHT((u_minify(desc->height0, level) - 1) & 0x7ff) |
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R300_TX_DEPTH(util_logbase2(u_minify(desc->depth0, level)) & 0xf);
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if (desc->uses_stride_addressing) {
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/* rectangles love this */
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out->format0 |= R300_TX_PITCH_EN;
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out->format2 = (desc->stride_in_pixels[level] - 1) & 0x1fff;
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} else {
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/* Power of two textures (3D, mipmaps, and no pitch),
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* also NPOT textures with a width being POT. */
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out->format0 |=
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R300_TX_DEPTH(util_logbase2(u_minify(pt->depth0, level)) & 0xf);
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}
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if (pt->target == PIPE_TEXTURE_CUBE) {
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@ -580,10 +577,10 @@ void r300_texture_setup_format_state(struct r300_screen *screen,
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/* large textures on r500 */
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if (is_r500)
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{
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if (pt->width0 > 2048) {
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if (desc->width0 > 2048) {
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out->format2 |= R500_TXWIDTH_BIT11;
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}
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if (pt->height0 > 2048) {
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if (desc->height0 > 2048) {
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out->format2 |= R500_TXHEIGHT_BIT11;
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}
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}
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@ -91,9 +91,9 @@ static boolean r300_texture_macro_switch(struct r300_texture_desc *desc,
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tile = r300_get_pixel_alignment(desc->b.b.format, desc->b.b.nr_samples,
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desc->microtile, R300_BUFFER_TILED, dim);
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if (dim == DIM_WIDTH) {
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texdim = u_minify(desc->b.b.width0, level);
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texdim = u_minify(desc->width0, level);
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} else {
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texdim = u_minify(desc->b.b.height0, level);
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texdim = u_minify(desc->height0, level);
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}
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/* See TX_FILTER1_n.MACRO_SWITCH. */
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@ -124,7 +124,7 @@ static unsigned r300_texture_get_stride(struct r300_screen *screen,
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return 0;
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}
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width = u_minify(desc->b.b.width0, level);
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width = u_minify(desc->width0, level);
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if (util_format_is_plain(desc->b.b.format)) {
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tile_width = r300_get_pixel_alignment(desc->b.b.format,
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@ -172,7 +172,7 @@ static unsigned r300_texture_get_nblocksy(struct r300_texture_desc *desc,
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{
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unsigned height, tile_height;
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height = u_minify(desc->b.b.height0, level);
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height = u_minify(desc->height0, level);
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if (util_format_is_plain(desc->b.b.format)) {
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tile_height = r300_get_pixel_alignment(desc->b.b.format,
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@ -237,7 +237,7 @@ static void r300_texture_3d_fix_mipmapping(struct r300_screen *screen,
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r300_texture_get_nblocksy(desc, i, FALSE);
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}
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size *= desc->b.b.depth0;
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size *= desc->depth0;
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desc->size_in_bytes = size;
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}
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}
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@ -292,7 +292,7 @@ static void r300_setup_miptree(struct r300_screen *screen,
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if (base->target == PIPE_TEXTURE_CUBE)
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size = layer_size * 6;
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else
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size = layer_size * u_minify(base->depth0, i);
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size = layer_size * u_minify(desc->depth0, i);
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desc->offset_in_bytes[i] = desc->size_in_bytes;
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desc->size_in_bytes = desc->offset_in_bytes[i] + size;
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@ -303,8 +303,8 @@ static void r300_setup_miptree(struct r300_screen *screen,
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SCREEN_DBG(screen, DBG_TEXALLOC, "r300: Texture miptree: Level %d "
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"(%dx%dx%d px, pitch %d bytes) %d bytes total, macrotiled %s\n",
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i, u_minify(base->width0, i), u_minify(base->height0, i),
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u_minify(base->depth0, i), stride, desc->size_in_bytes,
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i, u_minify(desc->width0, i), u_minify(desc->height0, i),
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u_minify(desc->depth0, i), stride, desc->size_in_bytes,
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desc->macrotile[i] ? "TRUE" : "FALSE");
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}
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}
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@ -313,14 +313,14 @@ static void r300_setup_flags(struct r300_texture_desc *desc)
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{
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desc->uses_stride_addressing =
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!util_is_power_of_two(desc->b.b.width0) ||
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!util_is_power_of_two(desc->b.b.height0) ||
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(desc->stride_in_bytes_override &&
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stride_to_width(desc->b.b.format,
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desc->stride_in_bytes_override) != desc->b.b.width0);
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desc->is_npot =
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desc->uses_stride_addressing ||
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!util_is_power_of_two(desc->b.b.height0);
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!util_is_power_of_two(desc->b.b.height0) ||
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!util_is_power_of_two(desc->b.b.depth0);
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}
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static void r300_setup_cbzb_flags(struct r300_screen *rscreen,
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@ -416,9 +416,21 @@ boolean r300_texture_desc_init(struct r300_screen *rscreen,
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{
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desc->b.b = *base;
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desc->b.b.screen = &rscreen->screen;
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desc->stride_in_bytes_override = stride_in_bytes_override;
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desc->width0 = base->width0;
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desc->height0 = base->height0;
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desc->depth0 = base->depth0;
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r300_setup_flags(desc);
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/* Align a 3D NPOT texture to POT. */
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if (base->target == PIPE_TEXTURE_3D && desc->is_npot) {
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desc->width0 = util_next_power_of_two(desc->width0);
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desc->height0 = util_next_power_of_two(desc->height0);
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desc->depth0 = util_next_power_of_two(desc->depth0);
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}
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/* Setup tiling. */
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if (microtile == R300_BUFFER_SELECT_LAYOUT ||
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macrotile == R300_BUFFER_SELECT_LAYOUT) {
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r300_setup_tiling(rscreen, desc);
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@ -428,7 +440,6 @@ boolean r300_texture_desc_init(struct r300_screen *rscreen,
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assert(desc->b.b.last_level == 0);
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}
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r300_setup_flags(desc);
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r300_setup_cbzb_flags(rscreen, desc);
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/* Setup the miptree description. */
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@ -60,6 +60,7 @@ enum {
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RC_STATE_R300_WINDOW_DIMENSION,
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RC_STATE_R300_TEXRECT_FACTOR,
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RC_STATE_R300_TEXSCALE_FACTOR,
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RC_STATE_R300_VIEWPORT_SCALE,
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RC_STATE_R300_VIEWPORT_OFFSET
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};
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@ -158,7 +159,13 @@ struct r300_fragment_program_external_state {
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* If this field is \ref RC_WRAP_NONE (aka 0), no wrapping maths
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* will be performed on the coordinates.
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*/
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unsigned wrap_mode : 2;
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unsigned wrap_mode : 3;
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/**
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* The coords are scaled after applying the wrap mode emulation
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* and right before texture fetch. The scaling factor is given by
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* RC_STATE_R300_TEXSCALE_FACTOR. */
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unsigned clamp_and_scale_before_fetch : 1;
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} unit[16];
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};
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@ -252,7 +252,8 @@ int radeonTransformTEX(
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/* Divide by W if needed. */
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if (inst->U.I.Opcode == RC_OPCODE_TXP &&
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(wrapmode == RC_WRAP_REPEAT || wrapmode == RC_WRAP_MIRRORED_REPEAT)) {
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(wrapmode == RC_WRAP_REPEAT || wrapmode == RC_WRAP_MIRRORED_REPEAT ||
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compiler->state.unit[inst->U.I.TexSrcUnit].clamp_and_scale_before_fetch)) {
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projective_divide(compiler, inst);
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}
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@ -388,6 +389,35 @@ int radeonTransformTEX(
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inst->U.I.SrcReg[0].Index = temp;
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}
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if (inst->U.I.Opcode != RC_OPCODE_KIL &&
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compiler->state.unit[inst->U.I.TexSrcUnit].clamp_and_scale_before_fetch) {
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struct rc_instruction *inst_mov;
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unsigned temp = rc_find_free_temporary(c);
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/* Saturate XYZ. */
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inst_mov = rc_insert_new_instruction(c, inst->Prev);
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inst_mov->U.I.Opcode = RC_OPCODE_MOV;
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inst_mov->U.I.SaturateMode = RC_SATURATE_ZERO_ONE;
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inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY;
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inst_mov->U.I.DstReg.Index = temp;
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inst_mov->U.I.DstReg.WriteMask = RC_MASK_XYZ;
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inst_mov->U.I.SrcReg[0] = inst->U.I.SrcReg[0];
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/* Copy W. */
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inst_mov = rc_insert_new_instruction(c, inst->Prev);
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inst_mov->U.I.Opcode = RC_OPCODE_MOV;
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inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY;
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inst_mov->U.I.DstReg.Index = temp;
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inst_mov->U.I.DstReg.WriteMask = RC_MASK_W;
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inst_mov->U.I.SrcReg[0] = inst->U.I.SrcReg[0];
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reset_srcreg(&inst->U.I.SrcReg[0]);
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inst->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
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inst->U.I.SrcReg[0].Index = temp;
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scale_texcoords(compiler, inst, RC_STATE_R300_TEXSCALE_FACTOR);
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}
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/* Cannot write texture to output registers (all chips) or with masks (non-r500) */
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if (inst->U.I.Opcode != RC_OPCODE_KIL &&
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(inst->U.I.DstReg.File != RC_FILE_TEMPORARY ||
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