radeonsi: update invariant registers for tessellation
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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99bf47f603
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12df9a7876
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@ -3125,8 +3125,8 @@ static void si_init_config(struct si_context *sctx)
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si_cmd_context_control(pm4);
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si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
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si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
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si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
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si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
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/* FIXME calculate these values somehow ??? */
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si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, 0x80);
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@ -3251,6 +3251,10 @@ static void si_init_config(struct si_context *sctx)
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si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
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if (sctx->b.chip_class >= CIK) {
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si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffc));
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si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
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si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xfffe));
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si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
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si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
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si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
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si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
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