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i965/fs: Apply usual FPU-like execution size restrictions to MULH. 

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Francisco Jerez 2016-05-17 16:43:05 -07:00
parent dea9c1df89
commit 12ae87abb1
1 changed files with 2 additions and 1 deletions
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3
src/mesa/drivers/dri/i965/brw_fs.cpp
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@ -4829,7 +4829,8 @@ get_lowered_simd_width(const struct brw_device_info *devinfo,
/* MULH is lowered to the MUL/MACH sequence using the accumulator, which
* is 8-wide on Gen7+.
*/
return (devinfo->gen >= 7 ? 8 : inst->exec_size);
return (devinfo->gen >= 7 ? 8 :
get_fpu_lowered_simd_width(devinfo, inst));
case FS_OPCODE_FB_WRITE_LOGICAL:
/* Gen6 doesn't support SIMD16 depth writes but we cannot handle them