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intel/compiler: add new half-float register type for 3-src instructions 

This is available since gen8.

v2: restore previously existing assertion.

v3: don't use separate tables for gen7 and gen8, just assert that we
    don't use half-float before gen8 (Matt)

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> (v1)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Iago Toral Quiroga 2018-05-21 14:42:42 +02:00 committed by Juan A. Suarez Romero
parent 4ab2b97a8f
commit 120c970619
1 changed files with 4 additions and 0 deletions
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4
src/intel/compiler/brw_reg_type.c
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@ -138,6 +138,7 @@ enum hw_3src_reg_type {
GEN7_3SRC_TYPE_D = 1,
GEN7_3SRC_TYPE_UD = 2,
GEN7_3SRC_TYPE_DF = 3,
GEN8_3SRC_TYPE_HF = 4,
/** When ExecutionDatatype is 1: @{ */
GEN10_ALIGN1_3SRC_REG_TYPE_HF = 0b000,
@ -166,6 +167,7 @@ static const struct hw_3src_type {
[BRW_REGISTER_TYPE_D] = { GEN7_3SRC_TYPE_D },
[BRW_REGISTER_TYPE_UD] = { GEN7_3SRC_TYPE_UD },
[BRW_REGISTER_TYPE_DF] = { GEN7_3SRC_TYPE_DF },
[BRW_REGISTER_TYPE_HF] = { GEN8_3SRC_TYPE_HF },
}, gen10_hw_3src_align1_type[] = {
#define E(x) BRW_ALIGN1_3SRC_EXEC_TYPE_##x
[0 ... BRW_REGISTER_TYPE_LAST] = { INVALID },
@ -258,6 +260,7 @@ brw_reg_type_to_a16_hw_3src_type(const struct gen_device_info *devinfo,
enum brw_reg_type type)
{
assert(type < ARRAY_SIZE(gen7_hw_3src_type));
assert(devinfo->gen >= 8 || type != BRW_REGISTER_TYPE_HF);
assert(gen7_hw_3src_type[type].reg_type != (enum hw_3src_reg_type)INVALID);
return gen7_hw_3src_type[type].reg_type;
}
@ -283,6 +286,7 @@ enum brw_reg_type
brw_a16_hw_3src_type_to_reg_type(const struct gen_device_info *devinfo,
unsigned hw_type)
{
assert(devinfo->gen >= 8 || hw_type != GEN8_3SRC_TYPE_HF);
for (enum brw_reg_type i = 0; i <= BRW_REGISTER_TYPE_LAST; i++) {
if (gen7_hw_3src_type[i].reg_type == hw_type) {
return i;