radv: Use NIR barycentric intrinsics
We have to add a few lowering to deal with things that used to be dealt with inline when creating inputs. We also move the code that fills out the radv_shader_variant_info struct for linking purposes to radv_shader.c, as it's no longer tied to the NIR->LLVM lowering. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Connor Abbott
parent
0cad0424e9
commit
118a66df99
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@ -2311,131 +2311,6 @@ handle_vs_input_decl(struct radv_shader_context *ctx,
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}
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}
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static void interp_fs_input(struct radv_shader_context *ctx,
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unsigned attr,
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LLVMValueRef interp_param,
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LLVMValueRef prim_mask,
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bool float16,
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LLVMValueRef result[4])
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{
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LLVMValueRef attr_number;
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unsigned chan;
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LLVMValueRef i, j;
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bool interp = !LLVMIsUndef(interp_param);
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attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
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/* fs.constant returns the param from the middle vertex, so it's not
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* really useful for flat shading. It's meant to be used for custom
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* interpolation (but the intrinsic can't fetch from the other two
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* vertices).
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*
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* Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
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* to do the right thing. The only reason we use fs.constant is that
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* fs.interp cannot be used on integers, because they can be equal
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* to NaN.
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*/
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if (interp) {
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interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
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ctx->ac.v2f32, "");
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i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
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ctx->ac.i32_0, "");
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j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
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ctx->ac.i32_1, "");
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}
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for (chan = 0; chan < 4; chan++) {
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LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
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if (interp && float16) {
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result[chan] = ac_build_fs_interp_f16(&ctx->ac,
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llvm_chan,
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attr_number,
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prim_mask, i, j);
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} else if (interp) {
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result[chan] = ac_build_fs_interp(&ctx->ac,
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llvm_chan,
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attr_number,
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prim_mask, i, j);
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} else {
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result[chan] = ac_build_fs_interp_mov(&ctx->ac,
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LLVMConstInt(ctx->ac.i32, 2, false),
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llvm_chan,
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attr_number,
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prim_mask);
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result[chan] = LLVMBuildBitCast(ctx->ac.builder, result[chan], ctx->ac.i32, "");
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result[chan] = LLVMBuildTruncOrBitCast(ctx->ac.builder, result[chan], float16 ? ctx->ac.i16 : ctx->ac.i32, "");
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}
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}
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}
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static void mark_16bit_fs_input(struct radv_shader_context *ctx,
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const struct glsl_type *type,
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int location)
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{
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if (glsl_type_is_scalar(type) || glsl_type_is_vector(type) || glsl_type_is_matrix(type)) {
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unsigned attrib_count = glsl_count_attribute_slots(type, false);
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if (glsl_type_is_16bit(type)) {
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ctx->float16_shaded_mask |= ((1ull << attrib_count) - 1) << location;
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}
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} else if (glsl_type_is_array(type)) {
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unsigned stride = glsl_count_attribute_slots(glsl_get_array_element(type), false);
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for (unsigned i = 0; i < glsl_get_length(type); ++i) {
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mark_16bit_fs_input(ctx, glsl_get_array_element(type), location + i * stride);
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}
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} else {
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assert(glsl_type_is_struct_or_ifc(type));
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for (unsigned i = 0; i < glsl_get_length(type); i++) {
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mark_16bit_fs_input(ctx, glsl_get_struct_field(type, i), location);
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location += glsl_count_attribute_slots(glsl_get_struct_field(type, i), false);
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}
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}
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}
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static void
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handle_fs_input_decl(struct radv_shader_context *ctx,
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struct nir_variable *variable)
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{
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int idx = variable->data.location;
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unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
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LLVMValueRef interp = NULL;
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uint64_t mask;
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variable->data.driver_location = idx * 4;
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if (variable->data.compact) {
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unsigned component_count = variable->data.location_frac +
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glsl_get_length(variable->type);
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attrib_count = (component_count + 3) / 4;
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} else
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mark_16bit_fs_input(ctx, variable->type, idx);
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mask = ((1ull << attrib_count) - 1) << variable->data.location;
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if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT ||
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glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT16 ||
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glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_STRUCT) {
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unsigned interp_type;
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if (variable->data.sample)
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interp_type = INTERP_SAMPLE;
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else if (variable->data.centroid)
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interp_type = INTERP_CENTROID;
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else
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interp_type = INTERP_CENTER;
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interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
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}
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if (interp == NULL)
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interp = LLVMGetUndef(ctx->ac.i32);
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for (unsigned i = 0; i < attrib_count; ++i)
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ctx->inputs[ac_llvm_reg_index_soa(idx + i, 0)] = interp;
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ctx->input_mask |= mask;
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}
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static void
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handle_vs_inputs(struct radv_shader_context *ctx,
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struct nir_shader *nir) {
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@ -2467,64 +2342,6 @@ prepare_interp_optimize(struct radv_shader_context *ctx,
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}
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}
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static void
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handle_fs_inputs(struct radv_shader_context *ctx,
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struct nir_shader *nir)
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{
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prepare_interp_optimize(ctx, nir);
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nir_foreach_variable(variable, &nir->inputs)
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handle_fs_input_decl(ctx, variable);
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unsigned index = 0;
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if (ctx->shader_info->info.needs_multiview_view_index ||
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ctx->shader_info->info.ps.layer_input) {
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ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
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ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)] = LLVMGetUndef(ctx->ac.i32);
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}
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for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
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LLVMValueRef interp_param;
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LLVMValueRef *inputs = ctx->inputs +ac_llvm_reg_index_soa(i, 0);
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if (!(ctx->input_mask & (1ull << i)))
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continue;
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if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
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i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
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interp_param = *inputs;
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bool float16 = (ctx->float16_shaded_mask >> i) & 1;
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interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask, float16,
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inputs);
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if (LLVMIsUndef(interp_param))
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ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
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if (float16)
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ctx->shader_info->fs.float16_shaded_mask |= 1u << index;
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if (i >= VARYING_SLOT_VAR0)
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ctx->abi.fs_input_attr_indices[i - VARYING_SLOT_VAR0] = index;
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++index;
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} else if (i == VARYING_SLOT_CLIP_DIST0) {
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int length = ctx->shader_info->info.ps.num_input_clips_culls;
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for (unsigned j = 0; j < length; j += 4) {
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inputs = ctx->inputs + ac_llvm_reg_index_soa(i, j);
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interp_param = *inputs;
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interp_fs_input(ctx, index, interp_param,
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ctx->abi.prim_mask, false, inputs);
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++index;
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}
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}
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}
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ctx->shader_info->fs.num_interp = index;
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ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
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if (ctx->shader_info->info.needs_multiview_view_index)
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ctx->abi.view_index = ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
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}
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static void
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scan_shader_output_decl(struct radv_shader_context *ctx,
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struct nir_variable *variable,
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@ -3877,8 +3694,6 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
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ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
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memset(shader_info, 0, sizeof(*shader_info));
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radv_nir_shader_info_init(&shader_info->info);
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for(int i = 0; i < shader_count; ++i)
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@ -4004,7 +3819,7 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
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}
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if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
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handle_fs_inputs(&ctx, shaders[i]);
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prepare_interp_optimize(&ctx, shaders[i]);
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else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
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handle_vs_inputs(&ctx, shaders[i]);
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else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
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@ -76,7 +76,8 @@ static const struct nir_shader_compiler_options nir_options = {
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.lower_fpow = true,
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.lower_mul_2x32_64 = true,
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.lower_rotate = true,
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.max_unroll_iterations = 32
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.max_unroll_iterations = 32,
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.use_interpolated_input_intrinsics = true,
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};
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VkResult radv_CreateShaderModule(
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@ -361,11 +362,11 @@ radv_shader_compile_to_nir(struct radv_device *device,
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nir_lower_vars_to_ssa(nir);
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if (nir->info.stage == MESA_SHADER_VERTEX ||
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nir->info.stage == MESA_SHADER_GEOMETRY) {
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nir->info.stage == MESA_SHADER_GEOMETRY ||
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nir->info.stage == MESA_SHADER_FRAGMENT) {
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NIR_PASS_V(nir, nir_lower_io_to_temporaries,
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nir_shader_get_entrypoint(nir), true, true);
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} else if (nir->info.stage == MESA_SHADER_TESS_EVAL||
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nir->info.stage == MESA_SHADER_FRAGMENT) {
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} else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
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NIR_PASS_V(nir, nir_lower_io_to_temporaries,
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nir_shader_get_entrypoint(nir), true, false);
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}
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@ -405,6 +406,152 @@ radv_shader_compile_to_nir(struct radv_device *device,
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return nir;
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}
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static void mark_16bit_fs_input(struct radv_shader_variant_info *shader_info,
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const struct glsl_type *type,
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int location)
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{
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if (glsl_type_is_scalar(type) || glsl_type_is_vector(type) || glsl_type_is_matrix(type)) {
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unsigned attrib_count = glsl_count_attribute_slots(type, false);
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if (glsl_type_is_16bit(type)) {
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shader_info->fs.float16_shaded_mask |= ((1ull << attrib_count) - 1) << location;
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}
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} else if (glsl_type_is_array(type)) {
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unsigned stride = glsl_count_attribute_slots(glsl_get_array_element(type), false);
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for (unsigned i = 0; i < glsl_get_length(type); ++i) {
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mark_16bit_fs_input(shader_info, glsl_get_array_element(type), location + i * stride);
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}
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} else {
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assert(glsl_type_is_struct_or_ifc(type));
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for (unsigned i = 0; i < glsl_get_length(type); i++) {
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mark_16bit_fs_input(shader_info, glsl_get_struct_field(type, i), location);
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location += glsl_count_attribute_slots(glsl_get_struct_field(type, i), false);
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}
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}
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}
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static void
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handle_fs_input_decl(struct radv_shader_variant_info *shader_info,
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struct nir_variable *variable)
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{
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unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
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if (variable->data.compact) {
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unsigned component_count = variable->data.location_frac +
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glsl_get_length(variable->type);
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attrib_count = (component_count + 3) / 4;
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} else {
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mark_16bit_fs_input(shader_info, variable->type,
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variable->data.driver_location);
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}
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uint64_t mask = ((1ull << attrib_count) - 1);
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if (variable->data.interpolation == INTERP_MODE_FLAT)
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shader_info->fs.flat_shaded_mask |= mask << variable->data.driver_location;
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if (variable->data.location >= VARYING_SLOT_VAR0)
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shader_info->fs.input_mask |= mask << (variable->data.location - VARYING_SLOT_VAR0);
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}
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static int
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type_size_vec4(const struct glsl_type *type, bool bindless)
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{
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return glsl_count_attribute_slots(type, false);
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}
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static nir_variable *
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find_layer_in_var(nir_shader *nir)
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{
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nir_foreach_variable(var, &nir->inputs) {
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if (var->data.location == VARYING_SLOT_LAYER) {
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return var;
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}
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}
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nir_variable *var =
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nir_variable_create(nir, nir_var_shader_in, glsl_int_type(), "layer id");
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var->data.location = VARYING_SLOT_LAYER;
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var->data.interpolation = INTERP_MODE_FLAT;
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return var;
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}
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/* We use layered rendering to implement multiview, which means we need to map
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* view_index to gl_Layer. The attachment lowering also uses needs to know the
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* layer so that it can sample from the correct layer. The code generates a
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* load from the layer_id sysval, but since we don't have a way to get at this
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* information from the fragment shader, we also need to lower this to the
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* gl_Layer varying. This pass lowers both to a varying load from the LAYER
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* slot, before lowering io, so that nir_assign_var_locations() will give the
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* LAYER varying the correct driver_location.
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*/
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static bool
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lower_view_index(nir_shader *nir)
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{
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bool progress = false;
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nir_function_impl *entry = nir_shader_get_entrypoint(nir);
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nir_builder b;
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nir_builder_init(&b, entry);
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nir_variable *layer = NULL;
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nir_foreach_block(block, entry) {
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nir_foreach_instr_safe(instr, block) {
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if (instr->type != nir_instr_type_intrinsic)
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continue;
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nir_intrinsic_instr *load = nir_instr_as_intrinsic(instr);
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if (load->intrinsic != nir_intrinsic_load_view_index &&
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load->intrinsic != nir_intrinsic_load_layer_id)
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continue;
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if (!layer)
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layer = find_layer_in_var(nir);
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b.cursor = nir_before_instr(instr);
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nir_ssa_def *def = nir_load_var(&b, layer);
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nir_ssa_def_rewrite_uses(&load->dest.ssa,
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nir_src_for_ssa(def));
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nir_instr_remove(instr);
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progress = true;
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}
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}
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return progress;
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}
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/* Gather information needed to setup the vs<->ps linking registers in
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* radv_pipeline_generate_ps_inputs().
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*/
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static void
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handle_fs_inputs(nir_shader *nir, struct radv_shader_variant_info *shader_info)
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{
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shader_info->fs.num_interp = nir->num_inputs;
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nir_foreach_variable(variable, &nir->inputs)
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handle_fs_input_decl(shader_info, variable);
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}
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static void
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lower_fs_io(nir_shader *nir, struct radv_shader_variant_info *shader_info)
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{
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NIR_PASS_V(nir, lower_view_index);
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nir_assign_io_var_locations(&nir->inputs, &nir->num_inputs,
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MESA_SHADER_FRAGMENT);
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handle_fs_inputs(nir, shader_info);
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NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
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/* This pass needs actual constants */
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nir_opt_constant_folding(nir);
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NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
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radv_optimize_nir(nir, false, false);
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}
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void *
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radv_alloc_shader_memory(struct radv_device *device,
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struct radv_shader_variant *shader)
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@ -853,6 +1000,9 @@ shader_variant_compile(struct radv_device *device,
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struct radv_shader_variant_info variant_info = {0};
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bool thread_compiler;
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if (shaders[0]->info.stage == MESA_SHADER_FRAGMENT)
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lower_fs_io(shaders[0], &variant_info);
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options->family = chip_family;
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options->chip_class = device->physical_device->rad_info.chip_class;
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options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
|
||||
|
|
|
|||
|
|
@ -224,7 +224,7 @@ gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
|
|||
struct radv_shader_info *info)
|
||||
{
|
||||
switch (instr->intrinsic) {
|
||||
case nir_intrinsic_interp_deref_at_sample:
|
||||
case nir_intrinsic_load_barycentric_at_sample:
|
||||
info->ps.needs_sample_positions = true;
|
||||
break;
|
||||
case nir_intrinsic_load_draw_id:
|
||||
|
|
|
|||
Loading…
Reference in New Issue