i965: Rename gen10_emit_isp_disable to gen7_emit_isp_disable
It's used on Gen7+, and there's nothing Gen10-specific about it. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6899>
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@ -166,7 +166,7 @@ gen7_emit_vs_workaround_flush(struct brw_context *brw)
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* so that it doesn't hang a previous 3DPRIMITIVE.
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*/
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void
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gen10_emit_isp_disable(struct brw_context *brw)
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gen7_emit_isp_disable(struct brw_context *brw)
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{
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brw->vtbl.emit_raw_pipe_control(brw,
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PIPE_CONTROL_STALL_AT_SCOREBOARD |
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@ -90,6 +90,6 @@ void brw_emit_post_sync_nonzero_flush(struct brw_context *brw);
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void brw_emit_depth_stall_flushes(struct brw_context *brw);
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void gen7_emit_vs_workaround_flush(struct brw_context *brw);
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void gen7_emit_cs_stall_flush(struct brw_context *brw);
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void gen10_emit_isp_disable(struct brw_context *brw);
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void gen7_emit_isp_disable(struct brw_context *brw);
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#endif
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@ -644,7 +644,7 @@ brw_finish_batch(struct brw_context *brw)
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/* Do not restore push constant packets during context restore. */
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if (devinfo->gen >= 7)
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gen10_emit_isp_disable(brw);
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gen7_emit_isp_disable(brw);
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/* Emit MI_BATCH_BUFFER_END to finish our batch. Note that execbuf2
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* requires our batch size to be QWord aligned, so we pad it out if
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