nv30, nv40: non-trivially unify nv[34]0_screen.c
The files have the same structure but are substantially different. They are unified with appropriate conditionals.
This commit is contained in:
parent
840c36f5e6
commit
10f464fc10
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@ -27,10 +27,7 @@
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#define NOUVEAU_BUFFER_USAGE_NO_RENDER (1 << 19)
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extern struct pipe_screen *
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nv30_screen_create(struct pipe_winsys *ws, struct nouveau_device *);
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extern struct pipe_screen *
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nv40_screen_create(struct pipe_winsys *ws, struct nouveau_device *);
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nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *);
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extern struct pipe_screen *
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nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *);
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@ -6,7 +6,6 @@ LIBNAME = nv30
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C_SOURCES = \
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nv30_context.c \
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nv30_fragtex.c \
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nv30_screen.c \
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nv30_state.c
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LIBRARY_INCLUDES = -I$(TOP)/src/gallium/drivers/nvfx
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@ -6,7 +6,6 @@ LIBNAME = nv40
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C_SOURCES = \
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nv40_context.c \
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nv40_fragtex.c \
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nv40_screen.c \
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nv40_state.c
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LIBRARY_INCLUDES = -I$(TOP)/src/gallium/drivers/nvfx
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@ -1,322 +0,0 @@
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#include "pipe/p_screen.h"
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#include "nv40_context.h"
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#include "nvfx_screen.h"
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#define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
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#define NV4X_GRCLASS4497_CHIPSETS 0x00005450
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#define NV6X_GRCLASS4497_CHIPSETS 0x00000088
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static int
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nv40_screen_get_param(struct pipe_screen *pscreen, int param)
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{
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struct nvfx_screen *screen = nvfx_screen(pscreen);
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switch (param) {
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case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
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return 16;
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case PIPE_CAP_NPOT_TEXTURES:
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return 1;
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case PIPE_CAP_TWO_SIDED_STENCIL:
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return 1;
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case PIPE_CAP_GLSL:
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return 0;
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case PIPE_CAP_ANISOTROPIC_FILTER:
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return 1;
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case PIPE_CAP_POINT_SPRITE:
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return 1;
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case PIPE_CAP_MAX_RENDER_TARGETS:
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return 4;
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case PIPE_CAP_OCCLUSION_QUERY:
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return 1;
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case PIPE_CAP_TEXTURE_SHADOW_MAP:
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return 1;
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case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
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return 13;
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case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
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return 10;
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case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
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return 13;
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case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
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case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
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return 1;
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case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
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return 0; /* We have 4 - but unsupported currently */
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case PIPE_CAP_TGSI_CONT_SUPPORTED:
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return 0;
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case PIPE_CAP_BLEND_EQUATION_SEPARATE:
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return 1;
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case NOUVEAU_CAP_HW_VTXBUF:
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return 1;
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case NOUVEAU_CAP_HW_IDXBUF:
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if (screen->eng3d->grclass == NV40TCL)
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return 1;
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return 0;
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case PIPE_CAP_INDEP_BLEND_ENABLE:
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return 0;
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case PIPE_CAP_INDEP_BLEND_FUNC:
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return 0;
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case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
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case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
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return 1;
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case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
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case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
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return 0;
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case PIPE_CAP_MAX_COMBINED_SAMPLERS:
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return 16;
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default:
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NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
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return 0;
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}
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}
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static float
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nv40_screen_get_paramf(struct pipe_screen *pscreen, int param)
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{
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switch (param) {
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case PIPE_CAP_MAX_LINE_WIDTH:
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case PIPE_CAP_MAX_LINE_WIDTH_AA:
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return 10.0;
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case PIPE_CAP_MAX_POINT_WIDTH:
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case PIPE_CAP_MAX_POINT_WIDTH_AA:
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return 64.0;
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case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
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return 16.0;
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case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
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return 16.0;
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default:
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NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
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return 0.0;
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}
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}
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static boolean
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nv40_screen_surface_format_supported(struct pipe_screen *pscreen,
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enum pipe_format format,
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enum pipe_texture_target target,
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unsigned tex_usage, unsigned geom_flags)
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{
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if (tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET) {
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switch (format) {
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case PIPE_FORMAT_B8G8R8A8_UNORM:
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case PIPE_FORMAT_B5G6R5_UNORM:
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return TRUE;
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default:
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break;
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}
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} else
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if (tex_usage & PIPE_TEXTURE_USAGE_DEPTH_STENCIL) {
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switch (format) {
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case PIPE_FORMAT_S8Z24_UNORM:
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case PIPE_FORMAT_X8Z24_UNORM:
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case PIPE_FORMAT_Z16_UNORM:
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return TRUE;
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default:
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break;
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}
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} else {
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switch (format) {
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case PIPE_FORMAT_B8G8R8A8_UNORM:
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case PIPE_FORMAT_B5G5R5A1_UNORM:
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case PIPE_FORMAT_B4G4R4A4_UNORM:
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case PIPE_FORMAT_B5G6R5_UNORM:
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case PIPE_FORMAT_R16_SNORM:
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case PIPE_FORMAT_L8_UNORM:
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case PIPE_FORMAT_A8_UNORM:
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case PIPE_FORMAT_I8_UNORM:
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case PIPE_FORMAT_L8A8_UNORM:
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case PIPE_FORMAT_Z16_UNORM:
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case PIPE_FORMAT_S8Z24_UNORM:
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case PIPE_FORMAT_DXT1_RGB:
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case PIPE_FORMAT_DXT1_RGBA:
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case PIPE_FORMAT_DXT3_RGBA:
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case PIPE_FORMAT_DXT5_RGBA:
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return TRUE;
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default:
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break;
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}
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}
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return FALSE;
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}
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static struct pipe_buffer *
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nv40_surface_buffer(struct pipe_surface *surf)
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{
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struct nvfx_miptree *mt = (struct nvfx_miptree *)surf->texture;
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return mt->buffer;
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}
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static void
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nv40_screen_destroy(struct pipe_screen *pscreen)
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{
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struct nvfx_screen *screen = nvfx_screen(pscreen);
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unsigned i;
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for (i = 0; i < NVFX_STATE_MAX; i++) {
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if (screen->state[i])
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so_ref(NULL, &screen->state[i]);
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}
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nouveau_resource_destroy(&screen->vp_exec_heap);
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nouveau_resource_destroy(&screen->vp_data_heap);
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nouveau_resource_destroy(&screen->query_heap);
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nouveau_notifier_free(&screen->query);
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nouveau_notifier_free(&screen->sync);
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nouveau_grobj_free(&screen->eng3d);
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nv04_surface_2d_takedown(&screen->eng2d);
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nouveau_screen_fini(&screen->base);
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FREE(pscreen);
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}
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struct pipe_screen *
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nv40_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
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{
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struct nvfx_screen *screen = CALLOC_STRUCT(nvfx_screen);
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struct nouveau_channel *chan;
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struct pipe_screen *pscreen;
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struct nouveau_stateobj *so;
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unsigned eng3d_class = 0;
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int ret;
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if (!screen)
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return NULL;
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screen->is_nv4x = ~0;
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pscreen = &screen->base.base;
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ret = nouveau_screen_init(&screen->base, dev);
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if (ret) {
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nv40_screen_destroy(pscreen);
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return NULL;
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}
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chan = screen->base.channel;
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pscreen->winsys = ws;
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pscreen->destroy = nv40_screen_destroy;
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pscreen->get_param = nv40_screen_get_param;
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pscreen->get_paramf = nv40_screen_get_paramf;
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pscreen->is_format_supported = nv40_screen_surface_format_supported;
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pscreen->context_create = nv40_create;
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nvfx_screen_init_miptree_functions(pscreen);
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/* 3D object */
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switch (dev->chipset & 0xf0) {
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case 0x40:
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if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
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eng3d_class = NV40TCL;
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else
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if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
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eng3d_class = NV44TCL;
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break;
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case 0x60:
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if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
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eng3d_class = NV44TCL;
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break;
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}
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if (!eng3d_class) {
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NOUVEAU_ERR("Unknown nv4x chipset: nv%02x\n", dev->chipset);
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return NULL;
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}
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ret = nouveau_grobj_alloc(chan, 0xbeef3097, eng3d_class, &screen->eng3d);
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if (ret) {
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NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
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return FALSE;
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}
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/* 2D engine setup */
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screen->eng2d = nv04_surface_2d_init(&screen->base);
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screen->eng2d->buf = nv40_surface_buffer;
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/* Notifier for sync purposes */
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ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
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if (ret) {
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NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
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nv40_screen_destroy(pscreen);
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return NULL;
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}
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/* Query objects */
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ret = nouveau_notifier_alloc(chan, 0xbeef0302, 32, &screen->query);
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if (ret) {
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NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
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nv40_screen_destroy(pscreen);
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return NULL;
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}
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nouveau_resource_init(&screen->query_heap, 0, 32);
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if (ret) {
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NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
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nv40_screen_destroy(pscreen);
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return NULL;
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}
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/* Vtxprog resources */
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if (nouveau_resource_init(&screen->vp_exec_heap, 0, 512) ||
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nouveau_resource_init(&screen->vp_data_heap, 0, 256)) {
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nv40_screen_destroy(pscreen);
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return NULL;
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}
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/* Static eng3d initialisation */
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so = so_new(16, 25, 0);
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so_method(so, screen->eng3d, NV34TCL_DMA_NOTIFY, 1);
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so_data (so, screen->sync->handle);
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so_method(so, screen->eng3d, NV34TCL_DMA_TEXTURE0, 2);
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so_data (so, chan->vram->handle);
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so_data (so, chan->gart->handle);
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so_method(so, screen->eng3d, NV34TCL_DMA_COLOR1, 1);
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so_data (so, chan->vram->handle);
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so_method(so, screen->eng3d, NV34TCL_DMA_COLOR0, 2);
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so_data (so, chan->vram->handle);
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so_data (so, chan->vram->handle);
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so_method(so, screen->eng3d, NV34TCL_DMA_VTXBUF0, 2);
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so_data (so, chan->vram->handle);
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so_data (so, chan->gart->handle);
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so_method(so, screen->eng3d, NV34TCL_DMA_FENCE, 2);
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so_data (so, 0);
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so_data (so, screen->query->handle);
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so_method(so, screen->eng3d, NV34TCL_DMA_IN_MEMORY7, 2);
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so_data (so, chan->vram->handle);
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so_data (so, chan->vram->handle);
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so_method(so, screen->eng3d, NV40TCL_DMA_COLOR2, 2);
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so_data (so, chan->vram->handle);
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so_data (so, chan->vram->handle);
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so_method(so, screen->eng3d, 0x1ea4, 3);
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so_data (so, 0x00000010);
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so_data (so, 0x01000100);
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so_data (so, 0xff800006);
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/* vtxprog output routing */
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so_method(so, screen->eng3d, 0x1fc4, 1);
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so_data (so, 0x06144321);
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so_method(so, screen->eng3d, 0x1fc8, 2);
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so_data (so, 0xedcba987);
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so_data (so, 0x00000021);
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so_method(so, screen->eng3d, 0x1fd0, 1);
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so_data (so, 0x00171615);
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so_method(so, screen->eng3d, 0x1fd4, 1);
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so_data (so, 0x001b1a19);
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so_method(so, screen->eng3d, 0x1ef8, 1);
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so_data (so, 0x0020ffff);
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so_method(so, screen->eng3d, 0x1d64, 1);
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so_data (so, 0x00d30000);
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so_method(so, screen->eng3d, 0x1e94, 1);
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so_data (so, 0x00000001);
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so_emit(chan, so);
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so_ref(NULL, &so);
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nouveau_pushbuf_flush(chan, 0);
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return pscreen;
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}
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@ -9,6 +9,7 @@ C_SOURCES = \
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nvfx_fragprog.c \
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nvfx_miptree.c \
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nvfx_query.c \
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nvfx_screen.c \
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nvfx_state.c \
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nvfx_state_blend.c \
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nvfx_state_emit.c \
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@ -3,7 +3,8 @@
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#include "nouveau/nouveau_screen.h"
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#include "nv30_context.h"
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#include "nv30/nv30_context.h"
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#include "nv40/nv40_context.h"
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#include "nvfx_screen.h"
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#define NV30TCL_CHIPSET_3X_MASK 0x00000003
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#define NV35TCL_CHIPSET_3X_MASK 0x000001e0
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/* FIXME: It seems I should not include directly ../../winsys/drm/nouveau/drm/nouveau_drm_api.h
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* to get the pointer to the context front buffer, so I copied nouveau_winsys here.
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* nv30_screen_surface_format_supported() can then use it to enforce creating fbo
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* with same number of bits everywhere.
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*/
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* to get the pointer to the context front buffer, so I copied nouveau_winsys here.
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* nv30_screen_surface_format_supported() can then use it to enforce creating fbo
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* with same number of bits everywhere.
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*/
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struct nouveau_winsys {
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struct pipe_winsys base;
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@ -22,15 +23,21 @@ struct nouveau_winsys {
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struct pipe_surface *front;
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};
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#define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
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#define NV4X_GRCLASS4497_CHIPSETS 0x00005450
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#define NV6X_GRCLASS4497_CHIPSETS 0x00000088
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static int
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nv30_screen_get_param(struct pipe_screen *pscreen, int param)
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nvfx_screen_get_param(struct pipe_screen *pscreen, int param)
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{
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struct nvfx_screen *screen = nvfx_screen(pscreen);
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switch (param) {
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case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
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return 8;
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/* TODO: check this */
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return screen->is_nv4x ? 16 : 8;
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case PIPE_CAP_NPOT_TEXTURES:
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return 0;
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return !!screen->is_nv4x;
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case PIPE_CAP_TWO_SIDED_STENCIL:
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return 1;
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case PIPE_CAP_GLSL:
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@ -40,7 +47,7 @@ nv30_screen_get_param(struct pipe_screen *pscreen, int param)
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case PIPE_CAP_POINT_SPRITE:
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return 1;
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case PIPE_CAP_MAX_RENDER_TARGETS:
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return 2;
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return screen->is_nv4x ? 4 : 2;
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case PIPE_CAP_OCCLUSION_QUERY:
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return 1;
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case PIPE_CAP_TEXTURE_SHADOW_MAP:
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@ -52,21 +59,26 @@ nv30_screen_get_param(struct pipe_screen *pscreen, int param)
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case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
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return 13;
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case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
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return 0;
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return !!screen->is_nv4x;
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case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
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return 1;
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case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
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return 0;
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return 0; /* We have 4 on nv40 - but unsupported currently */
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case PIPE_CAP_TGSI_CONT_SUPPORTED:
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return 0;
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case PIPE_CAP_BLEND_EQUATION_SEPARATE:
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return 0;
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return !!screen->is_nv4x;
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case NOUVEAU_CAP_HW_VTXBUF:
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/* TODO: this is almost surely wrong */
|
||||
return !!screen->is_nv4x;
|
||||
case NOUVEAU_CAP_HW_IDXBUF:
|
||||
return 1;
|
||||
/* TODO: this is also almost surely wrong */
|
||||
return screen->is_nv4x && screen->eng3d->grclass == NV40TCL;
|
||||
case PIPE_CAP_MAX_COMBINED_SAMPLERS:
|
||||
return 16;
|
||||
case PIPE_CAP_INDEP_BLEND_ENABLE:
|
||||
/* TODO: on nv40 we have separate color masks */
|
||||
/* TODO: nv40 mrt blending is probably broken */
|
||||
return 0;
|
||||
case PIPE_CAP_INDEP_BLEND_FUNC:
|
||||
return 0;
|
||||
|
@ -83,8 +95,10 @@ nv30_screen_get_param(struct pipe_screen *pscreen, int param)
|
|||
}
|
||||
|
||||
static float
|
||||
nv30_screen_get_paramf(struct pipe_screen *pscreen, int param)
|
||||
nvfx_screen_get_paramf(struct pipe_screen *pscreen, int param)
|
||||
{
|
||||
struct nvfx_screen *screen = nvfx_screen(pscreen);
|
||||
|
||||
switch (param) {
|
||||
case PIPE_CAP_MAX_LINE_WIDTH:
|
||||
case PIPE_CAP_MAX_LINE_WIDTH_AA:
|
||||
|
@ -93,9 +107,9 @@ nv30_screen_get_paramf(struct pipe_screen *pscreen, int param)
|
|||
case PIPE_CAP_MAX_POINT_WIDTH_AA:
|
||||
return 64.0;
|
||||
case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
|
||||
return 8.0;
|
||||
return screen->is_nv4x ? 16.0 : 8.0;
|
||||
case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
|
||||
return 4.0;
|
||||
return screen->is_nv4x ? 16.0 : 4.0;
|
||||
default:
|
||||
NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
|
||||
return 0.0;
|
||||
|
@ -103,11 +117,12 @@ nv30_screen_get_paramf(struct pipe_screen *pscreen, int param)
|
|||
}
|
||||
|
||||
static boolean
|
||||
nv30_screen_surface_format_supported(struct pipe_screen *pscreen,
|
||||
nvfx_screen_surface_format_supported(struct pipe_screen *pscreen,
|
||||
enum pipe_format format,
|
||||
enum pipe_texture_target target,
|
||||
unsigned tex_usage, unsigned geom_flags)
|
||||
{
|
||||
struct nvfx_screen *screen = nvfx_screen(pscreen);
|
||||
struct pipe_surface *front = ((struct nouveau_winsys *) pscreen->winsys)->front;
|
||||
|
||||
if (tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET) {
|
||||
|
@ -125,9 +140,9 @@ nv30_screen_surface_format_supported(struct pipe_screen *pscreen,
|
|||
case PIPE_FORMAT_X8Z24_UNORM:
|
||||
return TRUE;
|
||||
case PIPE_FORMAT_Z16_UNORM:
|
||||
if (front) {
|
||||
/* TODO: this nv30 limitation probably does not exist */
|
||||
if (!screen->is_nv4x && front)
|
||||
return (front->format == PIPE_FORMAT_B5G6R5_UNORM);
|
||||
}
|
||||
return TRUE;
|
||||
default:
|
||||
break;
|
||||
|
@ -144,7 +159,14 @@ nv30_screen_surface_format_supported(struct pipe_screen *pscreen,
|
|||
case PIPE_FORMAT_L8A8_UNORM:
|
||||
case PIPE_FORMAT_Z16_UNORM:
|
||||
case PIPE_FORMAT_S8Z24_UNORM:
|
||||
case PIPE_FORMAT_DXT1_RGB:
|
||||
case PIPE_FORMAT_DXT1_RGBA:
|
||||
case PIPE_FORMAT_DXT3_RGBA:
|
||||
case PIPE_FORMAT_DXT5_RGBA:
|
||||
return TRUE;
|
||||
/* TODO: does nv30 support this? */
|
||||
case PIPE_FORMAT_R16_SNORM:
|
||||
return !!screen->is_nv4x;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
@ -154,7 +176,7 @@ nv30_screen_surface_format_supported(struct pipe_screen *pscreen,
|
|||
}
|
||||
|
||||
static struct pipe_buffer *
|
||||
nv30_surface_buffer(struct pipe_surface *surf)
|
||||
nvfx_surface_buffer(struct pipe_surface *surf)
|
||||
{
|
||||
struct nvfx_miptree *mt = (struct nvfx_miptree *)surf->texture;
|
||||
|
||||
|
@ -162,7 +184,7 @@ nv30_surface_buffer(struct pipe_surface *surf)
|
|||
}
|
||||
|
||||
static void
|
||||
nv30_screen_destroy(struct pipe_screen *pscreen)
|
||||
nvfx_screen_destroy(struct pipe_screen *pscreen)
|
||||
{
|
||||
struct nvfx_screen *screen = nvfx_screen(pscreen);
|
||||
unsigned i;
|
||||
|
@ -185,121 +207,12 @@ nv30_screen_destroy(struct pipe_screen *pscreen)
|
|||
FREE(pscreen);
|
||||
}
|
||||
|
||||
struct pipe_screen *
|
||||
nv30_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
|
||||
static void nv30_screen_init(struct nvfx_screen *screen, struct nouveau_stateobj* so)
|
||||
{
|
||||
struct nvfx_screen *screen = CALLOC_STRUCT(nvfx_screen);
|
||||
struct nouveau_channel *chan;
|
||||
struct pipe_screen *pscreen;
|
||||
struct nouveau_stateobj *so;
|
||||
unsigned eng3d_class = 0;
|
||||
int ret, i;
|
||||
|
||||
if (!screen)
|
||||
return NULL;
|
||||
pscreen = &screen->base.base;
|
||||
|
||||
ret = nouveau_screen_init(&screen->base, dev);
|
||||
if (ret) {
|
||||
nv30_screen_destroy(pscreen);
|
||||
return NULL;
|
||||
}
|
||||
chan = screen->base.channel;
|
||||
|
||||
pscreen->winsys = ws;
|
||||
pscreen->destroy = nv30_screen_destroy;
|
||||
pscreen->get_param = nv30_screen_get_param;
|
||||
pscreen->get_paramf = nv30_screen_get_paramf;
|
||||
pscreen->is_format_supported = nv30_screen_surface_format_supported;
|
||||
pscreen->context_create = nv30_create;
|
||||
|
||||
nvfx_screen_init_miptree_functions(pscreen);
|
||||
|
||||
/* 3D object */
|
||||
switch (dev->chipset & 0xf0) {
|
||||
case 0x30:
|
||||
if (NV30TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
|
||||
eng3d_class = 0x0397;
|
||||
else
|
||||
if (NV34TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
|
||||
eng3d_class = 0x0697;
|
||||
else
|
||||
if (NV35TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
|
||||
eng3d_class = 0x0497;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (!eng3d_class) {
|
||||
NOUVEAU_ERR("Unknown nv3x chipset: nv%02x\n", dev->chipset);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
ret = nouveau_grobj_alloc(chan, 0xbeef3097, eng3d_class,
|
||||
&screen->eng3d);
|
||||
if (ret) {
|
||||
NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/* 2D engine setup */
|
||||
screen->eng2d = nv04_surface_2d_init(&screen->base);
|
||||
screen->eng2d->buf = nv30_surface_buffer;
|
||||
|
||||
/* Notifier for sync purposes */
|
||||
ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
|
||||
if (ret) {
|
||||
NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
|
||||
nv30_screen_destroy(pscreen);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Query objects */
|
||||
ret = nouveau_notifier_alloc(chan, 0xbeef0302, 32, &screen->query);
|
||||
if (ret) {
|
||||
NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
|
||||
nv30_screen_destroy(pscreen);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
ret = nouveau_resource_init(&screen->query_heap, 0, 32);
|
||||
if (ret) {
|
||||
NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
|
||||
nv30_screen_destroy(pscreen);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Vtxprog resources */
|
||||
if (nouveau_resource_init(&screen->vp_exec_heap, 0, 256) ||
|
||||
nouveau_resource_init(&screen->vp_data_heap, 0, 256)) {
|
||||
nv30_screen_destroy(pscreen);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Static eng3d initialisation */
|
||||
so = so_new(36, 60, 0);
|
||||
so_method(so, screen->eng3d, NV34TCL_DMA_NOTIFY, 1);
|
||||
so_data (so, screen->sync->handle);
|
||||
so_method(so, screen->eng3d, NV34TCL_DMA_TEXTURE0, 2);
|
||||
so_data (so, chan->vram->handle);
|
||||
so_data (so, chan->gart->handle);
|
||||
so_method(so, screen->eng3d, NV34TCL_DMA_COLOR1, 1);
|
||||
so_data (so, chan->vram->handle);
|
||||
so_method(so, screen->eng3d, NV34TCL_DMA_COLOR0, 2);
|
||||
so_data (so, chan->vram->handle);
|
||||
so_data (so, chan->vram->handle);
|
||||
so_method(so, screen->eng3d, NV34TCL_DMA_VTXBUF0, 2);
|
||||
so_data (so, chan->vram->handle);
|
||||
so_data (so, chan->gart->handle);
|
||||
/* so_method(so, screen->eng3d, NV34TCL_DMA_FENCE, 2);
|
||||
so_data (so, 0);
|
||||
so_data (so, screen->query->handle);*/
|
||||
so_method(so, screen->eng3d, NV34TCL_DMA_IN_MEMORY7, 1);
|
||||
so_data (so, chan->vram->handle);
|
||||
so_method(so, screen->eng3d, NV34TCL_DMA_IN_MEMORY8, 1);
|
||||
so_data (so, chan->vram->handle);
|
||||
screen->base.base.context_create = nv30_create;
|
||||
int i;
|
||||
|
||||
/* TODO: perhaps we should do some of this on nv40 too? */
|
||||
for (i=1; i<8; i++) {
|
||||
so_method(so, screen->eng3d, NV34TCL_VIEWPORT_CLIP_HORIZ(i), 1);
|
||||
so_data (so, 0);
|
||||
|
@ -352,6 +265,168 @@ nv30_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
|
|||
/* enables use of vp rather than fixed-function somehow */
|
||||
so_method(so, screen->eng3d, 0x1e94, 1);
|
||||
so_data (so, 0x13);
|
||||
}
|
||||
|
||||
static void nv40_screen_init(struct nvfx_screen *screen, struct nouveau_stateobj* so)
|
||||
{
|
||||
screen->base.base.context_create = nv40_create;
|
||||
|
||||
so_method(so, screen->eng3d, NV40TCL_DMA_COLOR2, 2);
|
||||
so_data (so, screen->base.channel->vram->handle);
|
||||
so_data (so, screen->base.channel->vram->handle);
|
||||
|
||||
so_method(so, screen->eng3d, 0x1ea4, 3);
|
||||
so_data (so, 0x00000010);
|
||||
so_data (so, 0x01000100);
|
||||
so_data (so, 0xff800006);
|
||||
|
||||
/* vtxprog output routing */
|
||||
so_method(so, screen->eng3d, 0x1fc4, 1);
|
||||
so_data (so, 0x06144321);
|
||||
so_method(so, screen->eng3d, 0x1fc8, 2);
|
||||
so_data (so, 0xedcba987);
|
||||
so_data (so, 0x00000021);
|
||||
so_method(so, screen->eng3d, 0x1fd0, 1);
|
||||
so_data (so, 0x00171615);
|
||||
so_method(so, screen->eng3d, 0x1fd4, 1);
|
||||
so_data (so, 0x001b1a19);
|
||||
|
||||
so_method(so, screen->eng3d, 0x1ef8, 1);
|
||||
so_data (so, 0x0020ffff);
|
||||
so_method(so, screen->eng3d, 0x1d64, 1);
|
||||
so_data (so, 0x00d30000);
|
||||
so_method(so, screen->eng3d, 0x1e94, 1);
|
||||
so_data (so, 0x00000001);
|
||||
}
|
||||
|
||||
struct pipe_screen *
|
||||
nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
|
||||
{
|
||||
struct nvfx_screen *screen = CALLOC_STRUCT(nvfx_screen);
|
||||
struct nouveau_channel *chan;
|
||||
struct pipe_screen *pscreen;
|
||||
struct nouveau_stateobj *so;
|
||||
unsigned eng3d_class = 0;
|
||||
int ret;
|
||||
|
||||
if (!screen)
|
||||
return NULL;
|
||||
|
||||
pscreen = &screen->base.base;
|
||||
|
||||
ret = nouveau_screen_init(&screen->base, dev);
|
||||
if (ret) {
|
||||
nvfx_screen_destroy(pscreen);
|
||||
return NULL;
|
||||
}
|
||||
chan = screen->base.channel;
|
||||
|
||||
pscreen->winsys = ws;
|
||||
pscreen->destroy = nvfx_screen_destroy;
|
||||
pscreen->get_param = nvfx_screen_get_param;
|
||||
pscreen->get_paramf = nvfx_screen_get_paramf;
|
||||
pscreen->is_format_supported = nvfx_screen_surface_format_supported;
|
||||
|
||||
switch (dev->chipset & 0xf0) {
|
||||
case 0x30:
|
||||
if (NV30TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
|
||||
eng3d_class = 0x0397;
|
||||
else if (NV34TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
|
||||
eng3d_class = 0x0697;
|
||||
else if (NV35TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
|
||||
eng3d_class = 0x0497;
|
||||
break;
|
||||
case 0x40:
|
||||
if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
|
||||
eng3d_class = NV40TCL;
|
||||
else if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
|
||||
eng3d_class = NV44TCL;
|
||||
screen->is_nv4x = ~0;
|
||||
break;
|
||||
case 0x60:
|
||||
if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
|
||||
eng3d_class = NV44TCL;
|
||||
screen->is_nv4x = ~0;
|
||||
break;
|
||||
}
|
||||
|
||||
if (!eng3d_class) {
|
||||
NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev->chipset);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
nvfx_screen_init_miptree_functions(pscreen);
|
||||
|
||||
ret = nouveau_grobj_alloc(chan, 0xbeef3097, eng3d_class, &screen->eng3d);
|
||||
if (ret) {
|
||||
NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/* 2D engine setup */
|
||||
screen->eng2d = nv04_surface_2d_init(&screen->base);
|
||||
screen->eng2d->buf = nvfx_surface_buffer;
|
||||
|
||||
/* Notifier for sync purposes */
|
||||
ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
|
||||
if (ret) {
|
||||
NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
|
||||
nvfx_screen_destroy(pscreen);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Query objects */
|
||||
ret = nouveau_notifier_alloc(chan, 0xbeef0302, 32, &screen->query);
|
||||
if (ret) {
|
||||
NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
|
||||
nvfx_screen_destroy(pscreen);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
ret = nouveau_resource_init(&screen->query_heap, 0, 32);
|
||||
if (ret) {
|
||||
NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
|
||||
nvfx_screen_destroy(pscreen);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Vtxprog resources */
|
||||
if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->is_nv4x ? 512 : 256) ||
|
||||
nouveau_resource_init(&screen->vp_data_heap, 0, 256)) {
|
||||
nvfx_screen_destroy(pscreen);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Static eng3d initialisation */
|
||||
/* make the so big and don't worry about exact values
|
||||
since we it will be thrown away immediately after use */
|
||||
so = so_new(256, 256, 0);
|
||||
so_method(so, screen->eng3d, NV34TCL_DMA_NOTIFY, 1);
|
||||
so_data (so, screen->sync->handle);
|
||||
so_method(so, screen->eng3d, NV34TCL_DMA_TEXTURE0, 2);
|
||||
so_data (so, chan->vram->handle);
|
||||
so_data (so, chan->gart->handle);
|
||||
so_method(so, screen->eng3d, NV34TCL_DMA_COLOR1, 1);
|
||||
so_data (so, chan->vram->handle);
|
||||
so_method(so, screen->eng3d, NV34TCL_DMA_COLOR0, 2);
|
||||
so_data (so, chan->vram->handle);
|
||||
so_data (so, chan->vram->handle);
|
||||
so_method(so, screen->eng3d, NV34TCL_DMA_VTXBUF0, 2);
|
||||
so_data (so, chan->vram->handle);
|
||||
so_data (so, chan->gart->handle);
|
||||
|
||||
so_method(so, screen->eng3d, NV34TCL_DMA_FENCE, 2);
|
||||
so_data (so, 0);
|
||||
so_data (so, screen->query->handle);
|
||||
|
||||
so_method(so, screen->eng3d, NV34TCL_DMA_IN_MEMORY7, 2);
|
||||
so_data (so, chan->vram->handle);
|
||||
so_data (so, chan->vram->handle);
|
||||
|
||||
if(!screen->is_nv4x)
|
||||
nv30_screen_init(screen, so);
|
||||
else
|
||||
nv40_screen_init(screen, so);
|
||||
|
||||
so_emit(chan, so);
|
||||
so_ref(NULL, &so);
|
|
@ -86,11 +86,9 @@ nouveau_drm_create_screen(struct drm_api *api, int fd,
|
|||
|
||||
switch (dev->chipset & 0xf0) {
|
||||
case 0x30:
|
||||
init = nv30_screen_create;
|
||||
break;
|
||||
case 0x40:
|
||||
case 0x60:
|
||||
init = nv40_screen_create;
|
||||
init = nvfx_screen_create;
|
||||
break;
|
||||
case 0x50:
|
||||
case 0x80:
|
||||
|
|
Loading…
Reference in New Issue