From 10d08da52c666e5158339da9dfc4e8c411e252ea Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 1 Aug 2019 15:45:11 +0200 Subject: [PATCH] radv/gfx10: add missing dcc_tile_swizzle tweak Fixes: c90f46700dd ("radv/gfx10: mask DCC tile swizzle by alignment") Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_image.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index ce12bb61fb9..aaaf15ec8dc 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -484,7 +484,9 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, if (chip_class <= GFX8) meta_va += base_level_info->dcc_offset; - meta_va |= (uint32_t)plane->surface.tile_swizzle << 8; + unsigned dcc_tile_swizzle = plane->surface.tile_swizzle << 8; + dcc_tile_swizzle &= plane->surface.dcc_alignment - 1; + meta_va |= dcc_tile_swizzle; } else if (!is_storage_image && radv_image_is_tc_compat_htile(image)) { meta_va = gpu_address + image->htile_offset;