vc4: Prefer nir_src_comp_as_uint over nir_src_as_const_value
Signed-off-by: Karol Herbst <kherbst@redhat.com> Reviewed-by: Eric Anholt <eric@anholt.net>
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@ -180,8 +180,7 @@ vc4_nir_lower_vertex_attr(struct vc4_compile *c, nir_builder *b,
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/* We only accept direct outputs and TGSI only ever gives them to us
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* with an offset value of 0.
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*/
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assert(nir_src_as_const_value(intr->src[0]) &&
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nir_src_as_const_value(intr->src[0])->u32[0] == 0);
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assert(nir_src_as_uint(intr->src[0]) == 0);
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/* Generate dword loads for the VPM values (Since these intrinsics may
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* be reordered, the actual reads will be generated at the top of the
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@ -147,9 +147,8 @@ indirect_uniform_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
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static struct qreg
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vc4_ubo_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
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{
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nir_const_value *buffer_index =
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nir_src_as_const_value(intr->src[0]);
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assert(buffer_index->u32[0] == 1);
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unsigned buffer_index = nir_src_as_uint(intr->src[0]);
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assert(buffer_index == 1);
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assert(c->stage == QSTAGE_FRAG);
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struct qreg offset = ntq_get_src(c, intr->src[1], 0);
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@ -161,7 +160,7 @@ vc4_ubo_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
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qir_ADD_dest(c, qir_reg(QFILE_TEX_S_DIRECT, 0),
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offset,
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qir_uniform(c, QUNIFORM_UBO_ADDR, buffer_index->u32[0]));
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qir_uniform(c, QUNIFORM_UBO_ADDR, buffer_index));
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c->num_texture_samples++;
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@ -1758,7 +1757,7 @@ ntq_emit_ssa_undef(struct vc4_compile *c, nir_ssa_undef_instr *instr)
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static void
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ntq_emit_color_read(struct vc4_compile *c, nir_intrinsic_instr *instr)
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{
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assert(nir_src_as_const_value(instr->src[0])->u32[0] == 0);
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assert(nir_src_as_uint(instr->src[0]) == 0);
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/* Reads of the per-sample color need to be done in
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* order.
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@ -1779,9 +1778,8 @@ static void
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ntq_emit_load_input(struct vc4_compile *c, nir_intrinsic_instr *instr)
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{
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assert(instr->num_components == 1);
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nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]);
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assert(const_offset && "vc4 doesn't support indirect inputs");
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assert(nir_src_is_const(instr->src[0]) &&
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"vc4 doesn't support indirect inputs");
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if (c->stage == QSTAGE_FRAG &&
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nir_intrinsic_base(instr) >= VC4_NIR_TLB_COLOR_READ_INPUT) {
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@ -1789,7 +1787,8 @@ ntq_emit_load_input(struct vc4_compile *c, nir_intrinsic_instr *instr)
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return;
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}
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uint32_t offset = nir_intrinsic_base(instr) + const_offset->u32[0];
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uint32_t offset = nir_intrinsic_base(instr) +
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nir_src_as_uint(instr->src[0]);
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int comp = nir_intrinsic_component(instr);
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ntq_store_dest(c, &instr->dest, 0,
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qir_MOV(c, c->inputs[offset * 4 + comp]));
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@ -1798,15 +1797,14 @@ ntq_emit_load_input(struct vc4_compile *c, nir_intrinsic_instr *instr)
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static void
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ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
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{
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nir_const_value *const_offset;
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unsigned offset;
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switch (instr->intrinsic) {
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case nir_intrinsic_load_uniform:
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assert(instr->num_components == 1);
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const_offset = nir_src_as_const_value(instr->src[0]);
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if (const_offset) {
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offset = nir_intrinsic_base(instr) + const_offset->u32[0];
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if (nir_src_is_const(instr->src[0])) {
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offset = nir_intrinsic_base(instr) +
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nir_src_as_uint(instr->src[0]);
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assert(offset % 4 == 0);
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/* We need dwords */
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offset = offset / 4;
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@ -1881,9 +1879,10 @@ ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
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break;
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case nir_intrinsic_store_output:
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const_offset = nir_src_as_const_value(instr->src[1]);
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assert(const_offset && "vc4 doesn't support indirect outputs");
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offset = nir_intrinsic_base(instr) + const_offset->u32[0];
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assert(nir_src_is_const(instr->src[1]) &&
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"vc4 doesn't support indirect outputs");
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offset = nir_intrinsic_base(instr) +
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nir_src_as_uint(instr->src[1]);
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/* MSAA color outputs are the only case where we have an
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* output that's not lowered to being a store of a single 32
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