ac/nir: change es output lower param to esgs_itemsize
radeonsi may add extra dword to the stride, so let's pass it directly. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
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@ -102,7 +102,7 @@ void
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ac_nir_lower_es_outputs_to_mem(nir_shader *shader,
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ac_nir_lower_es_outputs_to_mem(nir_shader *shader,
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ac_nir_map_io_driver_location map,
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ac_nir_map_io_driver_location map,
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enum amd_gfx_level gfx_level,
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enum amd_gfx_level gfx_level,
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unsigned num_reserved_es_outputs);
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unsigned esgs_itemsize);
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void
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void
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ac_nir_lower_gs_inputs_to_mem(nir_shader *shader,
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ac_nir_lower_gs_inputs_to_mem(nir_shader *shader,
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@ -47,10 +47,8 @@ typedef struct {
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/* I/O semantic -> real location used by lowering. */
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/* I/O semantic -> real location used by lowering. */
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ac_nir_map_io_driver_location map_io;
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ac_nir_map_io_driver_location map_io;
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/* Number of ES outputs for which memory should be reserved.
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/* Stride of an ES invocation outputs in esgs ring, in bytes. */
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* When compacted, this should be the number of linked ES outputs.
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unsigned esgs_itemsize;
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*/
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unsigned num_reserved_es_outputs;
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} lower_esgs_io_state;
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} lower_esgs_io_state;
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static nir_ssa_def *
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static nir_ssa_def *
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@ -171,9 +169,8 @@ lower_es_output_store(nir_builder *b,
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write_mask, true, true);
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write_mask, true, true);
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} else {
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} else {
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/* GFX9+: ES is merged into GS, data is passed through LDS. */
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/* GFX9+: ES is merged into GS, data is passed through LDS. */
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unsigned esgs_itemsize = st->num_reserved_es_outputs * 16u;
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nir_ssa_def *vertex_idx = nir_build_load_local_invocation_index(b);
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nir_ssa_def *vertex_idx = nir_build_load_local_invocation_index(b);
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nir_ssa_def *off = nir_iadd(b, nir_imul_imm(b, vertex_idx, esgs_itemsize), io_off);
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nir_ssa_def *off = nir_iadd(b, nir_imul_imm(b, vertex_idx, st->esgs_itemsize), io_off);
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nir_build_store_shared(b, intrin->src[0].ssa, off, .write_mask = write_mask,
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nir_build_store_shared(b, intrin->src[0].ssa, off, .write_mask = write_mask,
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.align_mul = 16u, .align_offset = (nir_intrinsic_component(intrin) * 4u) % 16u);
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.align_mul = 16u, .align_offset = (nir_intrinsic_component(intrin) * 4u) % 16u);
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}
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}
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@ -267,11 +264,11 @@ void
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ac_nir_lower_es_outputs_to_mem(nir_shader *shader,
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ac_nir_lower_es_outputs_to_mem(nir_shader *shader,
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ac_nir_map_io_driver_location map,
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ac_nir_map_io_driver_location map,
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enum amd_gfx_level gfx_level,
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enum amd_gfx_level gfx_level,
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unsigned num_reserved_es_outputs)
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unsigned esgs_itemsize)
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{
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{
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lower_esgs_io_state state = {
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lower_esgs_io_state state = {
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.gfx_level = gfx_level,
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.gfx_level = gfx_level,
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.num_reserved_es_outputs = num_reserved_es_outputs,
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.esgs_itemsize = esgs_itemsize,
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.map_io = map,
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.map_io = map,
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};
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};
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@ -1115,7 +1115,8 @@ radv_lower_io_to_mem(struct radv_device *device, struct radv_pipeline_stage *sta
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return true;
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return true;
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} else if (info->vs.as_es) {
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} else if (info->vs.as_es) {
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NIR_PASS_V(nir, ac_nir_lower_es_outputs_to_mem, NULL,
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NIR_PASS_V(nir, ac_nir_lower_es_outputs_to_mem, NULL,
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device->physical_device->rad_info.gfx_level, info->vs.num_linked_outputs);
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device->physical_device->rad_info.gfx_level,
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info->vs.num_linked_outputs * 16u);
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return true;
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return true;
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}
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}
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} else if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
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} else if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
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@ -1133,7 +1134,8 @@ radv_lower_io_to_mem(struct radv_device *device, struct radv_pipeline_stage *sta
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if (info->tes.as_es) {
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if (info->tes.as_es) {
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NIR_PASS_V(nir, ac_nir_lower_es_outputs_to_mem, NULL,
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NIR_PASS_V(nir, ac_nir_lower_es_outputs_to_mem, NULL,
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device->physical_device->rad_info.gfx_level, info->tes.num_linked_outputs);
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device->physical_device->rad_info.gfx_level,
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info->tes.num_linked_outputs * 16u);
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}
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}
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return true;
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return true;
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