radeonsi: unify si_set_optimal_micro_tile_mode call sites
There is nothing special happening in those code blocks. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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@ -2503,10 +2503,6 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
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if (rctx->screen->debug_flags & DBG_NO_DCC_CLEAR)
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if (rctx->screen->debug_flags & DBG_NO_DCC_CLEAR)
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continue;
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continue;
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/* We can change the micro tile mode before a full clear. */
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if (rctx->screen->chip_class >= SI)
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si_set_optimal_micro_tile_mode(rctx->screen, tex);
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if (!vi_get_fast_clear_parameters(fb->cbufs[i]->format,
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if (!vi_get_fast_clear_parameters(fb->cbufs[i]->format,
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color, &reset_value,
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color, &reset_value,
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&clear_words_needed))
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&clear_words_needed))
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@ -2533,10 +2529,6 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
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continue;
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continue;
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}
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}
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/* We can change the micro tile mode before a full clear. */
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if (rctx->screen->chip_class >= SI)
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si_set_optimal_micro_tile_mode(rctx->screen, tex);
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/* Do the fast clear. */
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/* Do the fast clear. */
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rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
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rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
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tex->cmask.offset, tex->cmask.size, 0,
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tex->cmask.offset, tex->cmask.size, 0,
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@ -2545,6 +2537,10 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
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tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
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tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
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}
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}
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/* We can change the micro tile mode before a full clear. */
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if (rctx->screen->chip_class >= SI)
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si_set_optimal_micro_tile_mode(rctx->screen, tex);
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evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
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evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
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if (dirty_cbufs)
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if (dirty_cbufs)
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