r600: remove (now) dead code
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fbe06a9c29
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0f854105f5
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@ -2477,260 +2477,7 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm)
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return GL_TRUE;
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}
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#if 0
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GLboolean assemble_alu_instruction_literal(r700_AssemblerBase *pAsm, GLfloat * pLiteral)
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{
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R700ALUInstruction * alu_instruction_ptr;
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R700ALUInstructionHalfLiteral * alu_instruction_ptr_hl;
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R700ALUInstructionFullLiteral * alu_instruction_ptr_fl;
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GLuint number_of_scalar_operations;
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GLboolean is_single_scalar_operation;
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GLuint scalar_channel_index;
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GLuint contiguous_slots_needed;
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GLuint lastInstruction;
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GLuint not_masked[4];
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GLuint uNumSrc = r700GetNumOperands(pAsm);
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GLboolean bSplitInst = GL_FALSE;
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number_of_scalar_operations = 0;
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contiguous_slots_needed = 0;
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if(1 == pAsm->D.dst.writew)
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{
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lastInstruction = 3;
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number_of_scalar_operations++;
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not_masked[3] = 1;
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}
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else
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{
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not_masked[3] = 0;
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}
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if(1 == pAsm->D.dst.writez)
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{
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lastInstruction = 2;
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number_of_scalar_operations++;
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not_masked[2] = 1;
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}
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else
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{
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not_masked[2] = 0;
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}
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if(1 == pAsm->D.dst.writey)
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{
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lastInstruction = 1;
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number_of_scalar_operations++;
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not_masked[1] = 1;
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}
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else
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{
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not_masked[1] = 0;
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}
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if(1 == pAsm->D.dst.writex)
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{
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lastInstruction = 0;
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number_of_scalar_operations++;
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not_masked[0] = 1;
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}
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else
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{
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not_masked[0] = 0;
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}
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if(GL_TRUE == is_reduction_opcode(&(pAsm->D)) )
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{
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contiguous_slots_needed = 4;
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}
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else
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{
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contiguous_slots_needed = number_of_scalar_operations;
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}
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if(1 == pAsm->D2.dst2.literal)
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{
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contiguous_slots_needed += 1;
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}
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else if(2 == pAsm->D2.dst2.literal)
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{
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contiguous_slots_needed += 2;
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}
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initialize(pAsm);
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for (scalar_channel_index=0; scalar_channel_index < 4; scalar_channel_index++)
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{
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if(0 == not_masked[scalar_channel_index])
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{
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continue;
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}
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if(scalar_channel_index == lastInstruction)
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{
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switch (pAsm->D2.dst2.literal)
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{
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case 0:
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alu_instruction_ptr = (R700ALUInstruction*) CALLOC_STRUCT(R700ALUInstruction);
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if (alu_instruction_ptr == NULL)
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{
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return GL_FALSE;
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}
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Init_R700ALUInstruction(alu_instruction_ptr);
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break;
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case 1:
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alu_instruction_ptr_hl = (R700ALUInstructionHalfLiteral*) CALLOC_STRUCT(R700ALUInstructionHalfLiteral);
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if (alu_instruction_ptr_hl == NULL)
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{
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return GL_FALSE;
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}
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Init_R700ALUInstructionHalfLiteral(alu_instruction_ptr_hl, pLiteral[0], pLiteral[1]);
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alu_instruction_ptr = (R700ALUInstruction*)alu_instruction_ptr_hl;
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break;
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case 2:
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alu_instruction_ptr_fl = (R700ALUInstructionFullLiteral*) CALLOC_STRUCT(R700ALUInstructionFullLiteral);
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if (alu_instruction_ptr_fl == NULL)
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{
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return GL_FALSE;
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}
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Init_R700ALUInstructionFullLiteral(alu_instruction_ptr_fl, pLiteral[0], pLiteral[1], pLiteral[2], pLiteral[3]);
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alu_instruction_ptr = (R700ALUInstruction*)alu_instruction_ptr_fl;
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break;
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default:
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break;
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};
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}
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else
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{
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alu_instruction_ptr = (R700ALUInstruction*) CALLOC_STRUCT(R700ALUInstruction);
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if (alu_instruction_ptr == NULL)
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{
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return GL_FALSE;
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}
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Init_R700ALUInstruction(alu_instruction_ptr);
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}
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//src 0
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if (GL_FALSE == assemble_alu_src(alu_instruction_ptr,
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0,
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&(pAsm->S[0].src),
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scalar_channel_index) )
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{
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return GL_FALSE;
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}
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if (uNumSrc > 1)
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{
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// Process source 1
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if (GL_FALSE == assemble_alu_src(alu_instruction_ptr,
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1,
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&(pAsm->S[1].src),
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scalar_channel_index) )
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{
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return GL_FALSE;
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}
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}
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//other bits
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alu_instruction_ptr->m_Word0.f.index_mode = SQ_INDEX_LOOP;
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if(scalar_channel_index == lastInstruction)
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{
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alu_instruction_ptr->m_Word0.f.last = 1;
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}
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alu_instruction_ptr->m_Word0.f.pred_sel = 0x0;
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if(1 == pAsm->D.dst.predicated)
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{
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alu_instruction_ptr->m_Word1_OP2.f.update_pred = 0x1;
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alu_instruction_ptr->m_Word1_OP2.f.update_execute_mask = 0x1;
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}
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else
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{
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alu_instruction_ptr->m_Word1_OP2.f.update_pred = 0;
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alu_instruction_ptr->m_Word1_OP2.f.update_execute_mask = 0;
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}
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// dst
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if( (pAsm->D.dst.rtype == DST_REG_TEMPORARY) ||
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(pAsm->D.dst.rtype == DST_REG_OUT) )
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{
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alu_instruction_ptr->m_Word1.f.dst_gpr = pAsm->D.dst.reg;
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}
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else
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{
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radeon_error("Only temp destination registers supported for ALU dest regs.\n");
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return GL_FALSE;
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}
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alu_instruction_ptr->m_Word1.f.dst_rel = SQ_ABSOLUTE; //D.rtype
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alu_instruction_ptr->m_Word1.f.dst_chan = scalar_channel_index;
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alu_instruction_ptr->m_Word1.f.clamp = pAsm->D2.dst2.SaturateMode;
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if (pAsm->D.dst.op3)
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{
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//op3
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alu_instruction_ptr->m_Word1_OP3.f.alu_inst = pAsm->D.dst.opcode;
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//There's 3rd src for op3
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if ( GL_FALSE == assemble_alu_src(alu_instruction_ptr,
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2,
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&(pAsm->S[2].src),
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scalar_channel_index) )
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{
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return GL_FALSE;
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}
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}
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else
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{
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//op2
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if (pAsm->bR6xx)
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{
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alu_instruction_ptr->m_Word1_OP2.f6.alu_inst = pAsm->D.dst.opcode;
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alu_instruction_ptr->m_Word1_OP2.f6.src0_abs = 0x0;
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alu_instruction_ptr->m_Word1_OP2.f6.src1_abs = 0x0;
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alu_instruction_ptr->m_Word1_OP2.f6.write_mask = 1;
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alu_instruction_ptr->m_Word1_OP2.f6.omod = SQ_ALU_OMOD_OFF;
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}
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else
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{
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alu_instruction_ptr->m_Word1_OP2.f.alu_inst = pAsm->D.dst.opcode;
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alu_instruction_ptr->m_Word1_OP2.f.src0_abs = 0x0;
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alu_instruction_ptr->m_Word1_OP2.f.src1_abs = 0x0;
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alu_instruction_ptr->m_Word1_OP2.f.write_mask = 1;
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alu_instruction_ptr->m_Word1_OP2.f.omod = SQ_ALU_OMOD_OFF;
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}
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}
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if(GL_FALSE == add_alu_instruction(pAsm, alu_instruction_ptr, contiguous_slots_needed) )
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{
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return GL_FALSE;
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}
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if (1 == number_of_scalar_operations)
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{
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if(GL_FALSE == check_scalar(pAsm, alu_instruction_ptr) )
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{
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return GL_FALSE;
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}
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}
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else
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{
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if(GL_FALSE == check_vector(pAsm, alu_instruction_ptr) )
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{
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return GL_FALSE;
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}
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}
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contiguous_slots_needed -= 2;
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}
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return GL_TRUE;
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}
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#endif
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GLboolean next_ins(r700_AssemblerBase *pAsm)
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{
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struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]);
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@ -2787,29 +2534,6 @@ GLboolean next_ins(r700_AssemblerBase *pAsm)
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return GL_TRUE;
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}
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#if 0/* not work yet */
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GLboolean next_ins_literal(r700_AssemblerBase *pAsm, GLfloat * pLiteral)
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{
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struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]);
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//ALU
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if( GL_FALSE == assemble_alu_instruction_literal(pAsm, pLiteral) )
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{
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radeon_error("Error assembling ALU instruction\n");
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return GL_FALSE;
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}
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//reset for next inst.
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pAsm->D.bits = 0;
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pAsm->D2.bits = 0;
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pAsm->S[0].bits = 0;
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pAsm->S[1].bits = 0;
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pAsm->S[2].bits = 0;
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pAsm->is_tex = GL_FALSE;
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pAsm->need_tex_barrier = GL_FALSE;
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return GL_TRUE;
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}
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#endif
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GLboolean assemble_math_function(r700_AssemblerBase* pAsm, BITS opcode)
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{
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BITS tmp;
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@ -4533,8 +4257,6 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm)
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setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
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pAsm->D.dst.rtype = DST_REG_TEMPORARY;
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pAsm->D.dst.reg = tmp2;
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pAsm->D2.dst2.literal_slots = 1;
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pAsm->C[0].f = 1.5F;
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setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
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pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
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@ -4546,33 +4268,14 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm)
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setswizzle_PVSSRC(&(pAsm->S[1].src), SQ_SEL_Z);
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setaddrmode_PVSSRC(&(pAsm->S[2].src), ADDR_ABSOLUTE);
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/* immediate c 1.5 */
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pAsm->D2.dst2.literal_slots = 1;
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pAsm->C[0].f = 1.5F;
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pAsm->S[2].src.rtype = SRC_REC_LITERAL;
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pAsm->S[2].src.reg = tmp1;
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setswizzle_PVSSRC(&(pAsm->S[2].src), SQ_SEL_X);
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next_ins(pAsm);
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#if 0
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/* ADD the remaining .5 */
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pAsm->D.dst.opcode = SQ_OP2_INST_ADD;
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setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
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pAsm->D.dst.rtype = DST_REG_TEMPORARY;
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pAsm->D.dst.reg = tmp2;
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pAsm->D.dst.writex = 1;
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pAsm->D.dst.writey = 1;
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pAsm->D.dst.writez = 0;
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pAsm->D.dst.writew = 0;
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setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
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pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
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pAsm->S[0].src.reg = tmp2;
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noswizzle_PVSSRC(&(pAsm->S[0].src));
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setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE);
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pAsm->S[1].src.rtype = SRC_REG_TEMPORARY;
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pAsm->S[1].src.reg = 252; // SQ_ALU_SRC_0_5
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noswizzle_PVSSRC(&(pAsm->S[1].src));
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next_ins(pAsm);
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#endif
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/* tmp1.xy = temp2.xy */
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pAsm->D.dst.opcode = SQ_OP2_INST_MOV;
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setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
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@ -531,10 +531,6 @@ GLboolean check_vector(r700_AssemblerBase* pAsm,
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GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm);
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GLboolean next_ins(r700_AssemblerBase *pAsm);
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/* TODO : merge next_ins/literal, assemble_alu_instruction/literal */
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GLboolean next_ins_literal(r700_AssemblerBase *pAsm, GLfloat * pLiteral);
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GLboolean assemble_alu_instruction_literal(r700_AssemblerBase *pAsm, GLfloat * pLiteral);
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GLboolean pops(r700_AssemblerBase *pAsm, GLuint pops);
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GLboolean jumpToOffest(r700_AssemblerBase *pAsm, GLuint pops, GLint offset);
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GLboolean setRetInLoopFlag(r700_AssemblerBase *pAsm, GLuint flagValue);
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