freedreno/ir3: debug cleanup
1) deduplicate IR3_SHADER_DEBUG=disasm versus fs/vs/etc handling 2) standardize shader stage name prints, in particular VERT vs BVERT 3) don't mix stderr and stdout Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
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@ -99,6 +99,9 @@ extern enum ir3_shader_debug ir3_shader_debug;
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static inline bool
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shader_debug_enabled(gl_shader_stage type)
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{
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if (ir3_shader_debug & IR3_DBG_DISASM)
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return true;
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switch (type) {
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case MESA_SHADER_VERTEX: return !!(ir3_shader_debug & IR3_DBG_SHADER_VS);
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case MESA_SHADER_TESS_CTRL: return !!(ir3_shader_debug & IR3_DBG_SHADER_TCS);
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@ -104,17 +104,10 @@ ir3_context_init(struct ir3_compiler *compiler,
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NIR_PASS_V(ctx->s, nir_convert_from_ssa, true);
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if (ir3_shader_debug & IR3_DBG_DISASM) {
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DBG("dump nir%dv%d: type=%d, k={cts=%u,hp=%u}",
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so->shader->id, so->id, so->type,
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so->key.color_two_side, so->key.half_precision);
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nir_print_shader(ctx->s, stdout);
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}
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if (shader_debug_enabled(so->type)) {
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fprintf(stderr, "NIR (final form) for %s shader:\n",
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_mesa_shader_stage_to_string(so->type));
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nir_print_shader(ctx->s, stderr);
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fprintf(stdout, "NIR (final form) for %s shader %s:\n",
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ir3_shader_stage(so), so->shader->nir->info.name);
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nir_print_shader(ctx->s, stdout);
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}
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ir3_ibo_mapping_init(&so->image_mapping, ctx->s->info.num_textures);
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@ -165,24 +165,16 @@ assemble_variant(struct ir3_shader_variant *v)
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v->bo = fd_bo_new(compiler->dev, sz,
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DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
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DRM_FREEDRENO_GEM_TYPE_KMEM,
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"%s:%s", ir3_shader_stage(v->shader), info->name);
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"%s:%s", ir3_shader_stage(v), info->name);
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memcpy(fd_bo_map(v->bo), bin, sz);
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if (ir3_shader_debug & IR3_DBG_DISASM) {
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struct ir3_shader_key key = v->key;
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printf("disassemble: type=%d, k={bp=%u,cts=%u,hp=%u}\n", v->type,
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v->binning_pass, key.color_two_side, key.half_precision);
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ir3_shader_disasm(v, bin, stdout);
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}
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if (shader_debug_enabled(v->shader->type)) {
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fprintf(stderr, "Native code for unnamed %s shader %s:\n",
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_mesa_shader_stage_to_string(v->shader->type),
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v->shader->nir->info.name);
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fprintf(stdout, "Native code for unnamed %s shader %s:\n",
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ir3_shader_stage(v), v->shader->nir->info.name);
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if (v->shader->type == MESA_SHADER_FRAGMENT)
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fprintf(stderr, "SIMD0\n");
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ir3_shader_disasm(v, bin, stderr);
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fprintf(stdout, "SIMD0\n");
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ir3_shader_disasm(v, bin, stdout);
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}
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free(bin);
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@ -382,7 +374,7 @@ ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out)
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{
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struct ir3 *ir = so->ir;
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struct ir3_register *reg;
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const char *type = ir3_shader_stage(so->shader);
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const char *type = ir3_shader_stage(so);
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uint8_t regid;
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unsigned i;
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@ -559,13 +559,28 @@ struct ir3_shader_variant {
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struct ir3_sampler_prefetch sampler_prefetch[IR3_MAX_SAMPLER_PREFETCH];
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};
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static inline const char *
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ir3_shader_stage(struct ir3_shader_variant *v)
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{
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switch (v->type) {
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case MESA_SHADER_VERTEX: return v->binning_pass ? "BVERT" : "VERT";
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case MESA_SHADER_TESS_CTRL: return "TCS";
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case MESA_SHADER_TESS_EVAL: return "TES";
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case MESA_SHADER_GEOMETRY: return "GEOM";
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case MESA_SHADER_FRAGMENT: return "FRAG";
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case MESA_SHADER_COMPUTE: return "CL";
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default:
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unreachable("invalid type");
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return NULL;
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}
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}
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struct ir3_ubo_range {
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uint32_t offset; /* start offset of this block in const register file */
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uint32_t start, end; /* range of block that's actually used */
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};
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struct ir3_ubo_analysis_state
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{
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struct ir3_ubo_analysis_state {
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struct ir3_ubo_range range[IR3_MAX_CONSTANT_BUFFERS];
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uint32_t size;
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uint32_t lower_count;
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@ -611,22 +626,6 @@ uint64_t ir3_shader_outputs(const struct ir3_shader *so);
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int
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ir3_glsl_type_size(const struct glsl_type *type, bool bindless);
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static inline const char *
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ir3_shader_stage(struct ir3_shader *shader)
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{
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switch (shader->type) {
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case MESA_SHADER_VERTEX: return "VERT";
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case MESA_SHADER_TESS_CTRL: return "TCS";
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case MESA_SHADER_TESS_EVAL: return "TES";
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case MESA_SHADER_GEOMETRY: return "GEOM";
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case MESA_SHADER_FRAGMENT: return "FRAG";
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case MESA_SHADER_COMPUTE: return "CL";
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default:
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unreachable("invalid type");
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return NULL;
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}
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}
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/*
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* Helper/util:
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*/
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@ -57,7 +57,7 @@
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static void dump_info(struct ir3_shader_variant *so, const char *str)
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{
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uint32_t *bin;
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const char *type = ir3_shader_stage(so->shader);
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const char *type = ir3_shader_stage(so);
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bin = ir3_shader_assemble(so, so->shader->compiler->gpu_id);
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debug_printf("; %s: %s\n", type, str);
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ir3_shader_disasm(so, bin, stdout);
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@ -51,11 +51,10 @@ dump_shader_info(struct ir3_shader_variant *v, bool binning_pass,
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return;
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pipe_debug_message(debug, SHADER_INFO,
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"%s%s shader: %u inst, %u dwords, "
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"%s shader: %u inst, %u dwords, "
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"%u half, %u full, %u constlen, "
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"%u (ss), %u (sy), %d max_sun, %d loops\n",
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binning_pass ? "B" : "",
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ir3_shader_stage(v->shader),
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ir3_shader_stage(v),
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v->info.instrs_count,
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v->info.sizedwords,
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v->info.max_half_reg + 1,
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