freedreno/ir3: debug cleanup

1) deduplicate IR3_SHADER_DEBUG=disasm versus fs/vs/etc handling
2) standardize shader stage name prints, in particular VERT vs BVERT
3) don't mix stderr and stdout

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
This commit is contained in:
Rob Clark 2019-10-14 10:42:25 -07:00
parent d31f415ba0
commit 0f395f0933
6 changed files with 32 additions and 46 deletions

View File

@ -99,6 +99,9 @@ extern enum ir3_shader_debug ir3_shader_debug;
static inline bool
shader_debug_enabled(gl_shader_stage type)
{
if (ir3_shader_debug & IR3_DBG_DISASM)
return true;
switch (type) {
case MESA_SHADER_VERTEX: return !!(ir3_shader_debug & IR3_DBG_SHADER_VS);
case MESA_SHADER_TESS_CTRL: return !!(ir3_shader_debug & IR3_DBG_SHADER_TCS);

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@ -104,17 +104,10 @@ ir3_context_init(struct ir3_compiler *compiler,
NIR_PASS_V(ctx->s, nir_convert_from_ssa, true);
if (ir3_shader_debug & IR3_DBG_DISASM) {
DBG("dump nir%dv%d: type=%d, k={cts=%u,hp=%u}",
so->shader->id, so->id, so->type,
so->key.color_two_side, so->key.half_precision);
nir_print_shader(ctx->s, stdout);
}
if (shader_debug_enabled(so->type)) {
fprintf(stderr, "NIR (final form) for %s shader:\n",
_mesa_shader_stage_to_string(so->type));
nir_print_shader(ctx->s, stderr);
fprintf(stdout, "NIR (final form) for %s shader %s:\n",
ir3_shader_stage(so), so->shader->nir->info.name);
nir_print_shader(ctx->s, stdout);
}
ir3_ibo_mapping_init(&so->image_mapping, ctx->s->info.num_textures);

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@ -165,24 +165,16 @@ assemble_variant(struct ir3_shader_variant *v)
v->bo = fd_bo_new(compiler->dev, sz,
DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
DRM_FREEDRENO_GEM_TYPE_KMEM,
"%s:%s", ir3_shader_stage(v->shader), info->name);
"%s:%s", ir3_shader_stage(v), info->name);
memcpy(fd_bo_map(v->bo), bin, sz);
if (ir3_shader_debug & IR3_DBG_DISASM) {
struct ir3_shader_key key = v->key;
printf("disassemble: type=%d, k={bp=%u,cts=%u,hp=%u}\n", v->type,
v->binning_pass, key.color_two_side, key.half_precision);
ir3_shader_disasm(v, bin, stdout);
}
if (shader_debug_enabled(v->shader->type)) {
fprintf(stderr, "Native code for unnamed %s shader %s:\n",
_mesa_shader_stage_to_string(v->shader->type),
v->shader->nir->info.name);
fprintf(stdout, "Native code for unnamed %s shader %s:\n",
ir3_shader_stage(v), v->shader->nir->info.name);
if (v->shader->type == MESA_SHADER_FRAGMENT)
fprintf(stderr, "SIMD0\n");
ir3_shader_disasm(v, bin, stderr);
fprintf(stdout, "SIMD0\n");
ir3_shader_disasm(v, bin, stdout);
}
free(bin);
@ -382,7 +374,7 @@ ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out)
{
struct ir3 *ir = so->ir;
struct ir3_register *reg;
const char *type = ir3_shader_stage(so->shader);
const char *type = ir3_shader_stage(so);
uint8_t regid;
unsigned i;

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@ -559,13 +559,28 @@ struct ir3_shader_variant {
struct ir3_sampler_prefetch sampler_prefetch[IR3_MAX_SAMPLER_PREFETCH];
};
static inline const char *
ir3_shader_stage(struct ir3_shader_variant *v)
{
switch (v->type) {
case MESA_SHADER_VERTEX: return v->binning_pass ? "BVERT" : "VERT";
case MESA_SHADER_TESS_CTRL: return "TCS";
case MESA_SHADER_TESS_EVAL: return "TES";
case MESA_SHADER_GEOMETRY: return "GEOM";
case MESA_SHADER_FRAGMENT: return "FRAG";
case MESA_SHADER_COMPUTE: return "CL";
default:
unreachable("invalid type");
return NULL;
}
}
struct ir3_ubo_range {
uint32_t offset; /* start offset of this block in const register file */
uint32_t start, end; /* range of block that's actually used */
};
struct ir3_ubo_analysis_state
{
struct ir3_ubo_analysis_state {
struct ir3_ubo_range range[IR3_MAX_CONSTANT_BUFFERS];
uint32_t size;
uint32_t lower_count;
@ -611,22 +626,6 @@ uint64_t ir3_shader_outputs(const struct ir3_shader *so);
int
ir3_glsl_type_size(const struct glsl_type *type, bool bindless);
static inline const char *
ir3_shader_stage(struct ir3_shader *shader)
{
switch (shader->type) {
case MESA_SHADER_VERTEX: return "VERT";
case MESA_SHADER_TESS_CTRL: return "TCS";
case MESA_SHADER_TESS_EVAL: return "TES";
case MESA_SHADER_GEOMETRY: return "GEOM";
case MESA_SHADER_FRAGMENT: return "FRAG";
case MESA_SHADER_COMPUTE: return "CL";
default:
unreachable("invalid type");
return NULL;
}
}
/*
* Helper/util:
*/

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@ -57,7 +57,7 @@
static void dump_info(struct ir3_shader_variant *so, const char *str)
{
uint32_t *bin;
const char *type = ir3_shader_stage(so->shader);
const char *type = ir3_shader_stage(so);
bin = ir3_shader_assemble(so, so->shader->compiler->gpu_id);
debug_printf("; %s: %s\n", type, str);
ir3_shader_disasm(so, bin, stdout);

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@ -51,11 +51,10 @@ dump_shader_info(struct ir3_shader_variant *v, bool binning_pass,
return;
pipe_debug_message(debug, SHADER_INFO,
"%s%s shader: %u inst, %u dwords, "
"%s shader: %u inst, %u dwords, "
"%u half, %u full, %u constlen, "
"%u (ss), %u (sy), %d max_sun, %d loops\n",
binning_pass ? "B" : "",
ir3_shader_stage(v->shader),
ir3_shader_stage(v),
v->info.instrs_count,
v->info.sizedwords,
v->info.max_half_reg + 1,