radeonsi: remove old_va parameter from si_rebind_buffer by remembering offsets
This is a prerequisite for the next commit. Cc: 19.1 <mesa-stable@lists.freedesktop.org>
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f3ae455eb0
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0f1b070bad
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@ -287,11 +287,9 @@ si_invalidate_buffer(struct si_context *sctx,
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/* Check if mapping this buffer would cause waiting for the GPU. */
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if (si_rings_is_buffer_referenced(sctx, buf->buf, RADEON_USAGE_READWRITE) ||
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!sctx->ws->buffer_wait(buf->buf, 0, RADEON_USAGE_READWRITE)) {
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uint64_t old_va = buf->gpu_address;
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/* Reallocate the buffer in the same pipe_resource. */
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si_alloc_resource(sctx->screen, buf);
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si_rebind_buffer(sctx, &buf->b.b, old_va);
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si_rebind_buffer(sctx, &buf->b.b);
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} else {
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util_range_set_empty(&buf->valid_buffer_range);
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}
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@ -307,7 +305,6 @@ void si_replace_buffer_storage(struct pipe_context *ctx,
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struct si_context *sctx = (struct si_context*)ctx;
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struct si_resource *sdst = si_resource(dst);
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struct si_resource *ssrc = si_resource(src);
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uint64_t old_gpu_address = sdst->gpu_address;
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pb_reference(&sdst->buf, ssrc->buf);
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sdst->gpu_address = ssrc->gpu_address;
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@ -322,7 +319,7 @@ void si_replace_buffer_storage(struct pipe_context *ctx,
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assert(sdst->bo_alignment == ssrc->bo_alignment);
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assert(sdst->domains == ssrc->domains);
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si_rebind_buffer(sctx, dst, old_gpu_address);
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si_rebind_buffer(sctx, dst);
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}
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static void si_invalidate_resource(struct pipe_context *ctx,
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@ -992,6 +992,7 @@ static void si_init_buffer_resources(struct si_buffer_resources *buffers,
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buffers->priority = priority;
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buffers->priority_constbuf = priority_constbuf;
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buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource*));
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buffers->offsets = CALLOC(num_buffers, sizeof(buffers->offsets[0]));
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si_init_descriptors(descs, shader_userdata_rel_index, 4, num_buffers);
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}
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@ -1006,6 +1007,7 @@ static void si_release_buffer_resources(struct si_buffer_resources *buffers,
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}
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FREE(buffers->buffers);
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FREE(buffers->offsets);
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}
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static void si_buffer_resources_begin_new_cs(struct si_context *sctx,
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@ -1205,11 +1207,10 @@ static void si_set_constant_buffer(struct si_context *sctx,
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if (input && (input->buffer || input->user_buffer)) {
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struct pipe_resource *buffer = NULL;
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uint64_t va;
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unsigned buffer_offset;
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/* Upload the user buffer if needed. */
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if (input->user_buffer) {
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unsigned buffer_offset;
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si_upload_const_buffer(sctx,
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(struct si_resource**)&buffer, input->user_buffer,
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input->buffer_size, &buffer_offset);
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@ -1218,12 +1219,13 @@ static void si_set_constant_buffer(struct si_context *sctx,
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si_set_constant_buffer(sctx, buffers, descriptors_idx, slot, NULL);
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return;
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}
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va = si_resource(buffer)->gpu_address + buffer_offset;
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} else {
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pipe_resource_reference(&buffer, input->buffer);
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va = si_resource(buffer)->gpu_address + input->buffer_offset;
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buffer_offset = input->buffer_offset;
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}
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va = si_resource(buffer)->gpu_address + buffer_offset;
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/* Set the descriptor. */
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uint32_t *desc = descs->list + slot*4;
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desc[0] = va;
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@ -1238,6 +1240,7 @@ static void si_set_constant_buffer(struct si_context *sctx,
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S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
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buffers->buffers[slot] = buffer;
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buffers->offsets[slot] = buffer_offset;
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radeon_add_to_gfx_buffer_list_check_mem(sctx,
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si_resource(buffer),
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RADEON_USAGE_READ,
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@ -1322,6 +1325,7 @@ static void si_set_shader_buffer(struct si_context *sctx,
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S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
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pipe_resource_reference(&buffers->buffers[slot], &buf->b.b);
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buffers->offsets[slot] = sbuffer->buffer_offset;
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radeon_add_to_gfx_buffer_list_check_mem(sctx, buf,
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writable ? RADEON_USAGE_READWRITE :
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RADEON_USAGE_READ,
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@ -1491,20 +1495,6 @@ void si_set_ring_buffer(struct si_context *sctx, uint slot,
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sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
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}
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static void si_desc_reset_buffer_offset(uint32_t *desc, uint64_t old_buf_va,
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struct pipe_resource *new_buf)
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{
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/* Retrieve the buffer offset from the descriptor. */
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uint64_t old_desc_va = si_desc_extract_buffer_address(desc);
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assert(old_buf_va <= old_desc_va);
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uint64_t offset_within_buffer = old_desc_va - old_buf_va;
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/* Update the descriptor. */
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si_set_buf_desc_address(si_resource(new_buf), offset_within_buffer,
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desc);
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}
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/* INTERNAL CONST BUFFERS */
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static void si_set_polygon_stipple(struct pipe_context *ctx,
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@ -1589,7 +1579,6 @@ static void si_reset_buffer_resources(struct si_context *sctx,
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unsigned descriptors_idx,
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unsigned slot_mask,
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struct pipe_resource *buf,
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uint64_t old_va,
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enum radeon_bo_priority priority)
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{
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struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
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@ -1598,8 +1587,8 @@ static void si_reset_buffer_resources(struct si_context *sctx,
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while (mask) {
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unsigned i = u_bit_scan(&mask);
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if (buffers->buffers[i] == buf) {
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si_desc_reset_buffer_offset(descs->list + i*4,
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old_va, buf);
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si_set_buf_desc_address(si_resource(buf), buffers->offsets[i],
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descs->list + i*4);
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sctx->descriptors_dirty |= 1u << descriptors_idx;
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radeon_add_to_gfx_buffer_list_check_mem(sctx,
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@ -1615,8 +1604,7 @@ static void si_reset_buffer_resources(struct si_context *sctx,
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/* Update all resource bindings where the buffer is bound, including
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* all resource descriptors. This is invalidate_buffer without
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* the invalidation. */
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void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf,
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uint64_t old_va)
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void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
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{
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struct si_resource *buffer = si_resource(buf);
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unsigned i, shader;
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@ -1656,8 +1644,8 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf,
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if (buffers->buffers[i] != buf)
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continue;
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si_desc_reset_buffer_offset(descs->list + i*4,
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old_va, buf);
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si_set_buf_desc_address(si_resource(buf), buffers->offsets[i],
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descs->list + i*4);
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sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
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radeon_add_to_gfx_buffer_list_check_mem(sctx,
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@ -1680,7 +1668,7 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf,
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si_reset_buffer_resources(sctx, &sctx->const_and_shader_buffers[shader],
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si_const_and_shader_buffer_descriptors_idx(shader),
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u_bit_consecutive(SI_NUM_SHADER_BUFFERS, SI_NUM_CONST_BUFFERS),
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buf, old_va,
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buf,
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sctx->const_and_shader_buffers[shader].priority_constbuf);
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}
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@ -1689,7 +1677,7 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf,
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si_reset_buffer_resources(sctx, &sctx->const_and_shader_buffers[shader],
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si_const_and_shader_buffer_descriptors_idx(shader),
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u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS),
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buf, old_va,
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buf,
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sctx->const_and_shader_buffers[shader].priority);
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}
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@ -1706,9 +1694,9 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf,
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if (samplers->views[i]->texture == buf) {
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unsigned desc_slot = si_get_sampler_slot(i);
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si_desc_reset_buffer_offset(descs->list +
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desc_slot * 16 + 4,
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old_va, buf);
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si_set_buf_desc_address(si_resource(buf),
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samplers->views[i]->u.buf.offset,
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descs->list + desc_slot * 16 + 4);
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sctx->descriptors_dirty |=
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1u << si_sampler_and_image_descriptors_idx(shader);
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@ -1738,9 +1726,9 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf,
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if (images->views[i].access & PIPE_IMAGE_ACCESS_WRITE)
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si_mark_image_range_valid(&images->views[i]);
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si_desc_reset_buffer_offset(
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descs->list + desc_slot * 8 + 4,
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old_va, buf);
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si_set_buf_desc_address(si_resource(buf),
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images->views[i].u.buf.offset,
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descs->list + desc_slot * 8 + 4);
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sctx->descriptors_dirty |=
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1u << si_sampler_and_image_descriptors_idx(shader);
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@ -447,6 +447,7 @@ struct si_descriptors {
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struct si_buffer_resources {
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struct pipe_resource **buffers; /* this has num_buffers elements */
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unsigned *offsets; /* this has num_buffers elements */
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enum radeon_bo_priority priority:6;
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enum radeon_bo_priority priority_constbuf:6;
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@ -525,8 +526,7 @@ struct pb_slab *si_bindless_descriptor_slab_alloc(void *priv, unsigned heap,
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unsigned entry_size,
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unsigned group_index);
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void si_bindless_descriptor_slab_free(void *priv, struct pb_slab *pslab);
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void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf,
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uint64_t old_va);
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void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf);
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/* si_state.c */
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void si_init_state_compute_functions(struct si_context *sctx);
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void si_init_state_functions(struct si_context *sctx);
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