pan/mdg: remove ins->alu
This commit removes the `ins->alu` field from midgard_instruction, simplifying the code by just recreating midgard_vector_alu later when we have to emit it. Signed-off-by: Italo Nicola <italonicola@collabora.com> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5933>
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@ -129,9 +129,6 @@ typedef struct midgard_instruction {
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/* If the op supports it */
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enum midgard_roundmode roundmode;
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/* Special fields for an ALU instruction */
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midgard_reg_info registers;
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/* For textures: should helpers execute this instruction (instead of
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* just helping with derivatives)? Should helpers terminate after? */
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bool helper_terminate;
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@ -186,7 +183,6 @@ typedef struct midgard_instruction {
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union {
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midgard_load_store_word load_store;
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midgard_vector_alu alu;
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midgard_texture_word texture;
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midgard_branch_extended branch_extended;
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uint16_t br_compact;
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@ -164,7 +164,7 @@ mir_pack_swizzle_64(unsigned *swizzle, unsigned max_component)
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}
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static void
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mir_pack_mask_alu(midgard_instruction *ins)
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mir_pack_mask_alu(midgard_instruction *ins, midgard_vector_alu *alu)
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{
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unsigned effective = ins->mask;
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@ -177,19 +177,19 @@ mir_pack_mask_alu(midgard_instruction *ins)
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if (upper_shift >= 0) {
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effective >>= upper_shift;
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ins->alu.dest_override = upper_shift ?
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alu->dest_override = upper_shift ?
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midgard_dest_override_upper :
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midgard_dest_override_lower;
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} else {
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ins->alu.dest_override = midgard_dest_override_none;
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alu->dest_override = midgard_dest_override_none;
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}
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if (inst_size == 32)
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ins->alu.mask = expand_writemask(effective, 2);
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alu->mask = expand_writemask(effective, 2);
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else if (inst_size == 64)
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ins->alu.mask = expand_writemask(effective, 1);
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alu->mask = expand_writemask(effective, 1);
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else
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ins->alu.mask = effective;
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alu->mask = effective;
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}
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static unsigned
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@ -559,10 +559,11 @@ texture_word_from_instr(midgard_instruction *ins)
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static midgard_vector_alu
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vector_alu_from_instr(midgard_instruction *ins)
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{
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midgard_vector_alu alu = ins->alu;
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alu.op = ins->op;
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alu.outmod = ins->outmod;
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alu.reg_mode = reg_mode_for_bitsize(max_bitsize_for_alu(ins));
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midgard_vector_alu alu = {
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.op = ins->op,
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.outmod = ins->outmod,
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.reg_mode = reg_mode_for_bitsize(max_bitsize_for_alu(ins))
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};
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if (ins->has_inline_constant) {
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/* Encode inline 16-bit constant. See disassembler for
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@ -631,8 +632,8 @@ emit_alu_bundle(compiler_context *ctx,
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}
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if (ins->unit & UNITS_ANY_VECTOR) {
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mir_pack_mask_alu(ins);
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source_alu = vector_alu_from_instr(ins);
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mir_pack_mask_alu(ins, &source_alu);
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mir_pack_vector_srcs(ins, &source_alu);
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size = sizeof(midgard_vector_alu);
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source = &source_alu;
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@ -235,14 +235,12 @@ mir_print_constant_component(FILE *fp, const midgard_constants *consts, unsigned
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static void
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mir_print_embedded_constant(midgard_instruction *ins, unsigned src_idx)
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{
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midgard_vector_alu_src src;
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assert(src_idx <= 1);
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if (src_idx == 0)
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src = vector_alu_from_unsigned(ins->alu.src1);
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else
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src = vector_alu_from_unsigned(ins->alu.src2);
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unsigned base_size = max_bitsize_for_alu(ins);
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unsigned sz = nir_alu_type_get_type_size(ins->src_types[src_idx]);
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bool half = (sz == (base_size >> 1));
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unsigned mod = mir_pack_mod(ins, src_idx, false);
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unsigned *swizzle = ins->swizzle[src_idx];
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midgard_reg_mode reg_mode = reg_mode_for_bitsize(max_bitsize_for_alu(ins));
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unsigned comp_mask = effective_writemask(ins->op, ins->mask);
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@ -266,7 +264,7 @@ mir_print_embedded_constant(midgard_instruction *ins, unsigned src_idx)
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mir_print_constant_component(stdout, &ins->constants,
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swizzle[comp], reg_mode,
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src.half, src.mod, ins->op);
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half, mod, ins->op);
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}
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if (num_comp > 1)
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@ -424,10 +424,6 @@ mir_flip(midgard_instruction *ins)
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assert(ins->type == TAG_ALU_4);
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temp = ins->alu.src1;
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ins->alu.src1 = ins->alu.src2;
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ins->alu.src2 = temp;
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temp = ins->src_types[0];
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ins->src_types[0] = ins->src_types[1];
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ins->src_types[1] = temp;
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