radeon/llvm: Fix VTX_READ patterns
The VTX_READ instructions were using the ADDRParam ComplexPattern which allows a load instruction's offset to be a register, but VTX_READ instructions can only handle an immediate offset. Also, the load_param pattern fragment had an erroneous return true; statement that was causing it to match the wrong load instructions.
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c108831d44
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@ -69,6 +69,7 @@ private:
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bool SelectADDR8BitOffset(SDValue Addr, SDValue& Base, SDValue& Offset);
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bool SelectADDRReg(SDValue Addr, SDValue& Base, SDValue& Offset);
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bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
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// Include the pieces autogenerated from the target description.
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#include "AMDGPUGenDAGISel.inc"
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@ -556,6 +557,34 @@ bool AMDILDAGToDAGISel::SelectADDR8BitOffset(SDValue Addr, SDValue& Base,
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return true;
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}
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bool AMDILDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
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SDValue &Offset)
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{
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ConstantSDNode * IMMOffset;
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if (Addr.getOpcode() == ISD::ADD
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&& (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
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&& isInt<16>(IMMOffset->getZExtValue())) {
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Base = Addr.getOperand(0);
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Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
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return true;
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// If the pointer address is constant, we can move it to the offset field.
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} else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
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&& isInt<16>(IMMOffset->getZExtValue())) {
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Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
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CurDAG->getEntryNode().getDebugLoc(),
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AMDIL::ZERO, MVT::i32);
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Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
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return true;
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}
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// Default case, no offset
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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bool AMDILDAGToDAGISel::SelectADDRReg(SDValue Addr, SDValue& Base,
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SDValue& Offset) {
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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@ -255,7 +255,7 @@ bool R600CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
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emitByte(0);
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// offset
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emitTwoBytes(0);
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emitTwoBytes(MI.getOperand(2).getImm());
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// endian
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emitByte(0);
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@ -51,6 +51,7 @@ def MEMrr : Operand<iPTR> {
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def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
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def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>;
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def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>;
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class R600_ALU {
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@ -225,7 +226,6 @@ def store_global : PatFrag<(ops node:$value, node:$ptr),
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def load_param : PatFrag<(ops node:$ptr),
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(load node:$ptr),
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[{
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return true;
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const Value *Src = cast<LoadSDNode>(N)->getSrcValue();
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if (Src) {
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PointerType * PT = dyn_cast<PointerType>(Src->getType());
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@ -804,11 +804,11 @@ class VTX_READ_eg <int buffer_id, list<dag> pattern> : InstR600ISA <
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>;
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def VTX_READ_PARAM_eg : VTX_READ_eg <0,
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[(set (i32 R600_TReg32_X:$dst), (load_param ADDRParam:$ptr))]
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[(set (i32 R600_TReg32_X:$dst), (load_param ADDRVTX_READ:$ptr))]
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>;
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def VTX_READ_GLOBAL_eg : VTX_READ_eg <1,
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[(set (i32 R600_TReg32_X:$dst), (global_load ADDRParam:$ptr))]
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[(set (i32 R600_TReg32_X:$dst), (global_load ADDRVTX_READ:$ptr))]
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>;
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} // End isEG Predicate
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