evergreen : initial support driver code.
This commit is contained in:
richard
Alex Deucher
parent
501c9dc627
commit
0eac4b8740
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@ -59,6 +59,15 @@ DRIVER_SOURCES = \
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r600_texstate.c \
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r600_blit.c \
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r700_debug.c \
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evergreen_context.c \
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evergreen_state.c \
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evergreen_tex.c \
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evergreen_ioctl.c \
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evergreen_render.c \
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evergreen_chip.c \
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evergreen_vertprog.c \
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evergreen_fragprog.c \
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evergreen_oglprog.c \
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$(RADEON_COMMON_SOURCES) \
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$(EGL_SOURCES) \
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$(CS_SOURCES)
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,516 @@
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/*
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* Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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/*
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* Authors:
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* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
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*/
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#ifndef _EVERGREEN_CHIP_H_
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#define _EVERGREEN_CHIP_H_
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#include "r700_chip.h"
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#define EVERGREEN_MAX_DX9_CONSTS 256
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#define EVERGREEN_MAX_SHADER_EXPORTS 32
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#define EVERGREEN_MAX_VIEWPORTS 16
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typedef struct _EVERGREEN_VIEWPORT_STATE
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{
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union UINT_FLOAT PA_SC_VPORT_SCISSOR_0_TL; ////0,1 // = 0x28250, // DIFF
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union UINT_FLOAT PA_SC_VPORT_SCISSOR_0_BR; ////0,1 // = 0x28254, // DIFF
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union UINT_FLOAT PA_SC_VPORT_ZMIN_0; ////0 // = 0x282D0, // SAME
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union UINT_FLOAT PA_SC_VPORT_ZMAX_0; ////0 // = 0x282D4, // SAME
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union UINT_FLOAT PA_CL_VPORT_XSCALE; //// // = 0x2843C, // SAME
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union UINT_FLOAT PA_CL_VPORT_XOFFSET; //// // = 0x28440, // SAME
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union UINT_FLOAT PA_CL_VPORT_YSCALE; //// // = 0x28444, // SAME
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union UINT_FLOAT PA_CL_VPORT_YOFFSET; //// // = 0x28448, // SAME
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union UINT_FLOAT PA_CL_VPORT_ZSCALE; //// // = 0x2844C, // SAME
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union UINT_FLOAT PA_CL_VPORT_ZOFFSET; //// // = 0x28450, // SAME
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GLboolean enabled;
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GLboolean dirty;
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} EVERGREEN_VIEWPORT_STATE;
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#define EVERGREEN_MAX_UCP 6
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typedef struct _EVERGREEN_UCP_STATE
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{
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union UINT_FLOAT PA_CL_UCP_0_X; // = 0x285BC, // SAME 0x28E20
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union UINT_FLOAT PA_CL_UCP_0_Y; // = 0x285C0, // SAME 0x28E24
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union UINT_FLOAT PA_CL_UCP_0_Z; // = 0x285C4, // SAME 0x28E28
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union UINT_FLOAT PA_CL_UCP_0_W; // = 0x285C8, // SAME 0x28E2C
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GLboolean enabled;
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GLboolean dirty;
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} EVERGREEN_UCP_STATE;
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#define EVERGREEN_MAX_RENDER_TARGETS 12
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typedef struct _EVERGREEN_RENDER_TARGET_STATE
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{
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union UINT_FLOAT CB_COLOR0_BASE; ////0 // = 0x28C60, // SAME 0x28040
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union UINT_FLOAT CB_COLOR0_PITCH; ////0 // = 0x28C64, //
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union UINT_FLOAT CB_COLOR0_SLICE; ////0 // = 0x28C68, //
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union UINT_FLOAT CB_COLOR0_VIEW; ////0 // = 0x28C6C, // SAME 0x28080
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union UINT_FLOAT CB_COLOR0_INFO; ////0,1,2,3,4,5,6,78,9,10,11 // = 0x28C70, // DIFF 0x280A0
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union UINT_FLOAT CB_COLOR0_ATTRIB; ////0 // = 0x28C74, //
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union UINT_FLOAT CB_COLOR0_DIM; // = 0x28C78, //
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union UINT_FLOAT CB_COLOR0_CMASK; ////0 // = 0x28C7C, //
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union UINT_FLOAT CB_COLOR0_CMASK_SLICE; ////0 // = 0x28C80, //
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union UINT_FLOAT CB_COLOR0_FMASK; ////0 // = 0x28C84, //
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union UINT_FLOAT CB_COLOR0_FMASK_SLICE; ////0 // = 0x28C88, //
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union UINT_FLOAT CB_COLOR0_CLEAR_WORD0; // = 0x28C8C, //
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union UINT_FLOAT CB_COLOR0_CLEAR_WORD1; // = 0x28C90, //
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union UINT_FLOAT CB_COLOR0_CLEAR_WORD2; // = 0x28C94, //
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union UINT_FLOAT CB_COLOR0_CLEAR_WORD3; // = 0x28C98, //
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GLboolean enabled;
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GLboolean dirty;
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} EVERGREEN_RENDER_TARGET_STATE;
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typedef struct _EVERGREEN_CONFIG
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{
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union UINT_FLOAT SPI_CONFIG_CNTL; // = 0x9100, // DIFF
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union UINT_FLOAT SPI_CONFIG_CNTL_1; // = 0x913C, // DIFF
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union UINT_FLOAT CP_PERFMON_CNTL; // = 0x87FC, // SAME
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union UINT_FLOAT SQ_MS_FIFO_SIZES; // = 0x8CF0, // SAME
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union UINT_FLOAT SQ_CONFIG; // = 0x8C00, // DIFF
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union UINT_FLOAT SQ_GPR_RESOURCE_MGMT_1; // = 0x8C04, // SAME
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union UINT_FLOAT SQ_GPR_RESOURCE_MGMT_2; // = 0x8C08, // SAME
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union UINT_FLOAT SQ_GPR_RESOURCE_MGMT_3; // = 0x8C0C, //
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union UINT_FLOAT SQ_THREAD_RESOURCE_MGMT; // = 0x8C18, // SAME 0x8C0C
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union UINT_FLOAT SQ_THREAD_RESOURCE_MGMT_2; // = 0x8C1C, //
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union UINT_FLOAT SQ_STACK_RESOURCE_MGMT_1; // = 0x8C20, // SAME 0x8C10
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union UINT_FLOAT SQ_STACK_RESOURCE_MGMT_2; // = 0x8C24, // SAME 0x8C14
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union UINT_FLOAT SQ_STACK_RESOURCE_MGMT_3; // = 0x8C28, //
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union UINT_FLOAT SQ_DYN_GPR_CNTL_PS_FLUSH_REQ; // = 0x8D8C, // DIFF
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union UINT_FLOAT SQ_LDS_RESOURCE_MGMT; // = 0x8E2C, //
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union UINT_FLOAT VGT_CACHE_INVALIDATION; // = 0x88C4, // DIFF
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union UINT_FLOAT VGT_GS_VERTEX_REUSE; // = 0x88D4, // SAME
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union UINT_FLOAT PA_SC_FORCE_EOV_MAX_CNTS; // = 0x8B24, // SAME
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union UINT_FLOAT PA_SC_LINE_STIPPLE_STATE; // = 0x8B10, // SAME
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union UINT_FLOAT PA_CL_ENHANCE; // = 0x8A14, // SAME
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} EVERGREEN_CONFIG;
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typedef struct _EVERGREEN_PS_RES
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{
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union UINT_FLOAT SQ_PGM_START_PS; //// // = 0x28840, // SAME
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GLboolean dirty;
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union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_0; // = 0x28940, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_1; // = 0x28944, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_2; // = 0x28948, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_3; // = 0x2894C, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_4; // = 0x28950, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_5; // = 0x28954, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_6; // = 0x28958, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_7; // = 0x2895C, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_8; // = 0x28960, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_9; // = 0x28964, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_10; // = 0x28968, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_11; // = 0x2896C, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_12; // = 0x28970, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_13; // = 0x28974, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_14; // = 0x28978, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_15; // = 0x2897C, // SAME
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int num_consts;
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union UINT_FLOAT consts[EVERGREEN_MAX_DX9_CONSTS][4];
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} EVERGREEN_PS_RES;
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typedef struct _EVERGREEN_VS_RES
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{
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union UINT_FLOAT SQ_PGM_START_VS; //// // = 0x2885C, // SAME 0x28858
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union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_VS_0; //// // = 0x28180, //?
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union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_0; //// // = 0x28980, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_1; // = 0x28984, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_2; // = 0x28988, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_3; // = 0x2898C, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_4; // = 0x28990, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_5; // = 0x28994, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_6; // = 0x28998, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_7; // = 0x2899C, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_8; // = 0x289A0, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_9; // = 0x289A4, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_10; // = 0x289A8, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_11; // = 0x289AC, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_12; // = 0x289B0, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_13; // = 0x289B4, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_14; // = 0x289B8, // SAME
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union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_15; // = 0x289BC, // SAME
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GLboolean dirty;
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int num_consts;
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union UINT_FLOAT consts[EVERGREEN_MAX_DX9_CONSTS][4];
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} EVERGREEN_VS_RES;
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typedef struct _EVERGREEN_CHIP_CONTEXT
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{
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/* Registers from PA block: */
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union UINT_FLOAT PA_SC_SCREEN_SCISSOR_TL; //// // = 0x28030, // DIFF
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union UINT_FLOAT PA_SC_SCREEN_SCISSOR_BR; //// // = 0x28034, // DIFF
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union UINT_FLOAT PA_SC_WINDOW_OFFSET; //// // = 0x28200, // DIFF
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union UINT_FLOAT PA_SC_WINDOW_SCISSOR_TL; //// // = 0x28204, // DIFF
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union UINT_FLOAT PA_SC_WINDOW_SCISSOR_BR; //// // = 0x28208, // DIFF
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union UINT_FLOAT PA_SC_CLIPRECT_RULE; //// // = 0x2820C, // SAME
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union UINT_FLOAT PA_SC_CLIPRECT_0_TL; //// // = 0x28210, // DIFF
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union UINT_FLOAT PA_SC_CLIPRECT_0_BR; //// // = 0x28214, // DIFF
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union UINT_FLOAT PA_SC_CLIPRECT_1_TL; //// // = 0x28218, // DIFF
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union UINT_FLOAT PA_SC_CLIPRECT_1_BR; //// // = 0x2821C, // DIFF
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union UINT_FLOAT PA_SC_CLIPRECT_2_TL; //// // = 0x28220, // DIFF
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union UINT_FLOAT PA_SC_CLIPRECT_2_BR; //// // = 0x28224, // DIFF
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union UINT_FLOAT PA_SC_CLIPRECT_3_TL; //// // = 0x28228, // DIFF
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union UINT_FLOAT PA_SC_CLIPRECT_3_BR; //// // = 0x2822C, // DIFF
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union UINT_FLOAT PA_SC_EDGERULE; // = 0x28230, // SAME
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union UINT_FLOAT PA_SU_HARDWARE_SCREEN_OFFSET; // = 0x28234, //
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union UINT_FLOAT PA_SC_GENERIC_SCISSOR_TL; //// // = 0x28240, // DIFF
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union UINT_FLOAT PA_SC_GENERIC_SCISSOR_BR; //// // = 0x28244, // DIFF
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EVERGREEN_VIEWPORT_STATE viewport[EVERGREEN_MAX_VIEWPORTS];
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EVERGREEN_UCP_STATE ucp[EVERGREEN_MAX_UCP];
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union UINT_FLOAT PA_CL_POINT_X_RAD; // = 0x287D4, // SAME 0x28E10
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union UINT_FLOAT PA_CL_POINT_Y_RAD; // = 0x287D8, // SAME 0x28E14
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union UINT_FLOAT PA_CL_POINT_SIZE; // = 0x287DC, // SAME 0x28E18
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union UINT_FLOAT PA_CL_POINT_CULL_RAD; // = 0x287E0, // SAME 0x28E1C
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union UINT_FLOAT PA_CL_CLIP_CNTL; //// // = 0x28810, // SAME
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union UINT_FLOAT PA_SU_SC_MODE_CNTL; //// // = 0x28814, // SAME
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union UINT_FLOAT PA_CL_VTE_CNTL; //// // = 0x28818, // SAME
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union UINT_FLOAT PA_CL_VS_OUT_CNTL; //// // = 0x2881C, // SAME
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union UINT_FLOAT PA_CL_NANINF_CNTL; //// // = 0x28820, // SAME
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union UINT_FLOAT PA_SU_LINE_STIPPLE_CNTL; // = 0x28824, //
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union UINT_FLOAT PA_SU_LINE_STIPPLE_SCALE; // = 0x28828, //
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union UINT_FLOAT PA_SU_PRIM_FILTER_CNTL; // = 0x2882C, //
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union UINT_FLOAT PA_SU_POINT_SIZE; //// // = 0x28A00, // SAME
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union UINT_FLOAT PA_SU_POINT_MINMAX; //// // = 0x28A04, // SAME
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union UINT_FLOAT PA_SU_LINE_CNTL; //// // = 0x28A08, // SAME
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union UINT_FLOAT PA_SC_LINE_STIPPLE; // = 0x28A0C, // SAME
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union UINT_FLOAT PA_SC_MODE_CNTL_0; //// // = 0x28A48, //
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union UINT_FLOAT PA_SC_MODE_CNTL_1; //// // = 0x28A4C, //
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union UINT_FLOAT PA_SU_POLY_OFFSET_DB_FMT_CNTL; //// // = 0x28B78, // SAME 0x28DF8
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union UINT_FLOAT PA_SU_POLY_OFFSET_CLAMP; //// // = 0x28B7C, // SAME 0x28DFC
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union UINT_FLOAT PA_SU_POLY_OFFSET_FRONT_SCALE;//// // = 0x28B80, // SAME 0x28E00
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union UINT_FLOAT PA_SU_POLY_OFFSET_FRONT_OFFSET; //// // = 0x28B84, // SAME 0x28E04
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union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_SCALE; //// // = 0x28B88, // SAME 0x28E08
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union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_OFFSET; //// // = 0x28B8C, // SAME 0x28E0C
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union UINT_FLOAT PA_SC_LINE_CNTL; //// // = 0x28C00, // DIFF
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union UINT_FLOAT PA_SC_AA_CONFIG; //// // = 0x28C04, // SAME
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union UINT_FLOAT PA_SU_VTX_CNTL; //// // = 0x28C08, // SAME
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union UINT_FLOAT PA_CL_GB_VERT_CLIP_ADJ; //// // = 0x28C0C, // SAME
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union UINT_FLOAT PA_CL_GB_VERT_DISC_ADJ; //// // = 0x28C10, // SAME
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union UINT_FLOAT PA_CL_GB_HORZ_CLIP_ADJ; //// // = 0x28C14, // SAME
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union UINT_FLOAT PA_CL_GB_HORZ_DISC_ADJ; //// // = 0x28C18, // SAME
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union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_0; //// // = 0x28C1C, //
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union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_1; //// // = 0x28C20, //
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union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_2; //// // = 0x28C24, //
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union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_3; //// // = 0x28C28, //
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union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_4; //// // = 0x28C2C, //
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union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_5; //// // = 0x28C30, //
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union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_6; //// // = 0x28C34, //
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union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_7; //// // = 0x28C38, //
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union UINT_FLOAT PA_SC_AA_MASK; //// // = 0x28C3C, // SAME 0x28C48
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/* Registers from VGT block: */
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union UINT_FLOAT VGT_INDEX_TYPE; // = 0x895C, // SAME
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union UINT_FLOAT VGT_PRIMITIVE_TYPE; // = 0x8958, // SAME
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union UINT_FLOAT VGT_MAX_VTX_INDX; //// // = 0x28400, // SAME
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union UINT_FLOAT VGT_MIN_VTX_INDX; //// // = 0x28404, // SAME
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union UINT_FLOAT VGT_INDX_OFFSET; //// // = 0x28408, // SAME
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union UINT_FLOAT VGT_MULTI_PRIM_IB_RESET_INDX; // = 0x2840C, // SAME
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union UINT_FLOAT VGT_DRAW_INITIATOR; // = 0x287F0, // SAME
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union UINT_FLOAT VGT_IMMED_DATA; // = 0x287F4, // SAME
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union UINT_FLOAT VGT_OUTPUT_PATH_CNTL; //// // = 0x28A10, // DIFF
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union UINT_FLOAT VGT_HOS_CNTL; // = 0x28A14, // SAME
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union UINT_FLOAT VGT_HOS_MAX_TESS_LEVEL; // = 0x28A18, // SAME
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union UINT_FLOAT VGT_HOS_MIN_TESS_LEVEL; // = 0x28A1C, // SAME
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union UINT_FLOAT VGT_HOS_REUSE_DEPTH; // = 0x28A20, // SAME
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union UINT_FLOAT VGT_GROUP_PRIM_TYPE; // = 0x28A24, // SAME
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union UINT_FLOAT VGT_GROUP_FIRST_DECR; // = 0x28A28, // SAME
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union UINT_FLOAT VGT_GROUP_DECR; // = 0x28A2C, // SAME
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union UINT_FLOAT VGT_GROUP_VECT_0_CNTL; // = 0x28A30, // SAME
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union UINT_FLOAT VGT_GROUP_VECT_1_CNTL; // = 0x28A34, // SAME
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union UINT_FLOAT VGT_GROUP_VECT_0_FMT_CNTL; // = 0x28A38, // SAME
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union UINT_FLOAT VGT_GROUP_VECT_1_FMT_CNTL; // = 0x28A3C, // SAME
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union UINT_FLOAT VGT_GS_MODE; //// // = 0x28A40, // DIFF
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union UINT_FLOAT VGT_PRIMITIVEID_EN; //// // = 0x28A84, // SAME
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union UINT_FLOAT VGT_DMA_NUM_INSTANCES; //// // = 0x28A88, // SAME
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union UINT_FLOAT VGT_EVENT_INITIATOR; // = 0x28A90, // SAME
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union UINT_FLOAT VGT_MULTI_PRIM_IB_RESET_EN; // = 0x28A94, // SAME
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union UINT_FLOAT VGT_INSTANCE_STEP_RATE_0; //// // = 0x28AA0, // SAME
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union UINT_FLOAT VGT_INSTANCE_STEP_RATE_1; //// // = 0x28AA4, // SAME
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union UINT_FLOAT VGT_REUSE_OFF; //// // = 0x28AB4, // SAME
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union UINT_FLOAT VGT_VTX_CNT_EN; //// // = 0x28AB8, // SAME
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union UINT_FLOAT VGT_SHADER_STAGES_EN; //// // = 0x28B54, //
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union UINT_FLOAT VGT_STRMOUT_CONFIG; //// // = 0x28B94, //
|
||||
union UINT_FLOAT VGT_STRMOUT_BUFFER_CONFIG; //// // = 0x28B98, //
|
||||
union UINT_FLOAT VGT_VERTEX_REUSE_BLOCK_CNTL;//// // = 0x28C58, // SAME
|
||||
union UINT_FLOAT VGT_OUT_DEALLOC_CNTL; //// // = 0x28C5C, // SAME
|
||||
|
||||
/* Registers from SQ block: */
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_0; //// // = 0x28380, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_1; //// // = 0x28384, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_2; //// // = 0x28388, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_3; //// // = 0x2838C, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_4; //// // = 0x28390, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_5; //// // = 0x28394, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_6; //// // = 0x28398, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_7; //// // = 0x2839C, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_8; //// // = 0x283A0, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_9; //// // = 0x283A4, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_10; //// // = 0x283A8, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_11; //// // = 0x283AC, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_12; //// // = 0x283B0, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_13; //// // = 0x283B4, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_14; //// // = 0x283B8, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_15; //// // = 0x283BC, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_16; //// // = 0x283C0, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_17; //// // = 0x283C4, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_18; //// // = 0x283C8, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_19; //// // = 0x283CC, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_20; //// // = 0x283D0, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_21; //// // = 0x283D4, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_22; //// // = 0x283D8, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_23; //// // = 0x283DC, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_24; //// // = 0x283E0, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_25; //// // = 0x283E4, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_26; //// // = 0x283E8, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_27; //// // = 0x283EC, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_28; //// // = 0x283F0, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_29; //// // = 0x283F4, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_30; //// // = 0x283F8, // SAME
|
||||
union UINT_FLOAT SQ_VTX_SEMANTIC_31; //// // = 0x283FC, // SAME
|
||||
union UINT_FLOAT SQ_DYN_GPR_RESOURCE_LIMIT_1;//// // = 0x28838, //
|
||||
|
||||
union UINT_FLOAT SQ_PGM_RESOURCES_PS; //// // = 0x28844, // DIFF 0x28850
|
||||
union UINT_FLOAT SQ_PGM_RESOURCES_2_PS; //// // = 0x28848, //
|
||||
union UINT_FLOAT SQ_PGM_EXPORTS_PS; //// // = 0x2884C, // SAME 0x28854
|
||||
|
||||
union UINT_FLOAT SQ_PGM_RESOURCES_VS;//// // = 0x28860, // DIFF 0x28868
|
||||
union UINT_FLOAT SQ_PGM_RESOURCES_2_VS; //// // = 0x28864, //
|
||||
union UINT_FLOAT SQ_PGM_START_GS; //// // = 0x28874, // SAME 0x2886C
|
||||
union UINT_FLOAT SQ_PGM_RESOURCES_GS; //// // = 0x28878, // DIFF 0x2887C
|
||||
union UINT_FLOAT SQ_PGM_RESOURCES_2_GS; //// // = 0x2887C, //
|
||||
union UINT_FLOAT SQ_PGM_START_ES; //// // = 0x2888C, // SAME 0x28880
|
||||
union UINT_FLOAT SQ_PGM_RESOURCES_ES; //// // = 0x28890, // DIFF
|
||||
union UINT_FLOAT SQ_PGM_RESOURCES_2_ES; //// // = 0x28894, //
|
||||
union UINT_FLOAT SQ_PGM_START_FS; //// // = 0x288A4, // SAME 0x28894
|
||||
union UINT_FLOAT SQ_PGM_RESOURCES_FS; //// // = 0x288A8, // DIFF 0x288A4
|
||||
union UINT_FLOAT SQ_PGM_START_HS; // = 0x288B8, //
|
||||
union UINT_FLOAT SQ_PGM_RESOURCES_HS; // = 0x288BC, //
|
||||
union UINT_FLOAT SQ_PGM_RESOURCES_2_HS;//// // = 0x288C0, //
|
||||
union UINT_FLOAT SQ_PGM_START_LS; // = 0x288D0, //
|
||||
union UINT_FLOAT SQ_PGM_RESOURCES_LS; // = 0x288D4, //
|
||||
union UINT_FLOAT SQ_PGM_RESOURCES_2_LS; //// // = 0x288D8, //
|
||||
union UINT_FLOAT SQ_LDS_ALLOC_PS; //// // = 0x288EC, //
|
||||
union UINT_FLOAT SQ_ESGS_RING_ITEMSIZE; //// // = 0x28900, // SAME 0x288A8
|
||||
union UINT_FLOAT SQ_GSVS_RING_ITEMSIZE; //// // = 0x28904, // SAME 0x288AC
|
||||
union UINT_FLOAT SQ_ESTMP_RING_ITEMSIZE; //// // = 0x28908, // SAME 0x288B0
|
||||
union UINT_FLOAT SQ_GSTMP_RING_ITEMSIZE; //// // = 0x2890C, // SAME 0x288B4
|
||||
union UINT_FLOAT SQ_VSTMP_RING_ITEMSIZE; //// // = 0x28910, // SAME 0x288B8
|
||||
union UINT_FLOAT SQ_PSTMP_RING_ITEMSIZE; //// // = 0x28914, // SAME 0x288BC
|
||||
union UINT_FLOAT SQ_GS_VERT_ITEMSIZE; //// // = 0x2891C, // SAME 0x288C8
|
||||
union UINT_FLOAT SQ_GS_VERT_ITEMSIZE_1; // = 0x28920, //
|
||||
union UINT_FLOAT SQ_GS_VERT_ITEMSIZE_2; // = 0x28924, //
|
||||
union UINT_FLOAT SQ_GS_VERT_ITEMSIZE_3; // = 0x28928, //
|
||||
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_0; // = 0x289C0, // SAME
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_1; // = 0x289C4, // SAME
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_2; // = 0x289C8, // SAME
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_3; // = 0x289CC, // SAME
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_4; // = 0x289D0, // SAME
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_5; // = 0x289D4, // SAME
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_6; // = 0x289D8, // SAME
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_7; // = 0x289DC, // SAME
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_8; // = 0x289E0, // SAME
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_9; // = 0x289E4, // SAME
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_10; // = 0x289E8, // SAME
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_11; // = 0x289EC, // SAME
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_12; // = 0x289F0, // SAME
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_13; // = 0x289F4, // SAME
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_14; // = 0x289F8, // SAME
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_15; // = 0x289FC, // SAME
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_0; // = 0x28F00, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_1; // = 0x28F04, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_2; // = 0x28F08, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_3; // = 0x28F0C, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_4; // = 0x28F10, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_5; // = 0x28F14, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_6; // = 0x28F18, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_7; // = 0x28F1C, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_8; // = 0x28F20, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_9; // = 0x28F24, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_10; // = 0x28F28, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_11; // = 0x28F2C, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_12; // = 0x28F30, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_13; // = 0x28F34, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_14; // = 0x28F38, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_15; // = 0x28F3C, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_0; // = 0x28F40, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_1; // = 0x28F44, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_2; // = 0x28F48, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_3; // = 0x28F4C, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_4; // = 0x28F50, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_5; // = 0x28F54, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_6; // = 0x28F58, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_7; // = 0x28F5C, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_8; // = 0x28F60, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_9; // = 0x28F64, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_10; // = 0x28F68, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_11; // = 0x28F6C, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_12; // = 0x28F70, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_13; // = 0x28F74, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_14; // = 0x28F78, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_15; // = 0x28F7C, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_0; // = 0x28F80, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_1; // = 0x28F84, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_2; // = 0x28F88, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_3; // = 0x28F8C, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_4; // = 0x28F90, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_5; // = 0x28F94, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_6; // = 0x28F98, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_7; // = 0x28F9C, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_8; // = 0x28FA0, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_9; // = 0x28FA4, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_10; // = 0x28FA8, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_11; // = 0x28FAC, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_12; // = 0x28FB0, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_13; // = 0x28FB4, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_14; // = 0x28FB8, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_15; // = 0x28FBC, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_0; // = 0x28FC0, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_1; // = 0x28FC4, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_2; // = 0x28FC8, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_3; // = 0x28FCC, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_4; // = 0x28FD0, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_5; // = 0x28FD4, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_6; // = 0x28FD8, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_7; // = 0x28FDC, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_8; // = 0x28FE0, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_9; // = 0x28FE4, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_10; // = 0x28FE8, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_11; // = 0x28FEC, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_12; // = 0x28FF0, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_13; // = 0x28FF4, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_14; // = 0x28FF8, //
|
||||
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_15; // = 0x28FFC, //
|
||||
|
||||
EVERGREEN_PS_RES ps;
|
||||
EVERGREEN_VS_RES vs;
|
||||
|
||||
/* Registers from SPI block: */
|
||||
union UINT_FLOAT SPI_VS_OUT_ID_0; //// // = 0x2861C, // SAME 0x28614
|
||||
union UINT_FLOAT SPI_VS_OUT_ID_1; //// // = 0x28620, // SAME 0x28618
|
||||
union UINT_FLOAT SPI_VS_OUT_ID_2; //// // = 0x28624, // SAME 0x2861C
|
||||
union UINT_FLOAT SPI_VS_OUT_ID_3; //// // = 0x28628, // SAME 0x28620
|
||||
union UINT_FLOAT SPI_VS_OUT_ID_4; //// // = 0x2862C, // SAME 0x28624
|
||||
union UINT_FLOAT SPI_VS_OUT_ID_5; //// // = 0x28630, // SAME 0x28628
|
||||
union UINT_FLOAT SPI_VS_OUT_ID_6; //// // = 0x28634, // SAME 0x2862C
|
||||
union UINT_FLOAT SPI_VS_OUT_ID_7; //// // = 0x28638, // SAME 0x28630
|
||||
union UINT_FLOAT SPI_VS_OUT_ID_8; //// // = 0x2863C, // SAME 0x28634
|
||||
union UINT_FLOAT SPI_VS_OUT_ID_9; //// // = 0x28640, // SAME 0x28638
|
||||
union UINT_FLOAT SPI_PS_INPUT_CNTL[32]; //// // = 0x28644, // SAME
|
||||
|
||||
union UINT_FLOAT SPI_VS_OUT_CONFIG; //// // = 0x286C4, // SAME
|
||||
union UINT_FLOAT SPI_THREAD_GROUPING; //// // = 0x286C8, // DIFF
|
||||
union UINT_FLOAT SPI_PS_IN_CONTROL_0; //// // = 0x286CC, // SAME
|
||||
union UINT_FLOAT SPI_PS_IN_CONTROL_1; //// // = 0x286D0, // SAME
|
||||
union UINT_FLOAT SPI_INTERP_CONTROL_0; //// // = 0x286D4, // SAME
|
||||
union UINT_FLOAT SPI_INPUT_Z; //// // = 0x286D8, // SAME
|
||||
union UINT_FLOAT SPI_FOG_CNTL; //// // = 0x286DC, // SAME
|
||||
union UINT_FLOAT SPI_BARYC_CNTL; //// // = 0x286E0, //
|
||||
union UINT_FLOAT SPI_PS_IN_CONTROL_2; //// // = 0x286E4, //
|
||||
union UINT_FLOAT SPI_COMPUTE_INPUT_CNTL; // = 0x286E8, //
|
||||
union UINT_FLOAT SPI_COMPUTE_NUM_THREAD_X; // = 0x286EC, //
|
||||
union UINT_FLOAT SPI_COMPUTE_NUM_THREAD_Y; // = 0x286F0, //
|
||||
union UINT_FLOAT SPI_COMPUTE_NUM_THREAD_Z; // = 0x286F4, //
|
||||
|
||||
/* Registers from SX block: */
|
||||
union UINT_FLOAT SX_MISC; // = 0x28350, // SAME
|
||||
union UINT_FLOAT SX_SURFACE_SYNC; // = 0x28354, // DIFF
|
||||
union UINT_FLOAT SX_ALPHA_TEST_CONTROL; //// // = 0x28410, // SAME
|
||||
union UINT_FLOAT SX_ALPHA_REF; // = 0x28438, // SAME
|
||||
|
||||
/* Registers from DB block: */
|
||||
union UINT_FLOAT DB_RENDER_CONTROL; //// // = 0x28000, // DIFF 0x28D0C
|
||||
union UINT_FLOAT DB_COUNT_CONTROL; //// // = 0x28004, //
|
||||
union UINT_FLOAT DB_DEPTH_VIEW; //// // = 0x28008, // DIFF 0x28004
|
||||
union UINT_FLOAT DB_RENDER_OVERRIDE; //// // = 0x2800C, // DIFF 0x28D10
|
||||
union UINT_FLOAT DB_RENDER_OVERRIDE2; //// // = 0x28010, //
|
||||
union UINT_FLOAT DB_HTILE_DATA_BASE; //// // = 0x28014, // SAME
|
||||
union UINT_FLOAT DB_STENCIL_CLEAR; //// // = 0x28028, // SAME
|
||||
union UINT_FLOAT DB_DEPTH_CLEAR; //// // = 0x2802C, // SAME
|
||||
union UINT_FLOAT DB_Z_INFO; //// // = 0x28040, //
|
||||
union UINT_FLOAT DB_STENCIL_INFO; //// // = 0x28044, //
|
||||
union UINT_FLOAT DB_Z_READ_BASE; //// // = 0x28048, //
|
||||
union UINT_FLOAT DB_STENCIL_READ_BASE;//// // = 0x2804C, //
|
||||
union UINT_FLOAT DB_Z_WRITE_BASE; //// // = 0x28050, //
|
||||
union UINT_FLOAT DB_STENCIL_WRITE_BASE; //// // = 0x28054, //
|
||||
union UINT_FLOAT DB_DEPTH_SIZE; //// // = 0x28058, // DIFF 0x28000
|
||||
union UINT_FLOAT DB_DEPTH_SLICE; //// // = 0x2805C, //
|
||||
union UINT_FLOAT DB_STENCILREFMASK; // = 0x28430, // SAME
|
||||
union UINT_FLOAT DB_STENCILREFMASK_BF; // = 0x28434, // SAME
|
||||
union UINT_FLOAT DB_DEPTH_CONTROL; //// // = 0x28800, // SAME
|
||||
union UINT_FLOAT DB_SHADER_CONTROL;//// // = 0x2880C, // DIFF
|
||||
union UINT_FLOAT DB_HTILE_SURFACE; //// // = 0x28ABC, // SAME 0x28D24
|
||||
union UINT_FLOAT DB_SRESULTS_COMPARE_STATE0; //// // = 0x28AC0, // SAME 0x28D28
|
||||
union UINT_FLOAT DB_SRESULTS_COMPARE_STATE1; //// // = 0x28AC4, // SAME 0x28D2C
|
||||
union UINT_FLOAT DB_PRELOAD_CONTROL; //// // = 0x28AC8, // SAME 0x28D30
|
||||
union UINT_FLOAT DB_ALPHA_TO_MASK; //// // = 0x28B70, // SAME 0x28D44
|
||||
|
||||
/* Registers from CB block: */
|
||||
union UINT_FLOAT CB_TARGET_MASK; //// // = 0x28238, // SAME
|
||||
union UINT_FLOAT CB_SHADER_MASK; //// // = 0x2823C, // SAME
|
||||
union UINT_FLOAT CB_BLEND_RED; //// // = 0x28414, // SAME
|
||||
union UINT_FLOAT CB_BLEND_GREEN; //// // = 0x28418, // SAME
|
||||
union UINT_FLOAT CB_BLEND_BLUE; //// // = 0x2841C, // SAME
|
||||
union UINT_FLOAT CB_BLEND_ALPHA; //// // = 0x28420, // SAME
|
||||
union UINT_FLOAT CB_BLEND0_CONTROL; //// // = 0x28780, // DIFF
|
||||
union UINT_FLOAT CB_BLEND1_CONTROL; // = 0x28784, // DIFF
|
||||
union UINT_FLOAT CB_BLEND2_CONTROL; // = 0x28788, // DIFF
|
||||
union UINT_FLOAT CB_BLEND3_CONTROL; // = 0x2878C, // DIFF
|
||||
union UINT_FLOAT CB_BLEND4_CONTROL; // = 0x28790, // DIFF
|
||||
union UINT_FLOAT CB_BLEND5_CONTROL; // = 0x28794, // DIFF
|
||||
union UINT_FLOAT CB_BLEND6_CONTROL; // = 0x28798, // DIFF
|
||||
union UINT_FLOAT CB_BLEND7_CONTROL; // = 0x2879C, // DIFF
|
||||
union UINT_FLOAT CB_COLOR_CONTROL; //// // = 0x28808, // DIFF
|
||||
union UINT_FLOAT CB_CLRCMP_CONTROL; //// // = 0x28C40, // SAME 0x28C30
|
||||
union UINT_FLOAT CB_CLRCMP_SRC; //// // = 0x28C44, // SAME 0x28C34
|
||||
union UINT_FLOAT CB_CLRCMP_DST; //// // = 0x28C48, // SAME 0x28C38
|
||||
union UINT_FLOAT CB_CLRCMP_MSK; //// // = 0x28C4C, // SAME 0x28C3C
|
||||
|
||||
EVERGREEN_RENDER_TARGET_STATE render_target[EVERGREEN_MAX_RENDER_TARGETS];
|
||||
|
||||
radeonTexObj* textures[R700_TEXTURE_NUMBERUNITS];
|
||||
|
||||
EVERGREEN_CONFIG evergreen_config;
|
||||
|
||||
GLboolean bEnablePerspective;
|
||||
|
||||
} EVERGREEN_CHIP_CONTEXT;
|
||||
|
||||
#endif /* _EVERGREEN_CHIP_H_ */
|
||||
|
|
@ -0,0 +1,109 @@
|
|||
/*
|
||||
* Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Authors:
|
||||
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
|
||||
*/
|
||||
|
||||
#include "main/glheader.h"
|
||||
#include "main/api_arrayelt.h"
|
||||
#include "main/context.h"
|
||||
#include "main/simple_list.h"
|
||||
#include "main/imports.h"
|
||||
#include "main/extensions.h"
|
||||
#include "main/bufferobj.h"
|
||||
#include "main/texobj.h"
|
||||
|
||||
#include "radeon_common_context.h"
|
||||
#include "evergreen_context.h"
|
||||
#include "evergreen_state.h"
|
||||
#include "r600_blit.h"
|
||||
|
||||
#include "utils.h"
|
||||
|
||||
static void evergreen_get_lock(radeonContextPtr rmesa)
|
||||
{
|
||||
drm_radeon_sarea_t *sarea = rmesa->sarea;
|
||||
|
||||
if (sarea->ctx_owner != rmesa->dri.hwContext) {
|
||||
sarea->ctx_owner = rmesa->dri.hwContext;
|
||||
if (!rmesa->radeonScreen->kernel_mm)
|
||||
radeon_bo_legacy_texture_age(rmesa->radeonScreen->bom);
|
||||
}
|
||||
}
|
||||
|
||||
static void evergreen_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
|
||||
{
|
||||
/* please flush pipe do all pending work */
|
||||
/* to be enabled */
|
||||
}
|
||||
|
||||
static void evergreen_vtbl_pre_emit_atoms(radeonContextPtr radeon)
|
||||
{
|
||||
//TODO apr.01
|
||||
//r700Start3D((context_t *)radeon);
|
||||
}
|
||||
|
||||
static void evergreen_fallback(GLcontext *ctx, GLuint bit, GLboolean mode)
|
||||
{
|
||||
context_t *context = EVERGREEN_CONTEXT(ctx);
|
||||
if (mode)
|
||||
context->radeon.Fallback |= bit;
|
||||
else
|
||||
context->radeon.Fallback &= ~bit;
|
||||
}
|
||||
|
||||
static void evergreen_emit_query_finish(radeonContextPtr radeon)
|
||||
{
|
||||
//TODO apr.01
|
||||
//context_t *context = (context_t*) radeon;
|
||||
//BATCH_LOCALS(&context->radeon);
|
||||
|
||||
struct radeon_query_object *query = radeon->query.current;
|
||||
|
||||
//BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
|
||||
//R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
|
||||
//R600_OUT_BATCH(ZPASS_DONE);
|
||||
//R600_OUT_BATCH(query->curr_offset + 8); /* hw writes qwords */
|
||||
//R600_OUT_BATCH(0x00000000);
|
||||
//R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
|
||||
//END_BATCH();
|
||||
//assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
|
||||
query->emitted_begin = GL_FALSE;
|
||||
}
|
||||
|
||||
void evergreen_init_vtbl(radeonContextPtr radeon)
|
||||
{
|
||||
radeon->vtbl.get_lock = evergreen_get_lock;
|
||||
radeon->vtbl.update_viewport_offset = evergreenUpdateViewportOffset;
|
||||
radeon->vtbl.emit_cs_header = evergreen_vtbl_emit_cs_header;
|
||||
radeon->vtbl.swtcl_flush = NULL;
|
||||
radeon->vtbl.pre_emit_atoms = evergreen_vtbl_pre_emit_atoms;
|
||||
radeon->vtbl.fallback = evergreen_fallback;
|
||||
radeon->vtbl.emit_query_finish = evergreen_emit_query_finish;
|
||||
radeon->vtbl.check_blit = r600_check_blit;
|
||||
radeon->vtbl.blit = r600_blit;
|
||||
radeon->vtbl.is_format_renderable = radeonIsFormatRenderable;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Authors:
|
||||
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef _EVERGREEN_CONTEXT_H_
|
||||
#define _EVERGREEN_CONTEXT_H_
|
||||
|
||||
extern void evergreen_init_vtbl(radeonContextPtr radeon);
|
||||
|
||||
#endif //_EVERGREEN_CONTEXT_H_
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,335 @@
|
|||
/*
|
||||
* Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Authors:
|
||||
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef _EVERGREEN_DIFF_H_
|
||||
#define _EVERGREEN_DIFF_H_
|
||||
|
||||
enum {
|
||||
/* CB_BLEND_CONTROL */
|
||||
EG_CB_BLENDX_CONTROL_ENABLE_bit = 1 << 30,
|
||||
/* PA_SC_SCREEN_SCISSOR_TL */
|
||||
EG_PA_SC_SCREEN_SCISSOR_TL__TL_X_mask = 0xffff << 0,
|
||||
EG_PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask = 0xffff << 16,
|
||||
/* PA_SC_SCREEN_SCISSOR_BR */
|
||||
EG_PA_SC_SCREEN_SCISSOR_BR__BR_X_mask = 0xffff << 0,
|
||||
EG_PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask = 0xffff << 16,
|
||||
/* PA_SC_WINDOW_SCISSOR_TL */
|
||||
EG_PA_SC_WINDOW_SCISSOR_TL__TL_X_mask = 0x7fff << 0,
|
||||
EG_PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask = 0x7fff << 16,
|
||||
/* PA_SC_WINDOW_SCISSOR_BR */
|
||||
EG_PA_SC_WINDOW_SCISSOR_BR__BR_X_mask = 0x7fff << 0,
|
||||
EG_PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask = 0x7fff << 16,
|
||||
/* PA_SC_CLIPRECT_0_TL */
|
||||
EG_PA_SC_CLIPRECT_0_TL__TL_X_mask = 0x7fff << 0,
|
||||
EG_PA_SC_CLIPRECT_0_TL__TL_Y_mask = 0x7fff << 16,
|
||||
/* PA_SC_CLIPRECT_0_BR */
|
||||
EG_PA_SC_CLIPRECT_0_BR__BR_X_mask = 0x7fff << 0,
|
||||
EG_PA_SC_CLIPRECT_0_BR__BR_Y_mask = 0x7fff << 16,
|
||||
/* PA_SC_GENERIC_SCISSOR_TL */
|
||||
EG_PA_SC_GENERIC_SCISSOR_TL__TL_X_mask = 0x7fff << 0,
|
||||
EG_PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask = 0x7fff << 16,
|
||||
/* PA_SC_GENERIC_SCISSOR_BR */
|
||||
EG_PA_SC_GENERIC_SCISSOR_BR__BR_X_mask = 0x7fff << 0,
|
||||
EG_PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask = 0x7fff << 16,
|
||||
/* PA_SC_VPORT_SCISSOR_0_TL */
|
||||
EG_PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask = 0x7fff << 0,
|
||||
EG_PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask = 0x7fff << 16,
|
||||
/* PA_SC_VPORT_SCISSOR_0_BR */
|
||||
EG_PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask = 0x7fff << 0,
|
||||
EG_PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask = 0x7fff << 16,
|
||||
/* PA_SC_WINDOW_OFFSET */
|
||||
EG_PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_shift = 0,
|
||||
EG_PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_mask = 0xffff << 0,
|
||||
EG_PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_shift = 16,
|
||||
EG_PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_mask = 0xffff << 16,
|
||||
/* SPI_BARYC_CNTL */
|
||||
EG_SPI_BARYC_CNTL__PERSP_CENTROID_ENA_shift = 4,
|
||||
EG_SPI_BARYC_CNTL__PERSP_CENTROID_ENA_mask = 0x3 << 4,
|
||||
EG_SPI_BARYC_CNTL__LINEAR_CENTROID_ENA_shift = 20,
|
||||
EG_SPI_BARYC_CNTL__LINEAR_CENTROID_ENA_mask = 0x3 << 20,
|
||||
/* DB_SHADER_CONTROL */
|
||||
EG_DB_SHADER_CONTROL__DUAL_EXPORT_ENABLE_bit = 1 << 9,
|
||||
|
||||
/* DB_Z_INFO */
|
||||
EG_DB_Z_INFO__FORMAT_shift = 0, //2;
|
||||
EG_DB_Z_INFO__FORMAT_mask = 0x3,
|
||||
//2;
|
||||
EG_DB_Z_INFO__ARRAY_MODE_shift = 4, //4;
|
||||
EG_DB_Z_INFO__ARRAY_MODE_mask = 0xf << 4,
|
||||
EG_DB_Z_INFO__TILE_SPLIT_shift = 8, //3;
|
||||
EG_DB_Z_INFO__TILE_SPLIT_mask = 0x7 << 8,
|
||||
//1;
|
||||
EG_DB_Z_INFO__NUM_BANKS_shift = 12, //2;
|
||||
EG_DB_Z_INFO__NUM_BANKS_mask = 0x3 << 12,
|
||||
//2;
|
||||
EG_DB_Z_INFO__BANK_WIDTH_shift = 16, //2;
|
||||
EG_DB_Z_INFO__BANK_WIDTH_mask = 0x3 << 16,
|
||||
//2;
|
||||
EG_DB_Z_INFO__BANK_HEIGHT_shift = 20, //2;
|
||||
EG_DB_Z_INFO__BANK_HEIGHT_mask = 0x3 << 20,
|
||||
|
||||
EG_Z_INVALID = 0x00000000,
|
||||
EG_Z_16 = 0x00000001,
|
||||
EG_Z_24 = 0x00000002,
|
||||
EG_Z_32_FLOAT = 0x00000003,
|
||||
EG_ADDR_SURF_TILE_SPLIT_256B = 0x00000002,
|
||||
EG_ADDR_SURF_8_BANK = 0x00000002,
|
||||
EG_ADDR_SURF_BANK_WIDTH_1 = 0x00000000,
|
||||
EG_ADDR_SURF_BANK_HEIGHT_1 = 0x00000000,
|
||||
/* DB_STENCIL_INFO */
|
||||
EG_DB_STENCIL_INFO__FORMAT_bit = 1, //1;
|
||||
//7;
|
||||
EG_DB_STENCIL_INFO__TILE_SPLIT_shift = 8, //3;
|
||||
EG_DB_STENCIL_INFO__TILE_SPLIT_mask = 0x7 << 8,
|
||||
|
||||
/* DB_DEPTH_SIZE */
|
||||
EG_DB_DEPTH_SIZE__PITCH_TILE_MAX_shift = 0, // 11;
|
||||
EG_DB_DEPTH_SIZE__PITCH_TILE_MAX_mask = 0x7ff,
|
||||
EG_DB_DEPTH_SIZE__HEIGHT_TILE_MAX_shift = 11, // 11;
|
||||
EG_DB_DEPTH_SIZE__HEIGHT_TILE_MAX_mask = 0x7ff << 11,
|
||||
|
||||
/* DB_COUNT_CONTROL */
|
||||
EG_DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_shift = 0, //1
|
||||
EG_DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_bit = 1,
|
||||
EG_DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_shift = 1, //1
|
||||
EG_DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_bit = 1 << 1,
|
||||
|
||||
/* CB_COLOR_CONTROL */
|
||||
//3;
|
||||
EG_CB_COLOR_CONTROL__DEGAMMA_ENABLE_bit = 1 << 3,//1;
|
||||
EG_CB_COLOR_CONTROL__MODE_shift = 4, //3;
|
||||
EG_CB_COLOR_CONTROL__MODE_mask = 0x7 << 4,
|
||||
//9;
|
||||
EG_CB_COLOR_CONTROL__ROP3_shift = 16, //8;
|
||||
EG_CB_COLOR_CONTROL__ROP3_mask = 0xff << 16,
|
||||
EG_CB_NORMAL = 0x00000001,
|
||||
|
||||
/* CB_COLOR0_INFO */
|
||||
EG_CB_COLOR0_INFO__ENDIAN_shift = 0, //2;
|
||||
EG_CB_COLOR0_INFO__ENDIAN_mask = 0x3,
|
||||
EG_CB_COLOR0_INFO__FORMAT_shift = 2, //6;
|
||||
EG_CB_COLOR0_INFO__FORMAT_mask = 0x3f << 2,
|
||||
EG_CB_COLOR0_INFO__ARRAY_MODE_shift = 8, //4;
|
||||
EG_CB_COLOR0_INFO__ARRAY_MODE_mask = 0xf << 8,
|
||||
EG_CB_COLOR0_INFO__NUMBER_TYPE_shift = 12, //3;
|
||||
EG_CB_COLOR0_INFO__NUMBER_TYPE_mask = 0x7 << 12,
|
||||
EG_CB_COLOR0_INFO__COMP_SWAP_shift = 15, //2;
|
||||
EG_CB_COLOR0_INFO__COMP_SWAP_mask = 0x3 << 15,
|
||||
EG_CB_COLOR0_INFO__FAST_CLEAR_bit = 1 << 17,//1;
|
||||
EG_CB_COLOR0_INFO__COMPRESSION_bit = 1 << 18,//1;
|
||||
EG_CB_COLOR0_INFO__BLEND_CLAMP_bit = 1 << 19,//1;
|
||||
EG_CB_COLOR0_INFO__BLEND_BYPASS_bit = 1 << 20,//1;
|
||||
EG_CB_COLOR0_INFO__SIMPLE_FLOAT_bit = 1 << 21,//1;
|
||||
EG_CB_COLOR0_INFO__ROUND_MODE_bit = 1 << 22,//1;
|
||||
EG_CB_COLOR0_INFO__TILE_COMPACT_bit = 1 << 23,//1;
|
||||
EG_CB_COLOR0_INFO__SOURCE_FORMAT_shift = 24, //2;
|
||||
EG_CB_COLOR0_INFO__SOURCE_FORMAT_mask = 0x3 << 24,
|
||||
EG_CB_COLOR0_INFO__RAT_bit = 1 << 26,//1;
|
||||
EG_CB_COLOR0_INFO__RESOURCE_TYPE_shift = 27, //3;
|
||||
EG_CB_COLOR0_INFO__RESOURCE_TYPE_mask = 0x7 << 27,
|
||||
|
||||
/* CB_COLOR0_ATTRIB */
|
||||
EG_CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_shift = 4,
|
||||
EG_CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_bit = 1 << 4,
|
||||
|
||||
/* SPI_CONFIG_CNTL_1 */
|
||||
EG_SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_shift = 0,
|
||||
EG_SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_mask = 0xf,
|
||||
/* SQ_MS_FIFO_SIZES */
|
||||
EG_SQ_MS_FIFO_SIZES__CACHE_FIFO_SIZE_shift = 0,
|
||||
EG_SQ_MS_FIFO_SIZES__CACHE_FIFO_SIZE_mask = 0xff,
|
||||
EG_SQ_MS_FIFO_SIZES__FETCH_FIFO_HIWATER_shift = 8,
|
||||
EG_SQ_MS_FIFO_SIZES__FETCH_FIFO_HIWATER_mask = 0x1f << 8,
|
||||
EG_SQ_MS_FIFO_SIZES__DONE_FIFO_HIWATER_shift = 16,
|
||||
EG_SQ_MS_FIFO_SIZES__DONE_FIFO_HIWATER_mask = 0xff << 16,
|
||||
EG_SQ_MS_FIFO_SIZES__ALU_UPDATE_FIFO_HIWATER_shift = 24,
|
||||
EG_SQ_MS_FIFO_SIZES__ALU_UPDATE_FIFO_HIWATER_mask = 0x1f << 24,
|
||||
/* SQ_CONFIG */
|
||||
EG_SQ_CONFIG__VC_ENABLE_bit = 1,
|
||||
EG_SQ_CONFIG__EXPORT_SRC_C_bit = 1 << 1,
|
||||
EG_SQ_CONFIG__PS_PRIO_shift = 24,
|
||||
EG_SQ_CONFIG__PS_PRIO_mask = 0x3 << 24,
|
||||
EG_SQ_CONFIG__VS_PRIO_shift = 26,
|
||||
EG_SQ_CONFIG__VS_PRIO_mask = 0x3 << 26,
|
||||
EG_SQ_CONFIG__GS_PRIO_shift = 28,
|
||||
EG_SQ_CONFIG__GS_PRIO_mask = 0x3 << 28,
|
||||
EG_SQ_CONFIG__ES_PRIO_shift = 30,
|
||||
EG_SQ_CONFIG__ES_PRIO_mask = 0x3 << 30,
|
||||
/* PA_SC_FORCE_EOV_MAX_CNTS */
|
||||
EG_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_shift = 0,
|
||||
EG_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_mask = 0x3fff,
|
||||
EG_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_shift = 16,
|
||||
EG_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_mask = 0x3fff << 16,
|
||||
/* VGT_CACHE_INVALIDATION */
|
||||
EG_VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_shift = 0,
|
||||
EG_VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_mask = 0x3,
|
||||
/* CB_COLOR0_PITCH */
|
||||
EG_CB_COLOR0_PITCH__TILE_MAX_shift = 0,
|
||||
EG_CB_COLOR0_PITCH__TILE_MAX_mask = 0x7ff,
|
||||
/* CB_COLOR0_SLICE */
|
||||
EG_CB_COLOR0_SLICE__TILE_MAX_shift = 0,
|
||||
EG_CB_COLOR0_SLICE__TILE_MAX_mask = 0x3fffff,
|
||||
/* SQ_VTX_CONSTANT_WORD3_0 */
|
||||
EG_SQ_VTX_CONSTANT_WORD3_0__UNCACHED_shift = 2,
|
||||
EG_SQ_VTX_CONSTANT_WORD3_0__UNCACHED_bit = 1 << 2,
|
||||
|
||||
EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_shift = 3,
|
||||
EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_mask = 0x7 << 3,
|
||||
|
||||
EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_shift = 6,
|
||||
EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_mask = 0x7 << 6,
|
||||
|
||||
EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_shift = 9,
|
||||
EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_mask = 0x7 << 9,
|
||||
|
||||
EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_shift = 12,
|
||||
EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_mask = 0x7 << 12,
|
||||
/* SQ_VTX_CONSTANT_WORD4_0 */
|
||||
EG_SQ_VTX_CONSTANT_WORD4_0__NUM_ELEMENTS_shift = 0,
|
||||
EG_SQ_VTX_CONSTANT_WORD4_0__NUM_ELEMENTS_mask = 0xFFFFFFFF,
|
||||
/* SQ_VTX_CONSTANT_WORD7_0 */
|
||||
EG_SQ_VTX_CONSTANT_WORD7_0__TYPE_shift = 30,
|
||||
EG_SQ_VTX_CONSTANT_WORD7_0__TYPE_mask = 0x3 << 30,
|
||||
/* SQ_TEX_SAMPLER_WORD0_0 */
|
||||
EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift = 0, // 3;
|
||||
EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_mask = 0x7,
|
||||
EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_Y_shift = 3, // 3;
|
||||
EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_Y_mask = 0x7 << 3,
|
||||
EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_Z_shift = 6, // 3;
|
||||
EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_Z_mask = 0x7 << 6,
|
||||
EG_SQ_TEX_SAMPLER_WORD0_0__XY_MAG_FILTER_shift = 9, // 2;
|
||||
EG_SQ_TEX_SAMPLER_WORD0_0__XY_MAG_FILTER_mask = 0x3 << 9,
|
||||
EG_SQ_TEX_SAMPLER_WORD0_0__XY_MIN_FILTER_shift = 11, // 2;
|
||||
EG_SQ_TEX_SAMPLER_WORD0_0__XY_MIN_FILTER_mask = 0x3 << 11,
|
||||
EG_SQ_TEX_SAMPLER_WORD0_0__Z_FILTER_shift = 13, // 2;
|
||||
EG_SQ_TEX_SAMPLER_WORD0_0__Z_FILTER_mask = 0x3 << 13,
|
||||
EG_SQ_TEX_SAMPLER_WORD0_0__MIP_FILTER_shift = 15, // 2;
|
||||
EG_SQ_TEX_SAMPLER_WORD0_0__MIP_FILTER_mask = 0x3 << 15,
|
||||
EG_SQ_TEX_SAMPLER_WORD0_0__MAX_ANISO_RATIO_shift = 17, // 3;
|
||||
EG_SQ_TEX_SAMPLER_WORD0_0__MAX_ANISO_RATIO_mask = 0x7 << 17,
|
||||
EG_SQ_TEX_SAMPLER_WORD0_0__BORDER_COLOR_TYPE_shift = 20,//2;
|
||||
EG_SQ_TEX_SAMPLER_WORD0_0__BORDER_COLOR_TYPE_mask = 0x3 << 20,
|
||||
EG_SQ_TEX_SAMPLER_WORD0_0__DCF_shift = 22, // 3;
|
||||
EG_SQ_TEX_SAMPLER_WORD0_0__DCF_mask = 0x7 << 22,
|
||||
EG_SQ_TEX_SAMPLER_WORD0_0__CHROMA_KEY_shift = 25, // 2;
|
||||
EG_SQ_TEX_SAMPLER_WORD0_0__CHROMA_KEY_mask = 0x3 << 25,
|
||||
EG_SQ_TEX_SAMPLER_WORD0_0__ANISO_THRESHOLD_shift = 27, // 3;
|
||||
EG_SQ_TEX_SAMPLER_WORD0_0__ANISO_THRESHOLD_mask = 0x7 << 27,
|
||||
EG_SQ_TEX_SAMPLER_WORD0_0__Reserved_shift = 30, // 2
|
||||
EG_SQ_TEX_SAMPLER_WORD0_0__Reserved_mask = 0x3 << 30,
|
||||
/* SQ_TEX_SAMPLER_WORD1_0 */
|
||||
EG_SQ_TEX_SAMPLER_WORD1_0__MIN_LOD_shift = 0, // 12;
|
||||
EG_SQ_TEX_SAMPLER_WORD1_0__MIN_LOD_mask = 0xfff,
|
||||
EG_SQ_TEX_SAMPLER_WORD1_0__MAX_LOD_shift = 12,// 12;
|
||||
EG_SQ_TEX_SAMPLER_WORD1_0__MAX_LOD_mask = 0xfff << 12,
|
||||
/* SQ_TEX_SAMPLER_WORD2_0 */
|
||||
EG_SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_shift = 0, //14;
|
||||
EG_SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_mask = 0x3fff,
|
||||
EG_SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_SEC_shift = 14,//6;
|
||||
EG_SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_SEC_mask = 0x3f << 14,
|
||||
EG_SQ_TEX_SAMPLER_WORD2_0__MC_COORD_TRUNCATE_shift = 20,//1;
|
||||
EG_SQ_TEX_SAMPLER_WORD2_0__MC_COORD_TRUNCATE_bit = 1 << 20,
|
||||
EG_SQ_TEX_SAMPLER_WORD2_0__FORCE_DEGAMMA_shift = 21,//1;
|
||||
EG_SQ_TEX_SAMPLER_WORD2_0__FORCE_DEGAMMA_bit = 1 << 21,
|
||||
EG_SQ_TEX_SAMPLER_WORD2_0__ANISO_BIAS_shift = 22,//6;
|
||||
EG_SQ_TEX_SAMPLER_WORD2_0__ANISO_BIAS_mask = 0x3f << 22,
|
||||
EG_SQ_TEX_SAMPLER_WORD2_0__TRUNCATE_COORD_shift = 28,//1;
|
||||
EG_SQ_TEX_SAMPLER_WORD2_0__TRUNCATE_COORD_bit = 1 << 28,
|
||||
EG_SQ_TEX_SAMPLER_WORD2_0__DISABLE_CUBE_WRAP_shift = 29,//1;
|
||||
EG_SQ_TEX_SAMPLER_WORD2_0__DISABLE_CUBE_WRAP_bit = 1 << 29,
|
||||
EG_SQ_TEX_SAMPLER_WORD2_0__Reserved_shift = 30,//1;
|
||||
EG_SQ_TEX_SAMPLER_WORD2_0__Reserved_bit = 1 << 30,
|
||||
EG_SQ_TEX_SAMPLER_WORD2_0__TYPE_shift = 31,//1;
|
||||
EG_SQ_TEX_SAMPLER_WORD2_0__TYPE_bit = 1 << 31,
|
||||
/* SQ_TEX_RESOURCE_WORD0_0 */
|
||||
EG_SQ_TEX_RESOURCE_WORD0_0__DIM_shift = 0, // 3;
|
||||
EG_SQ_TEX_RESOURCE_WORD0_0__DIM_mask = 0x7,
|
||||
EG_SQ_TEX_RESOURCE_WORD0_0__ISET_shift = 3, // 1;
|
||||
EG_SQ_TEX_RESOURCE_WORD0_0__ISET_bit = 1 << 3,
|
||||
EG_SQ_TEX_RESOURCE_WORD0_0__Reserve_shift = 4, // 1;
|
||||
EG_SQ_TEX_RESOURCE_WORD0_0__Reserve_bit = 1 << 4,
|
||||
EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_shift = 5, // 1;
|
||||
EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit = 1 << 5,
|
||||
EG_SQ_TEX_RESOURCE_WORD0_0__PITCH_shift = 6, // 12;
|
||||
EG_SQ_TEX_RESOURCE_WORD0_0__PITCH_mask = 0xfff << 6,
|
||||
EG_SQ_TEX_RESOURCE_WORD0_0__TEX_WIDTH_shift = 18,// 14;
|
||||
EG_SQ_TEX_RESOURCE_WORD0_0__TEX_WIDTH_mask = 0x3fff << 18,
|
||||
/* SQ_TEX_RESOURCE_WORD1_0 */
|
||||
EG_SQ_TEX_RESOURCE_WORD1_0__TEX_HEIGHT_shift = 0, // 14;
|
||||
EG_SQ_TEX_RESOURCE_WORD1_0__TEX_HEIGHT_mask = 0x3fff,
|
||||
EG_SQ_TEX_RESOURCE_WORD1_0__TEX_DEPTH_shift = 14,// 13;
|
||||
EG_SQ_TEX_RESOURCE_WORD1_0__TEX_DEPTH_mask = 0x1fff << 14,
|
||||
EG_SQ_TEX_RESOURCE_WORD1_0__Reserved_shift = 27,// 1;
|
||||
EG_SQ_TEX_RESOURCE_WORD1_0__Reserved_bit = 1 << 27,
|
||||
EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift = 28,// 4;
|
||||
EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask = 0xf << 28,
|
||||
/* SQ_TEX_RESOURCE_WORD6_0 */
|
||||
EG_SQ_TEX_RESOURCE_WORD6_0__MAX_ANISO_RATIO_shift = 0, //: 3;
|
||||
EG_SQ_TEX_RESOURCE_WORD6_0__MAX_ANISO_RATIO_mask = 0x7,
|
||||
EG_SQ_TEX_RESOURCE_WORD6_0__INTERLACED_shift = 6, //1;
|
||||
EG_SQ_TEX_RESOURCE_WORD6_0__INTERLACED_bit = 1 << 6,
|
||||
EG_SQ_TEX_RESOURCE_WORD6_0__MIN_LOD_shift = 8, //12;
|
||||
EG_SQ_TEX_RESOURCE_WORD6_0__MIN_LOD_mask = 0xfff << 8,
|
||||
EG_SQ_TEX_RESOURCE_WORD6_0__TILE_SPLIT_shift = 29,// 3;
|
||||
EG_SQ_TEX_RESOURCE_WORD6_0__TILE_SPLIT_mask = 0x7 << 29,
|
||||
/* SQ_TEX_RESOURCE_WORD7_0 */
|
||||
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift = 0, // 6;
|
||||
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask = 0x3f,
|
||||
EG_SQ_TEX_RESOURCE_WORD7_0__MACRO_TILE_ASPECT_shift = 6, // 2;
|
||||
EG_SQ_TEX_RESOURCE_WORD7_0__MACRO_TILE_ASPECT_mask = 0x3 << 6,
|
||||
EG_SQ_TEX_RESOURCE_WORD7_0__BANK_WIDTH_shift = 8, // 2;
|
||||
EG_SQ_TEX_RESOURCE_WORD7_0__BANK_WIDTH_mask = 0x3 << 8,
|
||||
EG_SQ_TEX_RESOURCE_WORD7_0__BANK_HEIGHT_shift = 10,// 2;
|
||||
EG_SQ_TEX_RESOURCE_WORD7_0__BANK_HEIGHT_mask = 0x3 << 10,
|
||||
EG_SQ_TEX_RESOURCE_WORD7_0__DEPTH_SAMPLE_ORDER_shift = 15,// 1;
|
||||
EG_SQ_TEX_RESOURCE_WORD7_0__DEPTH_SAMPLE_ORDER_bit = 1 << 15,
|
||||
EG_SQ_TEX_RESOURCE_WORD7_0__NUM_BANKS_shift = 16,// 2;
|
||||
EG_SQ_TEX_RESOURCE_WORD7_0__NUM_BANKS_mask = 0x3 << 16,
|
||||
EG_SQ_TEX_RESOURCE_WORD7_0__TYPE_shift = 30,// 2;
|
||||
EG_SQ_TEX_RESOURCE_WORD7_0__TYPE_mask = 0x3 << 30,
|
||||
};
|
||||
|
||||
/* */
|
||||
|
||||
#define EG_SQ_FETCH_RESOURCE_COUNT 0x00000400
|
||||
#define EG_SQ_TEX_SAMPLER_COUNT 0x0000006c
|
||||
#define EG_SQ_LOOP_CONST_COUNT 0x000000c0
|
||||
|
||||
#define EG_SET_RESOURCE_OFFSET 0x30000
|
||||
#define EG_SET_RESOURCE_END 0x30400 //r600 := offset + 0x4000
|
||||
|
||||
#define EG_SET_LOOP_CONST_OFFSET 0x3A200
|
||||
#define EG_SET_LOOP_CONST_END 0x3A26C //r600 := offset + 0x180
|
||||
|
||||
|
||||
#define EG_SQ_FETCH_RESOURCE_VS_OFFSET 0x000000b0
|
||||
#define EG_FETCH_RESOURCE_STRIDE 8
|
||||
|
||||
#define EG_SET_BOOL_CONST_OFFSET 0x3A500
|
||||
#define EG_SET_BOOL_CONST_END 0x3A506
|
||||
|
||||
|
||||
#endif //_EVERGREEN_DIFF_H_
|
||||
|
|
@ -0,0 +1,808 @@
|
|||
/*
|
||||
* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Authors:
|
||||
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
|
||||
* CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdarg.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
|
||||
#include "main/imports.h"
|
||||
|
||||
#include "program/prog_parameter.h"
|
||||
#include "program/prog_statevars.h"
|
||||
#include "program/program.h"
|
||||
|
||||
#include "r600_context.h"
|
||||
#include "r600_cmdbuf.h"
|
||||
|
||||
#include "evergreen_vertprog.h"
|
||||
#include "evergreen_fragprog.h"
|
||||
|
||||
#include "r700_debug.h"
|
||||
|
||||
void evergreen_insert_wpos_code(GLcontext *ctx, struct gl_fragment_program *fprog)
|
||||
{
|
||||
static const gl_state_index winstate[STATE_LENGTH]
|
||||
= { STATE_INTERNAL, STATE_FB_SIZE, 0, 0, 0};
|
||||
struct prog_instruction *newInst, *inst;
|
||||
GLint win_size; /* state reference */
|
||||
GLuint wpos_temp; /* temp register */
|
||||
int i, j;
|
||||
|
||||
/* PARAM win_size = STATE_FB_SIZE */
|
||||
win_size = _mesa_add_state_reference(fprog->Base.Parameters, winstate);
|
||||
|
||||
wpos_temp = fprog->Base.NumTemporaries++;
|
||||
|
||||
/* scan program where WPOS is used and replace with wpos_temp */
|
||||
inst = fprog->Base.Instructions;
|
||||
for (i = 0; i < fprog->Base.NumInstructions; i++) {
|
||||
for (j=0; j < 3; j++) {
|
||||
if(inst->SrcReg[j].File == PROGRAM_INPUT &&
|
||||
inst->SrcReg[j].Index == FRAG_ATTRIB_WPOS) {
|
||||
inst->SrcReg[j].File = PROGRAM_TEMPORARY;
|
||||
inst->SrcReg[j].Index = wpos_temp;
|
||||
}
|
||||
}
|
||||
inst++;
|
||||
}
|
||||
|
||||
_mesa_insert_instructions(&(fprog->Base), 0, 1);
|
||||
|
||||
newInst = fprog->Base.Instructions;
|
||||
/* invert wpos.y
|
||||
* wpos_temp.xyzw = wpos.x-yzw + winsize.0y00 */
|
||||
newInst[0].Opcode = OPCODE_ADD;
|
||||
newInst[0].DstReg.File = PROGRAM_TEMPORARY;
|
||||
newInst[0].DstReg.Index = wpos_temp;
|
||||
newInst[0].DstReg.WriteMask = WRITEMASK_XYZW;
|
||||
|
||||
newInst[0].SrcReg[0].File = PROGRAM_INPUT;
|
||||
newInst[0].SrcReg[0].Index = FRAG_ATTRIB_WPOS;
|
||||
newInst[0].SrcReg[0].Swizzle = SWIZZLE_XYZW;
|
||||
newInst[0].SrcReg[0].Negate = NEGATE_Y;
|
||||
|
||||
newInst[0].SrcReg[1].File = PROGRAM_STATE_VAR;
|
||||
newInst[0].SrcReg[1].Index = win_size;
|
||||
newInst[0].SrcReg[1].Swizzle = MAKE_SWIZZLE4(SWIZZLE_ZERO, SWIZZLE_Y, SWIZZLE_ZERO, SWIZZLE_ZERO);
|
||||
|
||||
}
|
||||
|
||||
//TODO : Validate FP input with VP output.
|
||||
void evergreen_Map_Fragment_Program(r700_AssemblerBase *pAsm,
|
||||
struct gl_fragment_program *mesa_fp,
|
||||
GLcontext *ctx)
|
||||
{
|
||||
unsigned int unBit;
|
||||
unsigned int i;
|
||||
GLuint ui;
|
||||
|
||||
/* match fp inputs with vp exports. */
|
||||
struct evergreen_vertex_program_cont *vpc =
|
||||
(struct evergreen_vertex_program_cont *)ctx->VertexProgram._Current;
|
||||
GLbitfield OutputsWritten = vpc->mesa_program.Base.OutputsWritten;
|
||||
|
||||
pAsm->number_used_registers = 0;
|
||||
|
||||
//Input mapping : mesa_fp->Base.InputsRead set the flag, set in
|
||||
//The flags parsed in parse_attrib_binding. FRAG_ATTRIB_COLx, FRAG_ATTRIB_TEXx, ...
|
||||
//MUST match order in Map_Vertex_Output
|
||||
unBit = 1 << FRAG_ATTRIB_WPOS;
|
||||
if(mesa_fp->Base.InputsRead & unBit)
|
||||
{
|
||||
pAsm->uiFP_AttributeMap[FRAG_ATTRIB_WPOS] = pAsm->number_used_registers++;
|
||||
}
|
||||
|
||||
unBit = 1 << VERT_RESULT_COL0;
|
||||
if(OutputsWritten & unBit)
|
||||
{
|
||||
pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL0] = pAsm->number_used_registers++;
|
||||
}
|
||||
|
||||
unBit = 1 << VERT_RESULT_COL1;
|
||||
if(OutputsWritten & unBit)
|
||||
{
|
||||
pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL1] = pAsm->number_used_registers++;
|
||||
}
|
||||
|
||||
unBit = 1 << VERT_RESULT_FOGC;
|
||||
if(OutputsWritten & unBit)
|
||||
{
|
||||
pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FOGC] = pAsm->number_used_registers++;
|
||||
}
|
||||
|
||||
for(i=0; i<8; i++)
|
||||
{
|
||||
unBit = 1 << (VERT_RESULT_TEX0 + i);
|
||||
if(OutputsWritten & unBit)
|
||||
{
|
||||
pAsm->uiFP_AttributeMap[FRAG_ATTRIB_TEX0 + i] = pAsm->number_used_registers++;
|
||||
}
|
||||
}
|
||||
|
||||
/* order has been taken care of */
|
||||
#if 1
|
||||
for(i=VERT_RESULT_VAR0; i<VERT_RESULT_MAX; i++)
|
||||
{
|
||||
unBit = 1 << i;
|
||||
if(OutputsWritten & unBit)
|
||||
{
|
||||
pAsm->uiFP_AttributeMap[i-VERT_RESULT_VAR0+FRAG_ATTRIB_VAR0] = pAsm->number_used_registers++;
|
||||
}
|
||||
}
|
||||
#else
|
||||
if( (mesa_fp->Base.InputsRead >> FRAG_ATTRIB_VAR0) > 0 )
|
||||
{
|
||||
struct evergreen_vertex_program_cont *vpc =
|
||||
(struct evergreen_vertex_program_cont *)ctx->VertexProgram._Current;
|
||||
struct gl_program_parameter_list * VsVarying = vpc->mesa_program.Base.Varying;
|
||||
struct gl_program_parameter_list * PsVarying = mesa_fp->Base.Varying;
|
||||
struct gl_program_parameter * pVsParam;
|
||||
struct gl_program_parameter * pPsParam;
|
||||
GLuint j, k;
|
||||
GLuint unMaxVarying = 0;
|
||||
|
||||
for(i=0; i<VsVarying->NumParameters; i++)
|
||||
{
|
||||
pAsm->uiFP_AttributeMap[i + FRAG_ATTRIB_VAR0] = 0;
|
||||
}
|
||||
|
||||
for(i=FRAG_ATTRIB_VAR0; i<FRAG_ATTRIB_MAX; i++)
|
||||
{
|
||||
unBit = 1 << i;
|
||||
if(mesa_fp->Base.InputsRead & unBit)
|
||||
{
|
||||
j = i - FRAG_ATTRIB_VAR0;
|
||||
pPsParam = PsVarying->Parameters + j;
|
||||
|
||||
for(k=0; k<VsVarying->NumParameters; k++)
|
||||
{
|
||||
pVsParam = VsVarying->Parameters + k;
|
||||
|
||||
if( strcmp(pPsParam->Name, pVsParam->Name) == 0)
|
||||
{
|
||||
pAsm->uiFP_AttributeMap[i] = pAsm->number_used_registers + k;
|
||||
if(k > unMaxVarying)
|
||||
{
|
||||
unMaxVarying = k;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pAsm->number_used_registers += unMaxVarying + 1;
|
||||
}
|
||||
#endif
|
||||
unBit = 1 << FRAG_ATTRIB_FACE;
|
||||
if(mesa_fp->Base.InputsRead & unBit)
|
||||
{
|
||||
pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FACE] = pAsm->number_used_registers++;
|
||||
}
|
||||
|
||||
unBit = 1 << FRAG_ATTRIB_PNTC;
|
||||
if(mesa_fp->Base.InputsRead & unBit)
|
||||
{
|
||||
pAsm->uiFP_AttributeMap[FRAG_ATTRIB_PNTC] = pAsm->number_used_registers++;
|
||||
}
|
||||
|
||||
pAsm->uIIns = pAsm->number_used_registers;
|
||||
|
||||
/* Map temporary registers (GPRs) */
|
||||
pAsm->starting_temp_register_number = pAsm->number_used_registers;
|
||||
|
||||
if(mesa_fp->Base.NumNativeTemporaries >= mesa_fp->Base.NumTemporaries)
|
||||
{
|
||||
pAsm->number_used_registers += mesa_fp->Base.NumNativeTemporaries;
|
||||
}
|
||||
else
|
||||
{
|
||||
pAsm->number_used_registers += mesa_fp->Base.NumTemporaries;
|
||||
}
|
||||
|
||||
/* Output mapping */
|
||||
pAsm->number_of_exports = 0;
|
||||
pAsm->number_of_colorandz_exports = 0; /* don't include stencil and mask out. */
|
||||
pAsm->starting_export_register_number = pAsm->number_used_registers;
|
||||
unBit = 1 << FRAG_RESULT_COLOR;
|
||||
if(mesa_fp->Base.OutputsWritten & unBit)
|
||||
{
|
||||
pAsm->uiFP_OutputMap[FRAG_RESULT_COLOR] = pAsm->number_used_registers++;
|
||||
pAsm->number_of_exports++;
|
||||
pAsm->number_of_colorandz_exports++;
|
||||
}
|
||||
unBit = 1 << FRAG_RESULT_DEPTH;
|
||||
if(mesa_fp->Base.OutputsWritten & unBit)
|
||||
{
|
||||
pAsm->depth_export_register_number = pAsm->number_used_registers;
|
||||
pAsm->uiFP_OutputMap[FRAG_RESULT_DEPTH] = pAsm->number_used_registers++;
|
||||
pAsm->number_of_exports++;
|
||||
pAsm->number_of_colorandz_exports++;
|
||||
pAsm->pR700Shader->depthIsExported = 1;
|
||||
}
|
||||
|
||||
pAsm->pucOutMask = (unsigned char*) MALLOC(pAsm->number_of_exports);
|
||||
for(ui=0; ui<pAsm->number_of_exports; ui++)
|
||||
{
|
||||
pAsm->pucOutMask[ui] = 0x0;
|
||||
}
|
||||
|
||||
pAsm->flag_reg_index = pAsm->number_used_registers++;
|
||||
|
||||
pAsm->uFirstHelpReg = pAsm->number_used_registers;
|
||||
}
|
||||
|
||||
GLboolean evergreen_Find_Instruction_Dependencies_fp(struct evergreen_fragment_program *fp,
|
||||
struct gl_fragment_program *mesa_fp)
|
||||
{
|
||||
GLuint i, j;
|
||||
GLint * puiTEMPwrites;
|
||||
GLint * puiTEMPreads;
|
||||
struct prog_instruction * pILInst;
|
||||
InstDeps *pInstDeps;
|
||||
struct prog_instruction * texcoord_DepInst;
|
||||
GLint nDepInstID;
|
||||
|
||||
puiTEMPwrites = (GLint*) MALLOC(sizeof(GLuint)*mesa_fp->Base.NumTemporaries);
|
||||
puiTEMPreads = (GLint*) MALLOC(sizeof(GLuint)*mesa_fp->Base.NumTemporaries);
|
||||
|
||||
for(i=0; i<mesa_fp->Base.NumTemporaries; i++)
|
||||
{
|
||||
puiTEMPwrites[i] = -1;
|
||||
puiTEMPreads[i] = -1;
|
||||
}
|
||||
|
||||
pInstDeps = (InstDeps*)MALLOC(sizeof(InstDeps)*mesa_fp->Base.NumInstructions);
|
||||
|
||||
for(i=0; i<mesa_fp->Base.NumInstructions; i++)
|
||||
{
|
||||
pInstDeps[i].nDstDep = -1;
|
||||
pILInst = &(mesa_fp->Base.Instructions[i]);
|
||||
|
||||
//Dst
|
||||
if(pILInst->DstReg.File == PROGRAM_TEMPORARY)
|
||||
{
|
||||
//Set lastwrite for the temp
|
||||
puiTEMPwrites[pILInst->DstReg.Index] = i;
|
||||
}
|
||||
|
||||
//Src
|
||||
for(j=0; j<3; j++)
|
||||
{
|
||||
if(pILInst->SrcReg[j].File == PROGRAM_TEMPORARY)
|
||||
{
|
||||
//Set dep.
|
||||
pInstDeps[i].nSrcDeps[j] = puiTEMPwrites[pILInst->SrcReg[j].Index];
|
||||
//Set first read
|
||||
if(puiTEMPreads[pILInst->SrcReg[j].Index] < 0 )
|
||||
{
|
||||
puiTEMPreads[pILInst->SrcReg[j].Index] = i;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
pInstDeps[i].nSrcDeps[j] = -1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fp->r700AsmCode.pInstDeps = pInstDeps;
|
||||
|
||||
//Find dep for tex inst
|
||||
for(i=0; i<mesa_fp->Base.NumInstructions; i++)
|
||||
{
|
||||
pILInst = &(mesa_fp->Base.Instructions[i]);
|
||||
|
||||
if(GL_TRUE == IsTex(pILInst->Opcode))
|
||||
{ //src0 is the tex coord register, src1 is texunit, src2 is textype
|
||||
nDepInstID = pInstDeps[i].nSrcDeps[0];
|
||||
if(nDepInstID >= 0)
|
||||
{
|
||||
texcoord_DepInst = &(mesa_fp->Base.Instructions[nDepInstID]);
|
||||
if(GL_TRUE == IsAlu(texcoord_DepInst->Opcode) )
|
||||
{
|
||||
pInstDeps[nDepInstID].nDstDep = i;
|
||||
pInstDeps[i].nDstDep = i;
|
||||
}
|
||||
else if(GL_TRUE == IsTex(texcoord_DepInst->Opcode) )
|
||||
{
|
||||
pInstDeps[i].nDstDep = i;
|
||||
}
|
||||
else
|
||||
{ //... other deps?
|
||||
}
|
||||
}
|
||||
// make sure that we dont overwrite src used earlier
|
||||
nDepInstID = puiTEMPreads[pILInst->DstReg.Index];
|
||||
if(nDepInstID < i)
|
||||
{
|
||||
pInstDeps[i].nDstDep = puiTEMPreads[pILInst->DstReg.Index];
|
||||
texcoord_DepInst = &(mesa_fp->Base.Instructions[nDepInstID]);
|
||||
if(GL_TRUE == IsAlu(texcoord_DepInst->Opcode) )
|
||||
{
|
||||
pInstDeps[nDepInstID].nDstDep = i;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
FREE(puiTEMPwrites);
|
||||
FREE(puiTEMPreads);
|
||||
|
||||
return GL_TRUE;
|
||||
}
|
||||
|
||||
GLboolean evergreenTranslateFragmentShader(struct evergreen_fragment_program *fp,
|
||||
struct gl_fragment_program *mesa_fp,
|
||||
GLcontext *ctx)
|
||||
{
|
||||
GLuint number_of_colors_exported;
|
||||
GLboolean z_enabled = GL_FALSE;
|
||||
GLuint unBit, shadow_unit;
|
||||
int i;
|
||||
struct prog_instruction *inst;
|
||||
gl_state_index shadow_ambient[STATE_LENGTH]
|
||||
= { STATE_INTERNAL, STATE_SHADOW_AMBIENT, 0, 0, 0};
|
||||
|
||||
//Init_Program
|
||||
Init_r700_AssemblerBase( SPT_FP, &(fp->r700AsmCode), &(fp->r700Shader) );
|
||||
|
||||
fp->constbo0 = NULL;
|
||||
fp->r700AsmCode.bUseMemConstant = GL_TRUE;
|
||||
fp->r700AsmCode.unAsic = 8;
|
||||
|
||||
if(mesa_fp->Base.InputsRead & FRAG_BIT_WPOS)
|
||||
{
|
||||
evergreen_insert_wpos_code(ctx, mesa_fp);
|
||||
}
|
||||
|
||||
/* add/map consts for ARB_shadow_ambient */
|
||||
if(mesa_fp->Base.ShadowSamplers)
|
||||
{
|
||||
inst = mesa_fp->Base.Instructions;
|
||||
for (i = 0; i < mesa_fp->Base.NumInstructions; i++)
|
||||
{
|
||||
if(inst->TexShadow == 1)
|
||||
{
|
||||
shadow_unit = inst->TexSrcUnit;
|
||||
shadow_ambient[2] = shadow_unit;
|
||||
fp->r700AsmCode.shadow_regs[shadow_unit] =
|
||||
_mesa_add_state_reference(mesa_fp->Base.Parameters, shadow_ambient);
|
||||
}
|
||||
inst++;
|
||||
}
|
||||
}
|
||||
|
||||
evergreen_Map_Fragment_Program(&(fp->r700AsmCode), mesa_fp, ctx);
|
||||
|
||||
if( GL_FALSE == evergreen_Find_Instruction_Dependencies_fp(fp, mesa_fp) )
|
||||
{
|
||||
return GL_FALSE;
|
||||
}
|
||||
|
||||
InitShaderProgram(&(fp->r700AsmCode));
|
||||
|
||||
for(i=0; i < MAX_SAMPLERS; i++)
|
||||
{
|
||||
fp->r700AsmCode.SamplerUnits[i] = fp->mesa_program.Base.SamplerUnits[i];
|
||||
}
|
||||
|
||||
fp->r700AsmCode.unCurNumILInsts = mesa_fp->Base.NumInstructions;
|
||||
|
||||
if( GL_FALSE == AssembleInstr(0,
|
||||
0,
|
||||
mesa_fp->Base.NumInstructions,
|
||||
&(mesa_fp->Base.Instructions[0]),
|
||||
&(fp->r700AsmCode)) )
|
||||
{
|
||||
return GL_FALSE;
|
||||
}
|
||||
|
||||
if(GL_FALSE == Process_Fragment_Exports(&(fp->r700AsmCode), mesa_fp->Base.OutputsWritten) )
|
||||
{
|
||||
return GL_FALSE;
|
||||
}
|
||||
|
||||
if( GL_FALSE == RelocProgram(&(fp->r700AsmCode), &(mesa_fp->Base)) )
|
||||
{
|
||||
return GL_FALSE;
|
||||
}
|
||||
|
||||
fp->r700Shader.nRegs = (fp->r700AsmCode.number_used_registers == 0) ? 0
|
||||
: (fp->r700AsmCode.number_used_registers - 1);
|
||||
|
||||
fp->r700Shader.nParamExports = fp->r700AsmCode.number_of_exports;
|
||||
|
||||
number_of_colors_exported = fp->r700AsmCode.number_of_colorandz_exports;
|
||||
|
||||
unBit = 1 << FRAG_RESULT_DEPTH;
|
||||
if(mesa_fp->Base.OutputsWritten & unBit)
|
||||
{
|
||||
z_enabled = GL_TRUE;
|
||||
number_of_colors_exported--;
|
||||
}
|
||||
|
||||
/* illegal to set this to 0 */
|
||||
if(number_of_colors_exported || z_enabled)
|
||||
{
|
||||
fp->r700Shader.exportMode = number_of_colors_exported << 1 | z_enabled;
|
||||
}
|
||||
else
|
||||
{
|
||||
fp->r700Shader.exportMode = (1 << 1);
|
||||
}
|
||||
|
||||
fp->translated = GL_TRUE;
|
||||
|
||||
return GL_TRUE;
|
||||
}
|
||||
|
||||
void evergreenSelectFragmentShader(GLcontext *ctx)
|
||||
{
|
||||
context_t *context = EVERGREEN_CONTEXT(ctx);
|
||||
struct evergreen_fragment_program *fp = (struct evergreen_fragment_program *)
|
||||
(ctx->FragmentProgram._Current);
|
||||
if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
|
||||
{
|
||||
fp->r700AsmCode.bR6xx = 1;
|
||||
}
|
||||
|
||||
if (GL_FALSE == fp->translated)
|
||||
evergreenTranslateFragmentShader(fp, &(fp->mesa_program), ctx);
|
||||
}
|
||||
|
||||
void * evergreenGetActiveFpShaderBo(GLcontext * ctx)
|
||||
{
|
||||
struct evergreen_fragment_program *fp = (struct evergreen_fragment_program *)
|
||||
(ctx->FragmentProgram._Current);
|
||||
|
||||
return fp->shaderbo;
|
||||
}
|
||||
|
||||
void * evergreenGetActiveFpShaderConstBo(GLcontext * ctx)
|
||||
{
|
||||
struct evergreen_fragment_program *fp = (struct evergreen_fragment_program *)
|
||||
(ctx->FragmentProgram._Current);
|
||||
|
||||
return fp->constbo0;
|
||||
}
|
||||
|
||||
GLboolean evergreenSetupFragmentProgram(GLcontext * ctx)
|
||||
{
|
||||
context_t *context = EVERGREEN_CONTEXT(ctx);
|
||||
EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
|
||||
struct evergreen_fragment_program *fp = (struct evergreen_fragment_program *)
|
||||
(ctx->FragmentProgram._Current);
|
||||
r700_AssemblerBase *pAsm = &(fp->r700AsmCode);
|
||||
struct gl_fragment_program *mesa_fp = &(fp->mesa_program);
|
||||
struct gl_program_parameter_list *paramList;
|
||||
unsigned int unNumParamData;
|
||||
unsigned int ui, i;
|
||||
unsigned int unNumOfReg;
|
||||
unsigned int unBit;
|
||||
GLuint exportCount;
|
||||
GLboolean point_sprite = GL_FALSE;
|
||||
|
||||
if(GL_FALSE == fp->loaded)
|
||||
{
|
||||
if(fp->r700Shader.bNeedsAssembly == GL_TRUE)
|
||||
{
|
||||
Assemble( &(fp->r700Shader) );
|
||||
}
|
||||
|
||||
r600EmitShader(ctx,
|
||||
&(fp->shaderbo),
|
||||
(GLvoid *)(fp->r700Shader.pProgram),
|
||||
fp->r700Shader.uShaderBinaryDWORDSize,
|
||||
"FS");
|
||||
|
||||
fp->loaded = GL_TRUE;
|
||||
}
|
||||
|
||||
/* TODO : enable this after MemUse fixed *=
|
||||
(context->chipobj.MemUse)(context, fp->shadercode.buf->id);
|
||||
*/
|
||||
|
||||
EVERGREEN_STATECHANGE(context, sq);
|
||||
|
||||
evergreen->SQ_PGM_RESOURCES_PS.u32All = 0;
|
||||
SETbit(evergreen->SQ_PGM_RESOURCES_PS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit);
|
||||
|
||||
evergreen->ps.SQ_ALU_CONST_CACHE_PS_0.u32All = 0;
|
||||
evergreen->ps.SQ_PGM_START_PS.u32All = 0;
|
||||
|
||||
EVERGREEN_STATECHANGE(context, spi);
|
||||
|
||||
unNumOfReg = fp->r700Shader.nRegs + 1;
|
||||
|
||||
ui = (evergreen->SPI_PS_IN_CONTROL_0.u32All & NUM_INTERP_mask) / (1 << NUM_INTERP_shift);
|
||||
|
||||
/* PS uses fragment.position */
|
||||
if (mesa_fp->Base.InputsRead & (1 << FRAG_ATTRIB_WPOS))
|
||||
{
|
||||
ui += 1;
|
||||
SETfield(evergreen->SPI_PS_IN_CONTROL_0.u32All, ui, NUM_INTERP_shift, NUM_INTERP_mask);
|
||||
SETfield(evergreen->SPI_PS_IN_CONTROL_0.u32All, CENTERS_ONLY, BARYC_SAMPLE_CNTL_shift, BARYC_SAMPLE_CNTL_mask);
|
||||
SETbit(evergreen->SPI_PS_IN_CONTROL_0.u32All, POSITION_ENA_bit);
|
||||
SETbit(evergreen->SPI_INPUT_Z.u32All, PROVIDE_Z_TO_SPI_bit);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLEARbit(evergreen->SPI_PS_IN_CONTROL_0.u32All, POSITION_ENA_bit);
|
||||
CLEARbit(evergreen->SPI_INPUT_Z.u32All, PROVIDE_Z_TO_SPI_bit);
|
||||
}
|
||||
|
||||
if (mesa_fp->Base.InputsRead & (1 << FRAG_ATTRIB_FACE))
|
||||
{
|
||||
ui += 1;
|
||||
SETfield(evergreen->SPI_PS_IN_CONTROL_0.u32All, ui, NUM_INTERP_shift, NUM_INTERP_mask);
|
||||
SETbit(evergreen->SPI_PS_IN_CONTROL_1.u32All, FRONT_FACE_ENA_bit);
|
||||
SETbit(evergreen->SPI_PS_IN_CONTROL_1.u32All, FRONT_FACE_ALL_BITS_bit);
|
||||
SETfield(evergreen->SPI_PS_IN_CONTROL_1.u32All, pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FACE], FRONT_FACE_ADDR_shift, FRONT_FACE_ADDR_mask);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLEARbit(evergreen->SPI_PS_IN_CONTROL_1.u32All, FRONT_FACE_ENA_bit);
|
||||
}
|
||||
|
||||
/* see if we need any point_sprite replacements */
|
||||
for (i = VERT_RESULT_TEX0; i<= VERT_RESULT_TEX7; i++)
|
||||
{
|
||||
if(ctx->Point.CoordReplace[i - VERT_RESULT_TEX0] == GL_TRUE)
|
||||
point_sprite = GL_TRUE;
|
||||
}
|
||||
|
||||
if ((mesa_fp->Base.InputsRead & (1 << FRAG_ATTRIB_PNTC)) || point_sprite)
|
||||
{
|
||||
/* for FRAG_ATTRIB_PNTC we need to increase num_interp */
|
||||
if(mesa_fp->Base.InputsRead & (1 << FRAG_ATTRIB_PNTC))
|
||||
{
|
||||
ui++;
|
||||
SETfield(evergreen->SPI_PS_IN_CONTROL_0.u32All, ui, NUM_INTERP_shift, NUM_INTERP_mask);
|
||||
}
|
||||
SETbit(evergreen->SPI_INTERP_CONTROL_0.u32All, PNT_SPRITE_ENA_bit);
|
||||
SETfield(evergreen->SPI_INTERP_CONTROL_0.u32All, SPI_PNT_SPRITE_SEL_S, PNT_SPRITE_OVRD_X_shift, PNT_SPRITE_OVRD_X_mask);
|
||||
SETfield(evergreen->SPI_INTERP_CONTROL_0.u32All, SPI_PNT_SPRITE_SEL_T, PNT_SPRITE_OVRD_Y_shift, PNT_SPRITE_OVRD_Y_mask);
|
||||
SETfield(evergreen->SPI_INTERP_CONTROL_0.u32All, SPI_PNT_SPRITE_SEL_0, PNT_SPRITE_OVRD_Z_shift, PNT_SPRITE_OVRD_Z_mask);
|
||||
SETfield(evergreen->SPI_INTERP_CONTROL_0.u32All, SPI_PNT_SPRITE_SEL_1, PNT_SPRITE_OVRD_W_shift, PNT_SPRITE_OVRD_W_mask);
|
||||
if(ctx->Point.SpriteOrigin == GL_LOWER_LEFT)
|
||||
SETbit(evergreen->SPI_INTERP_CONTROL_0.u32All, PNT_SPRITE_TOP_1_bit);
|
||||
else
|
||||
CLEARbit(evergreen->SPI_INTERP_CONTROL_0.u32All, PNT_SPRITE_TOP_1_bit);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLEARbit(evergreen->SPI_INTERP_CONTROL_0.u32All, PNT_SPRITE_ENA_bit);
|
||||
}
|
||||
|
||||
|
||||
ui = (unNumOfReg < ui) ? ui : unNumOfReg;
|
||||
|
||||
SETfield(evergreen->SQ_PGM_RESOURCES_PS.u32All, ui, NUM_GPRS_shift, NUM_GPRS_mask);
|
||||
|
||||
CLEARbit(evergreen->SQ_PGM_RESOURCES_PS.u32All, UNCACHED_FIRST_INST_bit);
|
||||
|
||||
if(fp->r700Shader.uStackSize) /* we don't use branch for now, it should be zero. */
|
||||
{
|
||||
SETfield(evergreen->SQ_PGM_RESOURCES_PS.u32All, fp->r700Shader.uStackSize,
|
||||
STACK_SIZE_shift, STACK_SIZE_mask);
|
||||
}
|
||||
|
||||
SETfield(evergreen->SQ_PGM_EXPORTS_PS.u32All, fp->r700Shader.exportMode,
|
||||
EXPORT_MODE_shift, EXPORT_MODE_mask);
|
||||
|
||||
// emit ps input map
|
||||
struct evergreen_vertex_program_cont *vpc =
|
||||
(struct evergreen_vertex_program_cont *)ctx->VertexProgram._Current;
|
||||
GLbitfield OutputsWritten = vpc->mesa_program.Base.OutputsWritten;
|
||||
|
||||
for(ui = 0; ui < EVERGREEN_MAX_SHADER_EXPORTS; ui++)
|
||||
evergreen->SPI_PS_INPUT_CNTL[ui].u32All = 0;
|
||||
|
||||
unBit = 1 << FRAG_ATTRIB_WPOS;
|
||||
if(mesa_fp->Base.InputsRead & unBit)
|
||||
{
|
||||
ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_WPOS];
|
||||
SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
|
||||
SETfield(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, ui,
|
||||
SEMANTIC_shift, SEMANTIC_mask);
|
||||
if (evergreen->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
|
||||
SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
|
||||
else
|
||||
CLEARbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
|
||||
}
|
||||
|
||||
unBit = 1 << VERT_RESULT_COL0;
|
||||
if(OutputsWritten & unBit)
|
||||
{
|
||||
ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL0];
|
||||
SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
|
||||
SETfield(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, ui,
|
||||
SEMANTIC_shift, SEMANTIC_mask);
|
||||
if (evergreen->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
|
||||
SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
|
||||
else
|
||||
CLEARbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
|
||||
}
|
||||
|
||||
unBit = 1 << VERT_RESULT_COL1;
|
||||
if(OutputsWritten & unBit)
|
||||
{
|
||||
ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL1];
|
||||
SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
|
||||
SETfield(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, ui,
|
||||
SEMANTIC_shift, SEMANTIC_mask);
|
||||
if (evergreen->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
|
||||
SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
|
||||
else
|
||||
CLEARbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
|
||||
}
|
||||
|
||||
unBit = 1 << VERT_RESULT_FOGC;
|
||||
if(OutputsWritten & unBit)
|
||||
{
|
||||
ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FOGC];
|
||||
SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
|
||||
SETfield(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, ui,
|
||||
SEMANTIC_shift, SEMANTIC_mask);
|
||||
if (evergreen->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
|
||||
SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
|
||||
else
|
||||
CLEARbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
|
||||
}
|
||||
|
||||
for(i=0; i<8; i++)
|
||||
{
|
||||
unBit = 1 << (VERT_RESULT_TEX0 + i);
|
||||
if(OutputsWritten & unBit)
|
||||
{
|
||||
ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_TEX0 + i];
|
||||
SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
|
||||
SETfield(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, ui,
|
||||
SEMANTIC_shift, SEMANTIC_mask);
|
||||
CLEARbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
|
||||
/* ARB_point_sprite */
|
||||
if(ctx->Point.CoordReplace[i] == GL_TRUE)
|
||||
{
|
||||
SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, PT_SPRITE_TEX_bit);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
unBit = 1 << FRAG_ATTRIB_FACE;
|
||||
if(mesa_fp->Base.InputsRead & unBit)
|
||||
{
|
||||
ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FACE];
|
||||
SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
|
||||
SETfield(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, ui,
|
||||
SEMANTIC_shift, SEMANTIC_mask);
|
||||
if (evergreen->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
|
||||
SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
|
||||
else
|
||||
CLEARbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
|
||||
}
|
||||
unBit = 1 << FRAG_ATTRIB_PNTC;
|
||||
if(mesa_fp->Base.InputsRead & unBit)
|
||||
{
|
||||
ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_PNTC];
|
||||
SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
|
||||
SETfield(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, ui,
|
||||
SEMANTIC_shift, SEMANTIC_mask);
|
||||
if (evergreen->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
|
||||
SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
|
||||
else
|
||||
CLEARbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
|
||||
SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, PT_SPRITE_TEX_bit);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
for(i=VERT_RESULT_VAR0; i<VERT_RESULT_MAX; i++)
|
||||
{
|
||||
unBit = 1 << i;
|
||||
if(OutputsWritten & unBit)
|
||||
{
|
||||
ui = pAsm->uiFP_AttributeMap[i-VERT_RESULT_VAR0+FRAG_ATTRIB_VAR0];
|
||||
SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
|
||||
SETfield(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, ui,
|
||||
SEMANTIC_shift, SEMANTIC_mask);
|
||||
if (evergreen->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
|
||||
SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
|
||||
else
|
||||
CLEARbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
|
||||
}
|
||||
}
|
||||
|
||||
exportCount = (evergreen->SQ_PGM_EXPORTS_PS.u32All & EXPORT_MODE_mask) / (1 << EXPORT_MODE_shift);
|
||||
|
||||
/* sent out shader constants. */
|
||||
paramList = fp->mesa_program.Base.Parameters;
|
||||
|
||||
if(NULL != paramList)
|
||||
{
|
||||
_mesa_load_state_parameters(ctx, paramList);
|
||||
|
||||
if (paramList->NumParameters > EVERGREEN_MAX_DX9_CONSTS)
|
||||
return GL_FALSE;
|
||||
|
||||
EVERGREEN_STATECHANGE(context, sq);
|
||||
|
||||
evergreen->ps.num_consts = paramList->NumParameters;
|
||||
|
||||
unNumParamData = paramList->NumParameters;
|
||||
|
||||
for(ui=0; ui<unNumParamData; ui++) {
|
||||
evergreen->ps.consts[ui][0].f32All = paramList->ParameterValues[ui][0];
|
||||
evergreen->ps.consts[ui][1].f32All = paramList->ParameterValues[ui][1];
|
||||
evergreen->ps.consts[ui][2].f32All = paramList->ParameterValues[ui][2];
|
||||
evergreen->ps.consts[ui][3].f32All = paramList->ParameterValues[ui][3];
|
||||
}
|
||||
|
||||
/* Load fp constants to gpu */
|
||||
if(unNumParamData > 0)
|
||||
{
|
||||
radeonAllocDmaRegion(&context->radeon,
|
||||
&context->fp_Constbo,
|
||||
&context->fp_bo_offset,
|
||||
256,
|
||||
256);
|
||||
r600EmitShaderConsts(ctx,
|
||||
context->fp_Constbo,
|
||||
context->fp_bo_offset,
|
||||
(GLvoid *)&(evergreen->ps.consts[0][0]),
|
||||
unNumParamData * 4 * 4);
|
||||
}
|
||||
} else
|
||||
evergreen->ps.num_consts = 0;
|
||||
|
||||
COMPILED_SUB * pCompiledSub;
|
||||
GLuint uj;
|
||||
GLuint unConstOffset = evergreen->ps.num_consts;
|
||||
for(ui=0; ui<pAsm->unNumPresub; ui++)
|
||||
{
|
||||
pCompiledSub = pAsm->presubs[ui].pCompiledSub;
|
||||
|
||||
evergreen->ps.num_consts += pCompiledSub->NumParameters;
|
||||
|
||||
for(uj=0; uj<pCompiledSub->NumParameters; uj++)
|
||||
{
|
||||
evergreen->ps.consts[uj + unConstOffset][0].f32All = pCompiledSub->ParameterValues[uj][0];
|
||||
evergreen->ps.consts[uj + unConstOffset][1].f32All = pCompiledSub->ParameterValues[uj][1];
|
||||
evergreen->ps.consts[uj + unConstOffset][2].f32All = pCompiledSub->ParameterValues[uj][2];
|
||||
evergreen->ps.consts[uj + unConstOffset][3].f32All = pCompiledSub->ParameterValues[uj][3];
|
||||
}
|
||||
unConstOffset += pCompiledSub->NumParameters;
|
||||
}
|
||||
|
||||
return GL_TRUE;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
/*
|
||||
* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Authors:
|
||||
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef _EVERGREEN_FRAGPROG_H_
|
||||
#define _EVERGREEN_FRAGPROG_H_
|
||||
|
||||
#include "r600_context.h"
|
||||
#include "r700_assembler.h"
|
||||
|
||||
struct evergreen_fragment_program
|
||||
{
|
||||
struct gl_fragment_program mesa_program;
|
||||
|
||||
r700_AssemblerBase r700AsmCode;
|
||||
R700_Shader r700Shader;
|
||||
|
||||
GLboolean translated;
|
||||
GLboolean loaded;
|
||||
GLboolean error;
|
||||
|
||||
void * shaderbo;
|
||||
|
||||
GLuint k0used;
|
||||
void * constbo0;
|
||||
|
||||
GLboolean WritesDepth;
|
||||
GLuint optimization;
|
||||
};
|
||||
|
||||
/* Internal */
|
||||
void evergreen_insert_wpos_code(GLcontext *ctx, struct gl_fragment_program *fprog);
|
||||
|
||||
void evergreen_Map_Fragment_Program(r700_AssemblerBase *pAsm,
|
||||
struct gl_fragment_program *mesa_fp,
|
||||
GLcontext *ctx);
|
||||
GLboolean evergreen_Find_Instruction_Dependencies_fp(struct evergreen_fragment_program *fp,
|
||||
struct gl_fragment_program *mesa_fp);
|
||||
|
||||
GLboolean evergreenTranslateFragmentShader(struct evergreen_fragment_program *fp,
|
||||
struct gl_fragment_program *mesa_vp,
|
||||
GLcontext *ctx);
|
||||
|
||||
/* Interface */
|
||||
extern void evergreenSelectFragmentShader(GLcontext *ctx);
|
||||
|
||||
extern GLboolean evergreenSetupFragmentProgram(GLcontext * ctx);
|
||||
|
||||
extern void * evergreenGetActiveFpShaderBo(GLcontext * ctx);
|
||||
|
||||
extern void * evergreenGetActiveFpShaderConstBo(GLcontext * ctx);
|
||||
|
||||
#endif /*_EVERGREEN_FRAGPROG_H_*/
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Authors:
|
||||
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
|
||||
*/
|
||||
|
||||
#include <sched.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include "main/glheader.h"
|
||||
#include "main/imports.h"
|
||||
#include "main/macros.h"
|
||||
#include "main/context.h"
|
||||
#include "main/simple_list.h"
|
||||
|
||||
#include "radeon_common.h"
|
||||
#include "r600_context.h"
|
||||
|
||||
#include "evergreen_ioctl.h"
|
||||
|
||||
#include "r700_clear.h"
|
||||
|
||||
void evergreenClear(GLcontext * ctx, GLbitfield mask)
|
||||
{
|
||||
r700Clear(ctx, mask);
|
||||
}
|
||||
|
||||
void evergreenInitIoctlFuncs(struct dd_function_table *functions)
|
||||
{
|
||||
functions->Clear = evergreenClear;
|
||||
functions->Finish = radeonFinish;
|
||||
functions->Flush = radeonFlush;
|
||||
}
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Authors:
|
||||
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef _EVERGREEN_IOCTL_H_
|
||||
#define _EVERGREEN_IOCTL_H_
|
||||
|
||||
#include "r600_context.h"
|
||||
#include "radeon_drm.h"
|
||||
|
||||
extern void evergreenClear(GLcontext * ctx, GLbitfield mask);
|
||||
extern void evergreenInitIoctlFuncs(struct dd_function_table *functions);
|
||||
|
||||
#endif /* _EVERGREEN_IOCTL_H_ */
|
||||
|
|
@ -0,0 +1,881 @@
|
|||
/*
|
||||
* Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Authors:
|
||||
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef _EVERGREEN_OFF_H_
|
||||
#define _EVERGREEN_OFF_H_
|
||||
|
||||
enum
|
||||
{
|
||||
/* Registers from PA block: */
|
||||
EG_PA_SC_SCREEN_SCISSOR_TL = 0x28030, // DIFF
|
||||
EG_PA_SC_SCREEN_SCISSOR_BR = 0x28034, // DIFF
|
||||
EG_PA_SC_WINDOW_OFFSET = 0x28200, // DIFF
|
||||
EG_PA_SC_WINDOW_SCISSOR_TL = 0x28204, // DIFF
|
||||
EG_PA_SC_WINDOW_SCISSOR_BR = 0x28208, // DIFF
|
||||
EG_PA_SC_CLIPRECT_RULE = 0x2820C, // SAME
|
||||
EG_PA_SC_CLIPRECT_0_TL = 0x28210, // DIFF
|
||||
EG_PA_SC_CLIPRECT_0_BR = 0x28214, // DIFF
|
||||
EG_PA_SC_CLIPRECT_1_TL = 0x28218, // DIFF
|
||||
EG_PA_SC_CLIPRECT_1_BR = 0x2821C, // DIFF
|
||||
EG_PA_SC_CLIPRECT_2_TL = 0x28220, // DIFF
|
||||
EG_PA_SC_CLIPRECT_2_BR = 0x28224, // DIFF
|
||||
EG_PA_SC_CLIPRECT_3_TL = 0x28228, // DIFF
|
||||
EG_PA_SC_CLIPRECT_3_BR = 0x2822C, // DIFF
|
||||
EG_PA_SC_EDGERULE = 0x28230, // SAME
|
||||
EG_PA_SU_HARDWARE_SCREEN_OFFSET = 0x28234, //
|
||||
EG_PA_SC_GENERIC_SCISSOR_TL = 0x28240, // DIFF
|
||||
EG_PA_SC_GENERIC_SCISSOR_BR = 0x28244, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_0_TL = 0x28250, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_0_BR = 0x28254, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_1_TL = 0x28258, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_1_BR = 0x2825C, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_2_TL = 0x28260, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_2_BR = 0x28264, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_3_TL = 0x28268, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_3_BR = 0x2826C, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_4_TL = 0x28270, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_4_BR = 0x28274, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_5_TL = 0x28278, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_5_BR = 0x2827C, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_6_TL = 0x28280, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_6_BR = 0x28284, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_7_TL = 0x28288, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_7_BR = 0x2828C, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_8_TL = 0x28290, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_8_BR = 0x28294, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_9_TL = 0x28298, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_9_BR = 0x2829C, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_10_TL = 0x282A0, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_10_BR = 0x282A4, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_11_TL = 0x282A8, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_11_BR = 0x282AC, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_12_TL = 0x282B0, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_12_BR = 0x282B4, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_13_TL = 0x282B8, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_13_BR = 0x282BC, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_14_TL = 0x282C0, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_14_BR = 0x282C4, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_15_TL = 0x282C8, // DIFF
|
||||
EG_PA_SC_VPORT_SCISSOR_15_BR = 0x282CC, // DIFF
|
||||
EG_PA_SC_VPORT_ZMIN_0 = 0x282D0, // SAME
|
||||
EG_PA_SC_VPORT_ZMAX_0 = 0x282D4, // SAME
|
||||
EG_PA_SC_VPORT_ZMIN_1 = 0x282D8, // SAME
|
||||
EG_PA_SC_VPORT_ZMAX_1 = 0x282DC, // SAME
|
||||
EG_PA_SC_VPORT_ZMIN_2 = 0x282E0, // SAME
|
||||
EG_PA_SC_VPORT_ZMAX_2 = 0x282E4, // SAME
|
||||
EG_PA_SC_VPORT_ZMIN_3 = 0x282E8, // SAME
|
||||
EG_PA_SC_VPORT_ZMAX_3 = 0x282EC, // SAME
|
||||
EG_PA_SC_VPORT_ZMIN_4 = 0x282F0, // SAME
|
||||
EG_PA_SC_VPORT_ZMAX_4 = 0x282F4, // SAME
|
||||
EG_PA_SC_VPORT_ZMIN_5 = 0x282F8, // SAME
|
||||
EG_PA_SC_VPORT_ZMAX_5 = 0x282FC, // SAME
|
||||
EG_PA_SC_VPORT_ZMIN_6 = 0x28300, // SAME
|
||||
EG_PA_SC_VPORT_ZMAX_6 = 0x28304, // SAME
|
||||
EG_PA_SC_VPORT_ZMIN_7 = 0x28308, // SAME
|
||||
EG_PA_SC_VPORT_ZMAX_7 = 0x2830C, // SAME
|
||||
EG_PA_SC_VPORT_ZMIN_8 = 0x28310, // SAME
|
||||
EG_PA_SC_VPORT_ZMAX_8 = 0x28314, // SAME
|
||||
EG_PA_SC_VPORT_ZMIN_9 = 0x28318, // SAME
|
||||
EG_PA_SC_VPORT_ZMAX_9 = 0x2831C, // SAME
|
||||
EG_PA_SC_VPORT_ZMIN_10 = 0x28320, // SAME
|
||||
EG_PA_SC_VPORT_ZMAX_10 = 0x28324, // SAME
|
||||
EG_PA_SC_VPORT_ZMIN_11 = 0x28328, // SAME
|
||||
EG_PA_SC_VPORT_ZMAX_11 = 0x2832C, // SAME
|
||||
EG_PA_SC_VPORT_ZMIN_12 = 0x28330, // SAME
|
||||
EG_PA_SC_VPORT_ZMAX_12 = 0x28334, // SAME
|
||||
EG_PA_SC_VPORT_ZMIN_13 = 0x28338, // SAME
|
||||
EG_PA_SC_VPORT_ZMAX_13 = 0x2833C, // SAME
|
||||
EG_PA_SC_VPORT_ZMIN_14 = 0x28340, // SAME
|
||||
EG_PA_SC_VPORT_ZMAX_14 = 0x28344, // SAME
|
||||
EG_PA_SC_VPORT_ZMIN_15 = 0x28348, // SAME
|
||||
EG_PA_SC_VPORT_ZMAX_15 = 0x2834C, // SAME
|
||||
EG_PA_CL_VPORT_XSCALE = 0x2843C, // SAME
|
||||
EG_PA_CL_VPORT_XOFFSET = 0x28440, // SAME
|
||||
EG_PA_CL_VPORT_YSCALE = 0x28444, // SAME
|
||||
EG_PA_CL_VPORT_YOFFSET = 0x28448, // SAME
|
||||
EG_PA_CL_VPORT_ZSCALE = 0x2844C, // SAME
|
||||
EG_PA_CL_VPORT_ZOFFSET = 0x28450, // SAME
|
||||
EG_PA_CL_VPORT_XSCALE_1 = 0x28454, // SAME
|
||||
EG_PA_CL_VPORT_XOFFSET_1 = 0x28458, // SAME
|
||||
EG_PA_CL_VPORT_YSCALE_1 = 0x2845C, // SAME
|
||||
EG_PA_CL_VPORT_YOFFSET_1 = 0x28460, // SAME
|
||||
EG_PA_CL_VPORT_ZSCALE_1 = 0x28464, // SAME
|
||||
EG_PA_CL_VPORT_ZOFFSET_1 = 0x28468, // SAME
|
||||
EG_PA_CL_VPORT_XSCALE_2 = 0x2846C, // SAME
|
||||
EG_PA_CL_VPORT_XOFFSET_2 = 0x28470, // SAME
|
||||
EG_PA_CL_VPORT_YSCALE_2 = 0x28474, // SAME
|
||||
EG_PA_CL_VPORT_YOFFSET_2 = 0x28478, // SAME
|
||||
EG_PA_CL_VPORT_ZSCALE_2 = 0x2847C, // SAME
|
||||
EG_PA_CL_VPORT_ZOFFSET_2 = 0x28480, // SAME
|
||||
EG_PA_CL_VPORT_XSCALE_3 = 0x28484, // SAME
|
||||
EG_PA_CL_VPORT_XOFFSET_3 = 0x28488, // SAME
|
||||
EG_PA_CL_VPORT_YSCALE_3 = 0x2848C, // SAME
|
||||
EG_PA_CL_VPORT_YOFFSET_3 = 0x28490, // SAME
|
||||
EG_PA_CL_VPORT_ZSCALE_3 = 0x28494, // SAME
|
||||
EG_PA_CL_VPORT_ZOFFSET_3 = 0x28498, // SAME
|
||||
EG_PA_CL_VPORT_XSCALE_4 = 0x2849C, // SAME
|
||||
EG_PA_CL_VPORT_XOFFSET_4 = 0x284A0, // SAME
|
||||
EG_PA_CL_VPORT_YSCALE_4 = 0x284A4, // SAME
|
||||
EG_PA_CL_VPORT_YOFFSET_4 = 0x284A8, // SAME
|
||||
EG_PA_CL_VPORT_ZSCALE_4 = 0x284AC, // SAME
|
||||
EG_PA_CL_VPORT_ZOFFSET_4 = 0x284B0, // SAME
|
||||
EG_PA_CL_VPORT_XSCALE_5 = 0x284B4, // SAME
|
||||
EG_PA_CL_VPORT_XOFFSET_5 = 0x284B8, // SAME
|
||||
EG_PA_CL_VPORT_YSCALE_5 = 0x284BC, // SAME
|
||||
EG_PA_CL_VPORT_YOFFSET_5 = 0x284C0, // SAME
|
||||
EG_PA_CL_VPORT_ZSCALE_5 = 0x284C4, // SAME
|
||||
EG_PA_CL_VPORT_ZOFFSET_5 = 0x284C8, // SAME
|
||||
EG_PA_CL_VPORT_XSCALE_6 = 0x284CC, // SAME
|
||||
EG_PA_CL_VPORT_XOFFSET_6 = 0x284D0, // SAME
|
||||
EG_PA_CL_VPORT_YSCALE_6 = 0x284D4, // SAME
|
||||
EG_PA_CL_VPORT_YOFFSET_6 = 0x284D8, // SAME
|
||||
EG_PA_CL_VPORT_ZSCALE_6 = 0x284DC, // SAME
|
||||
EG_PA_CL_VPORT_ZOFFSET_6 = 0x284E0, // SAME
|
||||
EG_PA_CL_VPORT_XSCALE_7 = 0x284E4, // SAME
|
||||
EG_PA_CL_VPORT_XOFFSET_7 = 0x284E8, // SAME
|
||||
EG_PA_CL_VPORT_YSCALE_7 = 0x284EC, // SAME
|
||||
EG_PA_CL_VPORT_YOFFSET_7 = 0x284F0, // SAME
|
||||
EG_PA_CL_VPORT_ZSCALE_7 = 0x284F4, // SAME
|
||||
EG_PA_CL_VPORT_ZOFFSET_7 = 0x284F8, // SAME
|
||||
EG_PA_CL_VPORT_XSCALE_8 = 0x284FC, // SAME
|
||||
EG_PA_CL_VPORT_XOFFSET_8 = 0x28500, // SAME
|
||||
EG_PA_CL_VPORT_YSCALE_8 = 0x28504, // SAME
|
||||
EG_PA_CL_VPORT_YOFFSET_8 = 0x28508, // SAME
|
||||
EG_PA_CL_VPORT_ZSCALE_8 = 0x2850C, // SAME
|
||||
EG_PA_CL_VPORT_ZOFFSET_8 = 0x28510, // SAME
|
||||
EG_PA_CL_VPORT_XSCALE_9 = 0x28514, // SAME
|
||||
EG_PA_CL_VPORT_XOFFSET_9 = 0x28518, // SAME
|
||||
EG_PA_CL_VPORT_YSCALE_9 = 0x2851C, // SAME
|
||||
EG_PA_CL_VPORT_YOFFSET_9 = 0x28520, // SAME
|
||||
EG_PA_CL_VPORT_ZSCALE_9 = 0x28524, // SAME
|
||||
EG_PA_CL_VPORT_ZOFFSET_9 = 0x28528, // SAME
|
||||
EG_PA_CL_VPORT_XSCALE_10 = 0x2852C, // SAME
|
||||
EG_PA_CL_VPORT_XOFFSET_10 = 0x28530, // SAME
|
||||
EG_PA_CL_VPORT_YSCALE_10 = 0x28534, // SAME
|
||||
EG_PA_CL_VPORT_YOFFSET_10 = 0x28538, // SAME
|
||||
EG_PA_CL_VPORT_ZSCALE_10 = 0x2853C, // SAME
|
||||
EG_PA_CL_VPORT_ZOFFSET_10 = 0x28540, // SAME
|
||||
EG_PA_CL_VPORT_XSCALE_11 = 0x28544, // SAME
|
||||
EG_PA_CL_VPORT_XOFFSET_11 = 0x28548, // SAME
|
||||
EG_PA_CL_VPORT_YSCALE_11 = 0x2854C, // SAME
|
||||
EG_PA_CL_VPORT_YOFFSET_11 = 0x28550, // SAME
|
||||
EG_PA_CL_VPORT_ZSCALE_11 = 0x28554, // SAME
|
||||
EG_PA_CL_VPORT_ZOFFSET_11 = 0x28558, // SAME
|
||||
EG_PA_CL_VPORT_XSCALE_12 = 0x2855C, // SAME
|
||||
EG_PA_CL_VPORT_XOFFSET_12 = 0x28560, // SAME
|
||||
EG_PA_CL_VPORT_YSCALE_12 = 0x28564, // SAME
|
||||
EG_PA_CL_VPORT_YOFFSET_12 = 0x28568, // SAME
|
||||
EG_PA_CL_VPORT_ZSCALE_12 = 0x2856C, // SAME
|
||||
EG_PA_CL_VPORT_ZOFFSET_12 = 0x28570, // SAME
|
||||
EG_PA_CL_VPORT_XSCALE_13 = 0x28574, // SAME
|
||||
EG_PA_CL_VPORT_XOFFSET_13 = 0x28578, // SAME
|
||||
EG_PA_CL_VPORT_YSCALE_13 = 0x2857C, // SAME
|
||||
EG_PA_CL_VPORT_YOFFSET_13 = 0x28580, // SAME
|
||||
EG_PA_CL_VPORT_ZSCALE_13 = 0x28584, // SAME
|
||||
EG_PA_CL_VPORT_ZOFFSET_13 = 0x28588, // SAME
|
||||
EG_PA_CL_VPORT_XSCALE_14 = 0x2858C, // SAME
|
||||
EG_PA_CL_VPORT_XOFFSET_14 = 0x28590, // SAME
|
||||
EG_PA_CL_VPORT_YSCALE_14 = 0x28594, // SAME
|
||||
EG_PA_CL_VPORT_YOFFSET_14 = 0x28598, // SAME
|
||||
EG_PA_CL_VPORT_ZSCALE_14 = 0x2859C, // SAME
|
||||
EG_PA_CL_VPORT_ZOFFSET_14 = 0x285A0, // SAME
|
||||
EG_PA_CL_VPORT_XSCALE_15 = 0x285A4, // SAME
|
||||
EG_PA_CL_VPORT_XOFFSET_15 = 0x285A8, // SAME
|
||||
EG_PA_CL_VPORT_YSCALE_15 = 0x285AC, // SAME
|
||||
EG_PA_CL_VPORT_YOFFSET_15 = 0x285B0, // SAME
|
||||
EG_PA_CL_VPORT_ZSCALE_15 = 0x285B4, // SAME
|
||||
EG_PA_CL_VPORT_ZOFFSET_15 = 0x285B8, // SAME
|
||||
EG_PA_CL_UCP_0_X = 0x285BC, // SAME 0x28E20
|
||||
EG_PA_CL_UCP_0_Y = 0x285C0, // SAME 0x28E24
|
||||
EG_PA_CL_UCP_0_Z = 0x285C4, // SAME 0x28E28
|
||||
EG_PA_CL_UCP_0_W = 0x285C8, // SAME 0x28E2C
|
||||
EG_PA_CL_UCP_1_X = 0x285CC, // SAME 0x28E30
|
||||
EG_PA_CL_UCP_1_Y = 0x285D0, // SAME 0x28E34
|
||||
EG_PA_CL_UCP_1_Z = 0x285D4, // SAME 0x28E38
|
||||
EG_PA_CL_UCP_1_W = 0x285D8, // SAME 0x28E3C
|
||||
EG_PA_CL_UCP_2_X = 0x285DC, // SAME 0x28E40
|
||||
EG_PA_CL_UCP_2_Y = 0x285E0, // SAME 0x28E44
|
||||
EG_PA_CL_UCP_2_Z = 0x285E4, // SAME 0x28E48
|
||||
EG_PA_CL_UCP_2_W = 0x285E8, // SAME 0x28E4C
|
||||
EG_PA_CL_UCP_3_X = 0x285EC, // SAME 0x28E50
|
||||
EG_PA_CL_UCP_3_Y = 0x285F0, // SAME 0x28E54
|
||||
EG_PA_CL_UCP_3_Z = 0x285F4, // SAME 0x28E58
|
||||
EG_PA_CL_UCP_3_W = 0x285F8, // SAME 0x28E5C
|
||||
EG_PA_CL_UCP_4_X = 0x285FC, // SAME 0x28E60
|
||||
EG_PA_CL_UCP_4_Y = 0x28600, // SAME 0x28E64
|
||||
EG_PA_CL_UCP_4_Z = 0x28604, // SAME 0x28E68
|
||||
EG_PA_CL_UCP_4_W = 0x28608, // SAME 0x28E6C
|
||||
EG_PA_CL_UCP_5_X = 0x2860C, // SAME 0x28E70
|
||||
EG_PA_CL_UCP_5_Y = 0x28610, // SAME 0x28E74
|
||||
EG_PA_CL_UCP_5_Z = 0x28614, // SAME 0x28E78
|
||||
EG_PA_CL_UCP_5_W = 0x28618, // SAME 0x28E7C
|
||||
EG_PA_CL_POINT_X_RAD = 0x287D4, // SAME 0x28E10
|
||||
EG_PA_CL_POINT_Y_RAD = 0x287D8, // SAME 0x28E14
|
||||
EG_PA_CL_POINT_SIZE = 0x287DC, // SAME 0x28E18
|
||||
EG_PA_CL_POINT_CULL_RAD = 0x287E0, // SAME 0x28E1C
|
||||
EG_PA_CL_CLIP_CNTL = 0x28810, // SAME
|
||||
EG_PA_SU_SC_MODE_CNTL = 0x28814, // SAME
|
||||
EG_PA_CL_VTE_CNTL = 0x28818, // SAME
|
||||
EG_PA_CL_VS_OUT_CNTL = 0x2881C, // SAME
|
||||
EG_PA_CL_NANINF_CNTL = 0x28820, // SAME
|
||||
EG_PA_SU_LINE_STIPPLE_CNTL = 0x28824, //
|
||||
EG_PA_SU_LINE_STIPPLE_SCALE = 0x28828, //
|
||||
EG_PA_SU_PRIM_FILTER_CNTL = 0x2882C, //
|
||||
EG_PA_SU_POINT_SIZE = 0x28A00, // SAME
|
||||
EG_PA_SU_POINT_MINMAX = 0x28A04, // SAME
|
||||
EG_PA_SU_LINE_CNTL = 0x28A08, // SAME
|
||||
EG_PA_SC_LINE_STIPPLE = 0x28A0C, // SAME
|
||||
EG_PA_SC_MODE_CNTL_0 = 0x28A48, //
|
||||
EG_PA_SC_MODE_CNTL_1 = 0x28A4C, //
|
||||
EG_PA_SU_POLY_OFFSET_DB_FMT_CNTL = 0x28B78, // SAME 0x28DF8
|
||||
EG_PA_SU_POLY_OFFSET_CLAMP = 0x28B7C, // SAME 0x28DFC
|
||||
EG_PA_SU_POLY_OFFSET_FRONT_SCALE = 0x28B80, // SAME 0x28E00
|
||||
EG_PA_SU_POLY_OFFSET_FRONT_OFFSET = 0x28B84, // SAME 0x28E04
|
||||
EG_PA_SU_POLY_OFFSET_BACK_SCALE = 0x28B88, // SAME 0x28E08
|
||||
EG_PA_SU_POLY_OFFSET_BACK_OFFSET = 0x28B8C, // SAME 0x28E0C
|
||||
EG_PA_SC_LINE_CNTL = 0x28C00, // DIFF
|
||||
EG_PA_SC_AA_CONFIG = 0x28C04, // SAME
|
||||
EG_PA_SU_VTX_CNTL = 0x28C08, // SAME
|
||||
EG_PA_CL_GB_VERT_CLIP_ADJ = 0x28C0C, // SAME
|
||||
EG_PA_CL_GB_VERT_DISC_ADJ = 0x28C10, // SAME
|
||||
EG_PA_CL_GB_HORZ_CLIP_ADJ = 0x28C14, // SAME
|
||||
EG_PA_CL_GB_HORZ_DISC_ADJ = 0x28C18, // SAME
|
||||
EG_PA_SC_AA_SAMPLE_LOCS_0 = 0x28C1C, //
|
||||
EG_PA_SC_AA_SAMPLE_LOCS_1 = 0x28C20, //
|
||||
EG_PA_SC_AA_SAMPLE_LOCS_2 = 0x28C24, //
|
||||
EG_PA_SC_AA_SAMPLE_LOCS_3 = 0x28C28, //
|
||||
EG_PA_SC_AA_SAMPLE_LOCS_4 = 0x28C2C, //
|
||||
EG_PA_SC_AA_SAMPLE_LOCS_5 = 0x28C30, //
|
||||
EG_PA_SC_AA_SAMPLE_LOCS_6 = 0x28C34, //
|
||||
EG_PA_SC_AA_SAMPLE_LOCS_7 = 0x28C38, //
|
||||
EG_PA_SC_AA_MASK = 0x28C3C, // SAME 0x28C48
|
||||
|
||||
/* Registers from VGT block: */
|
||||
EG_VGT_INDEX_TYPE = 0x895C, //? config space
|
||||
EG_VGT_PRIMITIVE_TYPE = 0x8958, //? config space
|
||||
|
||||
EG_VGT_MAX_VTX_INDX = 0x28400, // SAME
|
||||
EG_VGT_MIN_VTX_INDX = 0x28404, // SAME
|
||||
EG_VGT_INDX_OFFSET = 0x28408, // SAME
|
||||
EG_VGT_MULTI_PRIM_IB_RESET_INDX = 0x2840C, // SAME
|
||||
EG_CS_COPY_STATE = 0x287CC, //
|
||||
EG_GFX_COPY_STATE = 0x287D0, // SAME
|
||||
EG_VGT_DMA_BASE_HI = 0x287E4, // SAME
|
||||
EG_VGT_DMA_BASE = 0x287E8, // SAME
|
||||
EG_VGT_DRAW_INITIATOR = 0x287F0, // SAME
|
||||
EG_VGT_IMMED_DATA = 0x287F4, // SAME
|
||||
EG_VGT_EVENT_ADDRESS_REG = 0x287F8, // SAME
|
||||
EG_VGT_OUTPUT_PATH_CNTL = 0x28A10, // DIFF
|
||||
EG_VGT_HOS_CNTL = 0x28A14, // SAME
|
||||
EG_VGT_HOS_MAX_TESS_LEVEL = 0x28A18, // SAME
|
||||
EG_VGT_HOS_MIN_TESS_LEVEL = 0x28A1C, // SAME
|
||||
EG_VGT_HOS_REUSE_DEPTH = 0x28A20, // SAME
|
||||
EG_VGT_GROUP_PRIM_TYPE = 0x28A24, // SAME
|
||||
EG_VGT_GROUP_FIRST_DECR = 0x28A28, // SAME
|
||||
EG_VGT_GROUP_DECR = 0x28A2C, // SAME
|
||||
EG_VGT_GROUP_VECT_0_CNTL = 0x28A30, // SAME
|
||||
EG_VGT_GROUP_VECT_1_CNTL = 0x28A34, // SAME
|
||||
EG_VGT_GROUP_VECT_0_FMT_CNTL = 0x28A38, // SAME
|
||||
EG_VGT_GROUP_VECT_1_FMT_CNTL = 0x28A3C, // SAME
|
||||
EG_VGT_GS_MODE = 0x28A40, // DIFF
|
||||
EG_VGT_ENHANCE = 0x28A50, // DIFF
|
||||
EG_VGT_GS_PER_ES = 0x28A54, // DIFF 0x88C8
|
||||
EG_VGT_ES_PER_GS = 0x28A58, // DIFF 0x88CC
|
||||
EG_VGT_GS_PER_VS = 0x28A5C, // SAME 0x88E8
|
||||
EG_VGT_GS_OUT_PRIM_TYPE = 0x28A6C, // SAME
|
||||
EG_VGT_DMA_SIZE = 0x28A74, // SAME
|
||||
EG_VGT_DMA_MAX_SIZE = 0x28A78, // SAME
|
||||
EG_VGT_DMA_INDEX_TYPE = 0x28A7C, // SAME
|
||||
EG_VGT_PRIMITIVEID_EN = 0x28A84, // SAME
|
||||
EG_VGT_DMA_NUM_INSTANCES = 0x28A88, // SAME
|
||||
EG_VGT_EVENT_INITIATOR = 0x28A90, // SAME
|
||||
EG_VGT_MULTI_PRIM_IB_RESET_EN = 0x28A94, // SAME
|
||||
EG_VGT_INSTANCE_STEP_RATE_0 = 0x28AA0, // SAME
|
||||
EG_VGT_INSTANCE_STEP_RATE_1 = 0x28AA4, // SAME
|
||||
EG_VGT_REUSE_OFF = 0x28AB4, // SAME
|
||||
EG_VGT_VTX_CNT_EN = 0x28AB8, // SAME
|
||||
EG_VGT_STRMOUT_BUFFER_SIZE_0 = 0x28AD0, // SAME
|
||||
EG_VGT_STRMOUT_VTX_STRIDE_0 = 0x28AD4, // SAME
|
||||
EG_VGT_STRMOUT_BUFFER_BASE_0 = 0x28AD8, // SAME
|
||||
EG_VGT_STRMOUT_BUFFER_OFFSET_0 = 0x28ADC, // SAME
|
||||
EG_VGT_STRMOUT_BUFFER_SIZE_1 = 0x28AE0, // SAME
|
||||
EG_VGT_STRMOUT_VTX_STRIDE_1 = 0x28AE4, // SAME
|
||||
EG_VGT_STRMOUT_BUFFER_BASE_1 = 0x28AE8, // SAME
|
||||
EG_VGT_STRMOUT_BUFFER_OFFSET_1 = 0x28AEC, // SAME
|
||||
EG_VGT_STRMOUT_BUFFER_SIZE_2 = 0x28AF0, // SAME
|
||||
EG_VGT_STRMOUT_VTX_STRIDE_2 = 0x28AF4, // SAME
|
||||
EG_VGT_STRMOUT_BUFFER_BASE_2 = 0x28AF8, // SAME
|
||||
EG_VGT_STRMOUT_BUFFER_OFFSET_2 = 0x28AFC, // SAME
|
||||
EG_VGT_STRMOUT_BUFFER_SIZE_3 = 0x28B00, // SAME
|
||||
EG_VGT_STRMOUT_VTX_STRIDE_3 = 0x28B04, // SAME
|
||||
EG_VGT_STRMOUT_BUFFER_BASE_3 = 0x28B08, // SAME
|
||||
EG_VGT_STRMOUT_BUFFER_OFFSET_3 = 0x28B0C, // SAME
|
||||
EG_VGT_STRMOUT_BASE_OFFSET_0 = 0x28B10, // SAME
|
||||
EG_VGT_STRMOUT_BASE_OFFSET_1 = 0x28B14, // SAME
|
||||
EG_VGT_STRMOUT_BASE_OFFSET_2 = 0x28B18, // SAME
|
||||
EG_VGT_STRMOUT_BASE_OFFSET_3 = 0x28B1C, // SAME
|
||||
EG_VGT_STRMOUT_DRAW_OPAQUE_OFFSET = 0x28B28, // SAME
|
||||
EG_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE = 0x28B2C, // SAME
|
||||
EG_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE = 0x28B30, // DIFF
|
||||
EG_VGT_GS_MAX_VERT_OUT = 0x28B38, // SAME
|
||||
EG_VGT_STRMOUT_BASE_OFFSET_HI_0 = 0x28B44, // SAME
|
||||
EG_VGT_STRMOUT_BASE_OFFSET_HI_1 = 0x28B48, // SAME
|
||||
EG_VGT_STRMOUT_BASE_OFFSET_HI_2 = 0x28B4C, // SAME
|
||||
EG_VGT_STRMOUT_BASE_OFFSET_HI_3 = 0x28B50, // SAME
|
||||
EG_VGT_SHADER_STAGES_EN = 0x28B54, //
|
||||
EG_VGT_LS_HS_CONFIG = 0x28B58, //
|
||||
EG_VGT_LS_SIZE = 0x28B5C, //
|
||||
EG_VGT_HS_SIZE = 0x28B60, //
|
||||
EG_VGT_LS_HS_ALLOC = 0x28B64, //
|
||||
EG_VGT_HS_PATCH_CONST = 0x28B68, //
|
||||
EG_VGT_TF_PARAM = 0x28B6C, //
|
||||
EG_VGT_DISPATCH_INITIATOR = 0x28B74, //
|
||||
EG_VGT_GS_INSTANCE_CNT = 0x28B90, //
|
||||
EG_VGT_STRMOUT_CONFIG = 0x28B94, //
|
||||
EG_VGT_STRMOUT_BUFFER_CONFIG = 0x28B98, //
|
||||
EG_VGT_VERTEX_REUSE_BLOCK_CNTL = 0x28C58, // SAME
|
||||
EG_VGT_OUT_DEALLOC_CNTL = 0x28C5C, // SAME
|
||||
|
||||
/* Registers from TP block: */
|
||||
EG_GDS_ADDR_BASE = 0x28720, //
|
||||
EG_GDS_ADDR_SIZE = 0x28724, //
|
||||
EG_GDS_ORDERED_WAVE_PER_SE = 0x28728, //
|
||||
EG_GDS_APPEND_CONSUME_UAV0 = 0x2872C, //
|
||||
EG_GDS_APPEND_CONSUME_UAV1 = 0x28730, //
|
||||
EG_GDS_APPEND_CONSUME_UAV2 = 0x28734, //
|
||||
EG_GDS_APPEND_CONSUME_UAV3 = 0x28738, //
|
||||
EG_GDS_APPEND_CONSUME_UAV4 = 0x2873C, //
|
||||
EG_GDS_APPEND_CONSUME_UAV5 = 0x28740, //
|
||||
EG_GDS_APPEND_CONSUME_UAV6 = 0x28744, //
|
||||
EG_GDS_APPEND_CONSUME_UAV7 = 0x28748, //
|
||||
EG_GDS_APPEND_CONSUME_UAV8 = 0x2874C, //
|
||||
EG_GDS_APPEND_CONSUME_UAV9 = 0x28750, //
|
||||
EG_GDS_APPEND_CONSUME_UAV10 = 0x28754, //
|
||||
EG_GDS_APPEND_CONSUME_UAV11 = 0x28758, //
|
||||
|
||||
/* Registers from SQ block: */
|
||||
EG_SQ_LOOP_CONST_0 = 0x3A200, // 0x3E200
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_VS_0 = 0x28180, // ?
|
||||
EG_SQ_VTX_SEMANTIC_0 = 0x28380, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_1 = 0x28384, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_2 = 0x28388, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_3 = 0x2838C, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_4 = 0x28390, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_5 = 0x28394, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_6 = 0x28398, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_7 = 0x2839C, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_8 = 0x283A0, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_9 = 0x283A4, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_10 = 0x283A8, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_11 = 0x283AC, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_12 = 0x283B0, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_13 = 0x283B4, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_14 = 0x283B8, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_15 = 0x283BC, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_16 = 0x283C0, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_17 = 0x283C4, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_18 = 0x283C8, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_19 = 0x283CC, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_20 = 0x283D0, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_21 = 0x283D4, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_22 = 0x283D8, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_23 = 0x283DC, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_24 = 0x283E0, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_25 = 0x283E4, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_26 = 0x283E8, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_27 = 0x283EC, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_28 = 0x283F0, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_29 = 0x283F4, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_30 = 0x283F8, // SAME
|
||||
EG_SQ_VTX_SEMANTIC_31 = 0x283FC, // SAME
|
||||
EG_SQ_LSTMP_RING_ITEMSIZE = 0x28830, //
|
||||
EG_SQ_HSTMP_RING_ITEMSIZE = 0x28834, //
|
||||
EG_SQ_DYN_GPR_RESOURCE_LIMIT_1 = 0x28838, //
|
||||
EG_SQ_PGM_START_PS = 0x28840, // SAME
|
||||
EG_SQ_PGM_RESOURCES_PS = 0x28844, // DIFF 0x28850
|
||||
EG_SQ_PGM_RESOURCES_2_PS = 0x28848, //
|
||||
EG_SQ_PGM_EXPORTS_PS = 0x2884C, // SAME 0x28854
|
||||
EG_SQ_PGM_START_VS = 0x2885C, // SAME 0x28858
|
||||
EG_SQ_PGM_RESOURCES_VS = 0x28860, // DIFF 0x28868
|
||||
EG_SQ_PGM_RESOURCES_2_VS = 0x28864, //
|
||||
EG_SQ_PGM_START_GS = 0x28874, // SAME 0x2886C
|
||||
EG_SQ_PGM_RESOURCES_GS = 0x28878, // DIFF 0x2887C
|
||||
EG_SQ_PGM_RESOURCES_2_GS = 0x2887C, //
|
||||
EG_SQ_PGM_START_ES = 0x2888C, // SAME 0x28880
|
||||
EG_SQ_PGM_RESOURCES_ES = 0x28890, // DIFF
|
||||
EG_SQ_PGM_RESOURCES_2_ES = 0x28894, //
|
||||
EG_SQ_PGM_START_FS = 0x288A4, // SAME 0x28894
|
||||
EG_SQ_PGM_RESOURCES_FS = 0x288A8, // DIFF 0x288A4
|
||||
EG_SQ_PGM_START_HS = 0x288B8, //
|
||||
EG_SQ_PGM_RESOURCES_HS = 0x288BC, //
|
||||
EG_SQ_PGM_RESOURCES_2_HS = 0x288C0, //
|
||||
EG_SQ_PGM_START_LS = 0x288D0, //
|
||||
EG_SQ_PGM_RESOURCES_LS = 0x288D4, //
|
||||
EG_SQ_PGM_RESOURCES_2_LS = 0x288D8, //
|
||||
EG_SQ_THREAD_TRACE_USERDATA = 0x288DC, //
|
||||
EG_SQ_LDS_ALLOC = 0x288E8, //
|
||||
EG_SQ_LDS_ALLOC_PS = 0x288EC, //
|
||||
EG_SQ_VTX_SEMANTIC_CLEAR = 0x288F0, // SAME 0x288E0
|
||||
EG_SQ_THREAD_TRACE_CTRL = 0x288F8, //
|
||||
EG_SQ_ESGS_RING_ITEMSIZE = 0x28900, // SAME 0x288A8
|
||||
EG_SQ_GSVS_RING_ITEMSIZE = 0x28904, // SAME 0x288AC
|
||||
EG_SQ_ESTMP_RING_ITEMSIZE = 0x28908, // SAME 0x288B0
|
||||
EG_SQ_GSTMP_RING_ITEMSIZE = 0x2890C, // SAME 0x288B4
|
||||
EG_SQ_VSTMP_RING_ITEMSIZE = 0x28910, // SAME 0x288B8
|
||||
EG_SQ_PSTMP_RING_ITEMSIZE = 0x28914, // SAME 0x288BC
|
||||
EG_SQ_GS_VERT_ITEMSIZE = 0x2891C, // SAME 0x288C8
|
||||
EG_SQ_GS_VERT_ITEMSIZE_1 = 0x28920, //
|
||||
EG_SQ_GS_VERT_ITEMSIZE_2 = 0x28924, //
|
||||
EG_SQ_GS_VERT_ITEMSIZE_3 = 0x28928, //
|
||||
EG_SQ_GSVS_RING_OFFSET_1 = 0x2892C, //
|
||||
EG_SQ_GSVS_RING_OFFSET_2 = 0x28930, //
|
||||
EG_SQ_GSVS_RING_OFFSET_3 = 0x28934, //
|
||||
EG_SQ_ALU_CONST_CACHE_PS_0 = 0x28940, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_PS_1 = 0x28944, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_PS_2 = 0x28948, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_PS_3 = 0x2894C, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_PS_4 = 0x28950, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_PS_5 = 0x28954, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_PS_6 = 0x28958, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_PS_7 = 0x2895C, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_PS_8 = 0x28960, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_PS_9 = 0x28964, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_PS_10 = 0x28968, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_PS_11 = 0x2896C, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_PS_12 = 0x28970, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_PS_13 = 0x28974, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_PS_14 = 0x28978, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_PS_15 = 0x2897C, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_VS_0 = 0x28980, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_VS_1 = 0x28984, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_VS_2 = 0x28988, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_VS_3 = 0x2898C, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_VS_4 = 0x28990, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_VS_5 = 0x28994, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_VS_6 = 0x28998, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_VS_7 = 0x2899C, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_VS_8 = 0x289A0, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_VS_9 = 0x289A4, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_VS_10 = 0x289A8, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_VS_11 = 0x289AC, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_VS_12 = 0x289B0, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_VS_13 = 0x289B4, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_VS_14 = 0x289B8, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_VS_15 = 0x289BC, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_GS_0 = 0x289C0, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_GS_1 = 0x289C4, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_GS_2 = 0x289C8, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_GS_3 = 0x289CC, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_GS_4 = 0x289D0, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_GS_5 = 0x289D4, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_GS_6 = 0x289D8, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_GS_7 = 0x289DC, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_GS_8 = 0x289E0, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_GS_9 = 0x289E4, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_GS_10 = 0x289E8, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_GS_11 = 0x289EC, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_GS_12 = 0x289F0, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_GS_13 = 0x289F4, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_GS_14 = 0x289F8, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_GS_15 = 0x289FC, // SAME
|
||||
EG_SQ_ALU_CONST_CACHE_HS_0 = 0x28F00, //
|
||||
EG_SQ_ALU_CONST_CACHE_HS_1 = 0x28F04, //
|
||||
EG_SQ_ALU_CONST_CACHE_HS_2 = 0x28F08, //
|
||||
EG_SQ_ALU_CONST_CACHE_HS_3 = 0x28F0C, //
|
||||
EG_SQ_ALU_CONST_CACHE_HS_4 = 0x28F10, //
|
||||
EG_SQ_ALU_CONST_CACHE_HS_5 = 0x28F14, //
|
||||
EG_SQ_ALU_CONST_CACHE_HS_6 = 0x28F18, //
|
||||
EG_SQ_ALU_CONST_CACHE_HS_7 = 0x28F1C, //
|
||||
EG_SQ_ALU_CONST_CACHE_HS_8 = 0x28F20, //
|
||||
EG_SQ_ALU_CONST_CACHE_HS_9 = 0x28F24, //
|
||||
EG_SQ_ALU_CONST_CACHE_HS_10 = 0x28F28, //
|
||||
EG_SQ_ALU_CONST_CACHE_HS_11 = 0x28F2C, //
|
||||
EG_SQ_ALU_CONST_CACHE_HS_12 = 0x28F30, //
|
||||
EG_SQ_ALU_CONST_CACHE_HS_13 = 0x28F34, //
|
||||
EG_SQ_ALU_CONST_CACHE_HS_14 = 0x28F38, //
|
||||
EG_SQ_ALU_CONST_CACHE_HS_15 = 0x28F3C, //
|
||||
EG_SQ_ALU_CONST_CACHE_LS_0 = 0x28F40, //
|
||||
EG_SQ_ALU_CONST_CACHE_LS_1 = 0x28F44, //
|
||||
EG_SQ_ALU_CONST_CACHE_LS_2 = 0x28F48, //
|
||||
EG_SQ_ALU_CONST_CACHE_LS_3 = 0x28F4C, //
|
||||
EG_SQ_ALU_CONST_CACHE_LS_4 = 0x28F50, //
|
||||
EG_SQ_ALU_CONST_CACHE_LS_5 = 0x28F54, //
|
||||
EG_SQ_ALU_CONST_CACHE_LS_6 = 0x28F58, //
|
||||
EG_SQ_ALU_CONST_CACHE_LS_7 = 0x28F5C, //
|
||||
EG_SQ_ALU_CONST_CACHE_LS_8 = 0x28F60, //
|
||||
EG_SQ_ALU_CONST_CACHE_LS_9 = 0x28F64, //
|
||||
EG_SQ_ALU_CONST_CACHE_LS_10 = 0x28F68, //
|
||||
EG_SQ_ALU_CONST_CACHE_LS_11 = 0x28F6C, //
|
||||
EG_SQ_ALU_CONST_CACHE_LS_12 = 0x28F70, //
|
||||
EG_SQ_ALU_CONST_CACHE_LS_13 = 0x28F74, //
|
||||
EG_SQ_ALU_CONST_CACHE_LS_14 = 0x28F78, //
|
||||
EG_SQ_ALU_CONST_CACHE_LS_15 = 0x28F7C, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_PS_0 = 0x28140,
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_0 = 0x28F80, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_1 = 0x28F84, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_2 = 0x28F88, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_3 = 0x28F8C, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_4 = 0x28F90, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_5 = 0x28F94, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_6 = 0x28F98, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_7 = 0x28F9C, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_8 = 0x28FA0, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_9 = 0x28FA4, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_10 = 0x28FA8, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_11 = 0x28FAC, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_12 = 0x28FB0, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_13 = 0x28FB4, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_14 = 0x28FB8, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_15 = 0x28FBC, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_0 = 0x28FC0, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_1 = 0x28FC4, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_2 = 0x28FC8, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_3 = 0x28FCC, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_4 = 0x28FD0, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_5 = 0x28FD4, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_6 = 0x28FD8, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_7 = 0x28FDC, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_8 = 0x28FE0, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_9 = 0x28FE4, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_10 = 0x28FE8, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_11 = 0x28FEC, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_12 = 0x28FF0, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_13 = 0x28FF4, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_14 = 0x28FF8, //
|
||||
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_15 = 0x28FFC, //
|
||||
|
||||
/* Registers from SPI block: */
|
||||
EG_SPI_VS_OUT_ID_0 = 0x2861C, // SAME 0x28614
|
||||
EG_SPI_VS_OUT_ID_1 = 0x28620, // SAME 0x28618
|
||||
EG_SPI_VS_OUT_ID_2 = 0x28624, // SAME 0x2861C
|
||||
EG_SPI_VS_OUT_ID_3 = 0x28628, // SAME 0x28620
|
||||
EG_SPI_VS_OUT_ID_4 = 0x2862C, // SAME 0x28624
|
||||
EG_SPI_VS_OUT_ID_5 = 0x28630, // SAME 0x28628
|
||||
EG_SPI_VS_OUT_ID_6 = 0x28634, // SAME 0x2862C
|
||||
EG_SPI_VS_OUT_ID_7 = 0x28638, // SAME 0x28630
|
||||
EG_SPI_VS_OUT_ID_8 = 0x2863C, // SAME 0x28634
|
||||
EG_SPI_VS_OUT_ID_9 = 0x28640, // SAME 0x28638
|
||||
EG_SPI_PS_INPUT_CNTL_0 = 0x28644, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_1 = 0x28648, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_2 = 0x2864C, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_3 = 0x28650, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_4 = 0x28654, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_5 = 0x28658, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_6 = 0x2865C, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_7 = 0x28660, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_8 = 0x28664, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_9 = 0x28668, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_10 = 0x2866C, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_11 = 0x28670, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_12 = 0x28674, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_13 = 0x28678, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_14 = 0x2867C, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_15 = 0x28680, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_16 = 0x28684, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_17 = 0x28688, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_18 = 0x2868C, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_19 = 0x28690, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_20 = 0x28694, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_21 = 0x28698, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_22 = 0x2869C, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_23 = 0x286A0, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_24 = 0x286A4, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_25 = 0x286A8, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_26 = 0x286AC, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_27 = 0x286B0, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_28 = 0x286B4, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_29 = 0x286B8, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_30 = 0x286BC, // SAME
|
||||
EG_SPI_PS_INPUT_CNTL_31 = 0x286C0, // SAME
|
||||
EG_SPI_VS_OUT_CONFIG = 0x286C4, // SAME
|
||||
EG_SPI_THREAD_GROUPING = 0x286C8, // DIFF
|
||||
EG_SPI_PS_IN_CONTROL_0 = 0x286CC, // SAME
|
||||
EG_SPI_PS_IN_CONTROL_1 = 0x286D0, // SAME
|
||||
EG_SPI_INTERP_CONTROL_0 = 0x286D4, // SAME
|
||||
EG_SPI_INPUT_Z = 0x286D8, // SAME
|
||||
EG_SPI_FOG_CNTL = 0x286DC, // SAME
|
||||
EG_SPI_BARYC_CNTL = 0x286E0, //
|
||||
EG_SPI_PS_IN_CONTROL_2 = 0x286E4, //
|
||||
EG_SPI_COMPUTE_INPUT_CNTL = 0x286E8, //
|
||||
EG_SPI_COMPUTE_NUM_THREAD_X = 0x286EC, //
|
||||
EG_SPI_COMPUTE_NUM_THREAD_Y = 0x286F0, //
|
||||
EG_SPI_COMPUTE_NUM_THREAD_Z = 0x286F4, //
|
||||
|
||||
/* Registers from SX block: */
|
||||
EG_SX_MISC = 0x28350, // SAME
|
||||
EG_SX_SURFACE_SYNC = 0x28354, // DIFF
|
||||
EG_SX_ALPHA_TEST_CONTROL = 0x28410, // SAME
|
||||
EG_SX_ALPHA_REF = 0x28438, // SAME
|
||||
|
||||
/* Registers from DB block: */
|
||||
EG_DB_RENDER_CONTROL = 0x28000, // DIFF 0x28D0C
|
||||
EG_DB_COUNT_CONTROL = 0x28004, //
|
||||
EG_DB_DEPTH_VIEW = 0x28008, // DIFF 0x28004
|
||||
EG_DB_RENDER_OVERRIDE = 0x2800C, // DIFF 0x28D10
|
||||
EG_DB_RENDER_OVERRIDE2 = 0x28010, //
|
||||
EG_DB_HTILE_DATA_BASE = 0x28014, // SAME
|
||||
|
||||
EG_DB_STENCIL_CLEAR = 0x28028, // SAME
|
||||
EG_DB_DEPTH_CLEAR = 0x2802C, // SAME
|
||||
|
||||
EG_DB_Z_INFO = 0x28040, //
|
||||
EG_DB_STENCIL_INFO = 0x28044, //
|
||||
EG_DB_Z_READ_BASE = 0x28048, //
|
||||
EG_DB_STENCIL_READ_BASE = 0x2804C, //
|
||||
EG_DB_Z_WRITE_BASE = 0x28050, //
|
||||
EG_DB_STENCIL_WRITE_BASE = 0x28054, //
|
||||
EG_DB_DEPTH_SIZE = 0x28058, // DIFF 0x28000
|
||||
EG_DB_DEPTH_SLICE = 0x2805C, //
|
||||
|
||||
EG_DB_STENCILREFMASK = 0x28430, // SAME
|
||||
EG_DB_STENCILREFMASK_BF = 0x28434, // SAME
|
||||
EG_DB_DEPTH_CONTROL = 0x28800, // SAME
|
||||
EG_DB_SHADER_CONTROL = 0x2880C, // DIFF
|
||||
EG_DB_HTILE_SURFACE = 0x28ABC, // SAME 0x28D24
|
||||
EG_DB_SRESULTS_COMPARE_STATE0 = 0x28AC0, // SAME 0x28D28
|
||||
EG_DB_SRESULTS_COMPARE_STATE1 = 0x28AC4, // SAME 0x28D2C
|
||||
EG_DB_PRELOAD_CONTROL = 0x28AC8, // SAME 0x28D30
|
||||
EG_DB_ALPHA_TO_MASK = 0x28B70, // SAME 0x28D44
|
||||
|
||||
/* Registers from CB block: */
|
||||
EG_CB_TARGET_MASK = 0x28238, // SAME
|
||||
EG_CB_SHADER_MASK = 0x2823C, // SAME
|
||||
EG_CB_BLEND_RED = 0x28414, // SAME
|
||||
EG_CB_BLEND_GREEN = 0x28418, // SAME
|
||||
EG_CB_BLEND_BLUE = 0x2841C, // SAME
|
||||
EG_CB_BLEND_ALPHA = 0x28420, // SAME
|
||||
EG_CB_BLEND0_CONTROL = 0x28780, // DIFF
|
||||
EG_CB_BLEND1_CONTROL = 0x28784, // DIFF
|
||||
EG_CB_BLEND2_CONTROL = 0x28788, // DIFF
|
||||
EG_CB_BLEND3_CONTROL = 0x2878C, // DIFF
|
||||
EG_CB_BLEND4_CONTROL = 0x28790, // DIFF
|
||||
EG_CB_BLEND5_CONTROL = 0x28794, // DIFF
|
||||
EG_CB_BLEND6_CONTROL = 0x28798, // DIFF
|
||||
EG_CB_BLEND7_CONTROL = 0x2879C, // DIFF
|
||||
EG_CB_COLOR_CONTROL = 0x28808, // DIFF
|
||||
EG_CB_IMMED0_BASE = 0x28B9C, //
|
||||
EG_CB_IMMED1_BASE = 0x28BA0, //
|
||||
EG_CB_IMMED2_BASE = 0x28BA4, //
|
||||
EG_CB_IMMED3_BASE = 0x28BA8, //
|
||||
EG_CB_IMMED4_BASE = 0x28BAC, //
|
||||
EG_CB_IMMED5_BASE = 0x28BB0, //
|
||||
EG_CB_IMMED6_BASE = 0x28BB4, //
|
||||
EG_CB_IMMED7_BASE = 0x28BB8, //
|
||||
EG_CB_IMMED8_BASE = 0x28BBC, //
|
||||
EG_CB_IMMED9_BASE = 0x28BC0, //
|
||||
EG_CB_IMMED10_BASE = 0x28BC4, //
|
||||
EG_CB_IMMED11_BASE = 0x28BC8, //
|
||||
EG_CB_CLRCMP_CONTROL = 0x28C40, // SAME 0x28C30
|
||||
EG_CB_CLRCMP_SRC = 0x28C44, // SAME 0x28C34
|
||||
EG_CB_CLRCMP_DST = 0x28C48, // SAME 0x28C38
|
||||
EG_CB_CLRCMP_MSK = 0x28C4C, // SAME 0x28C3C
|
||||
EG_CB_COLOR0_BASE = 0x28C60, // SAME 0x28040
|
||||
EG_CB_COLOR0_PITCH = 0x28C64, //
|
||||
EG_CB_COLOR0_SLICE = 0x28C68, //
|
||||
EG_CB_COLOR0_VIEW = 0x28C6C, // SAME 0x28080
|
||||
EG_CB_COLOR0_INFO = 0x28C70, // DIFF 0x280A0
|
||||
EG_CB_COLOR0_ATTRIB = 0x28C74, //
|
||||
EG_CB_COLOR0_DIM = 0x28C78, //
|
||||
EG_CB_COLOR0_CMASK = 0x28C7C, //
|
||||
EG_CB_COLOR0_CMASK_SLICE = 0x28C80, //
|
||||
EG_CB_COLOR0_FMASK = 0x28C84, //
|
||||
EG_CB_COLOR0_FMASK_SLICE = 0x28C88, //
|
||||
EG_CB_COLOR0_CLEAR_WORD0 = 0x28C8C, //
|
||||
EG_CB_COLOR0_CLEAR_WORD1 = 0x28C90, //
|
||||
EG_CB_COLOR0_CLEAR_WORD2 = 0x28C94, //
|
||||
EG_CB_COLOR0_CLEAR_WORD3 = 0x28C98, //
|
||||
EG_CB_COLOR1_BASE = 0x28C9C, // SAME 0x28044
|
||||
EG_CB_COLOR1_PITCH = 0x28CA0, //
|
||||
EG_CB_COLOR1_SLICE = 0x28CA4, //
|
||||
EG_CB_COLOR1_VIEW = 0x28CA8, // SAME 0x28084
|
||||
EG_CB_COLOR1_INFO = 0x28CAC, // DIFF 0x280A4
|
||||
EG_CB_COLOR1_ATTRIB = 0x28CB0, //
|
||||
EG_CB_COLOR1_DIM = 0x28CB4, //
|
||||
EG_CB_COLOR1_CMASK = 0x28CB8, //
|
||||
EG_CB_COLOR1_CMASK_SLICE = 0x28CBC, //
|
||||
EG_CB_COLOR1_FMASK = 0x28CC0, //
|
||||
EG_CB_COLOR1_FMASK_SLICE = 0x28CC4, //
|
||||
EG_CB_COLOR1_CLEAR_WORD0 = 0x28CC8, //
|
||||
EG_CB_COLOR1_CLEAR_WORD1 = 0x28CCC, //
|
||||
EG_CB_COLOR1_CLEAR_WORD2 = 0x28CD0, //
|
||||
EG_CB_COLOR1_CLEAR_WORD3 = 0x28CD4, //
|
||||
EG_CB_COLOR2_BASE = 0x28CD8, // SAME 0x28048
|
||||
EG_CB_COLOR2_PITCH = 0x28CDC, //
|
||||
EG_CB_COLOR2_SLICE = 0x28CE0, //
|
||||
EG_CB_COLOR2_VIEW = 0x28CE4, // SAME 0x28088
|
||||
EG_CB_COLOR2_INFO = 0x28CE8, // DIFF 0x280A8
|
||||
EG_CB_COLOR2_ATTRIB = 0x28CEC, //
|
||||
EG_CB_COLOR2_DIM = 0x28CF0, //
|
||||
EG_CB_COLOR2_CMASK = 0x28CF4, //
|
||||
EG_CB_COLOR2_CMASK_SLICE = 0x28CF8, //
|
||||
EG_CB_COLOR2_FMASK = 0x28CFC, //
|
||||
EG_CB_COLOR2_FMASK_SLICE = 0x28D00, //
|
||||
EG_CB_COLOR2_CLEAR_WORD0 = 0x28D04, //
|
||||
EG_CB_COLOR2_CLEAR_WORD1 = 0x28D08, //
|
||||
EG_CB_COLOR2_CLEAR_WORD2 = 0x28D0C, //
|
||||
EG_CB_COLOR2_CLEAR_WORD3 = 0x28D10, //
|
||||
EG_CB_COLOR3_BASE = 0x28D14, // SAME 0x2804C
|
||||
EG_CB_COLOR3_PITCH = 0x28D18, //
|
||||
EG_CB_COLOR3_SLICE = 0x28D1C, //
|
||||
EG_CB_COLOR3_VIEW = 0x28D20, // SAME 0x2808C
|
||||
EG_CB_COLOR3_INFO = 0x28D24, // DIFF 0x280AC
|
||||
EG_CB_COLOR3_ATTRIB = 0x28D28, //
|
||||
EG_CB_COLOR3_DIM = 0x28D2C, //
|
||||
EG_CB_COLOR3_CMASK = 0x28D30, //
|
||||
EG_CB_COLOR3_CMASK_SLICE = 0x28D34, //
|
||||
EG_CB_COLOR3_FMASK = 0x28D38, //
|
||||
EG_CB_COLOR3_FMASK_SLICE = 0x28D3C, //
|
||||
EG_CB_COLOR3_CLEAR_WORD0 = 0x28D40, //
|
||||
EG_CB_COLOR3_CLEAR_WORD1 = 0x28D44, //
|
||||
EG_CB_COLOR3_CLEAR_WORD2 = 0x28D48, //
|
||||
EG_CB_COLOR3_CLEAR_WORD3 = 0x28D4C, //
|
||||
EG_CB_COLOR4_BASE = 0x28D50, // SAME 0x28050
|
||||
EG_CB_COLOR4_PITCH = 0x28D54, //
|
||||
EG_CB_COLOR4_SLICE = 0x28D58, //
|
||||
EG_CB_COLOR4_VIEW = 0x28D5C, // SAME 0x28090
|
||||
EG_CB_COLOR4_INFO = 0x28D60, // DIFF 0x280B0
|
||||
EG_CB_COLOR4_ATTRIB = 0x28D64, //
|
||||
EG_CB_COLOR4_DIM = 0x28D68, //
|
||||
EG_CB_COLOR4_CMASK = 0x28D6C, //
|
||||
EG_CB_COLOR4_CMASK_SLICE = 0x28D70, //
|
||||
EG_CB_COLOR4_FMASK = 0x28D74, //
|
||||
EG_CB_COLOR4_FMASK_SLICE = 0x28D78, //
|
||||
EG_CB_COLOR4_CLEAR_WORD0 = 0x28D7C, //
|
||||
EG_CB_COLOR4_CLEAR_WORD1 = 0x28D80, //
|
||||
EG_CB_COLOR4_CLEAR_WORD2 = 0x28D84, //
|
||||
EG_CB_COLOR4_CLEAR_WORD3 = 0x28D88, //
|
||||
EG_CB_COLOR5_BASE = 0x28D8C, // SAME 0x28054
|
||||
EG_CB_COLOR5_PITCH = 0x28D90, //
|
||||
EG_CB_COLOR5_SLICE = 0x28D94, //
|
||||
EG_CB_COLOR5_VIEW = 0x28D98, // SAME 0x28094
|
||||
EG_CB_COLOR5_INFO = 0x28D9C, // DIFF 0x280B4
|
||||
EG_CB_COLOR5_ATTRIB = 0x28DA0, //
|
||||
EG_CB_COLOR5_DIM = 0x28DA4, //
|
||||
EG_CB_COLOR5_CMASK = 0x28DA8, //
|
||||
EG_CB_COLOR5_CMASK_SLICE = 0x28DAC, //
|
||||
EG_CB_COLOR5_FMASK = 0x28DB0, //
|
||||
EG_CB_COLOR5_FMASK_SLICE = 0x28DB4, //
|
||||
EG_CB_COLOR5_CLEAR_WORD0 = 0x28DB8, //
|
||||
EG_CB_COLOR5_CLEAR_WORD1 = 0x28DBC, //
|
||||
EG_CB_COLOR5_CLEAR_WORD2 = 0x28DC0, //
|
||||
EG_CB_COLOR5_CLEAR_WORD3 = 0x28DC4, //
|
||||
EG_CB_COLOR6_BASE = 0x28DC8, // SAME 0x28058
|
||||
EG_CB_COLOR6_PITCH = 0x28DCC, //
|
||||
EG_CB_COLOR6_SLICE = 0x28DD0, //
|
||||
EG_CB_COLOR6_VIEW = 0x28DD4, // SAME 0x28098
|
||||
EG_CB_COLOR6_INFO = 0x28DD8, // DIFF 0x280B8
|
||||
EG_CB_COLOR6_ATTRIB = 0x28DDC, //
|
||||
EG_CB_COLOR6_DIM = 0x28DE0, //
|
||||
EG_CB_COLOR6_CMASK = 0x28DE4, //
|
||||
EG_CB_COLOR6_CMASK_SLICE = 0x28DE8, //
|
||||
EG_CB_COLOR6_FMASK = 0x28DEC, //
|
||||
EG_CB_COLOR6_FMASK_SLICE = 0x28DF0, //
|
||||
EG_CB_COLOR6_CLEAR_WORD0 = 0x28DF4, //
|
||||
EG_CB_COLOR6_CLEAR_WORD1 = 0x28DF8, //
|
||||
EG_CB_COLOR6_CLEAR_WORD2 = 0x28DFC, //
|
||||
EG_CB_COLOR6_CLEAR_WORD3 = 0x28E00, //
|
||||
EG_CB_COLOR7_BASE = 0x28E04, // SAME 0x2805C
|
||||
EG_CB_COLOR7_PITCH = 0x28E08, //
|
||||
EG_CB_COLOR7_SLICE = 0x28E0C, //
|
||||
EG_CB_COLOR7_VIEW = 0x28E10, // SAME 0x2809C
|
||||
EG_CB_COLOR7_INFO = 0x28E14, // DIFF 0x280BC
|
||||
EG_CB_COLOR7_ATTRIB = 0x28E18, //
|
||||
EG_CB_COLOR7_DIM = 0x28E1C, //
|
||||
EG_CB_COLOR7_CMASK = 0x28E20, //
|
||||
EG_CB_COLOR7_CMASK_SLICE = 0x28E24, //
|
||||
EG_CB_COLOR7_FMASK = 0x28E28, //
|
||||
EG_CB_COLOR7_FMASK_SLICE = 0x28E2C, //
|
||||
EG_CB_COLOR7_CLEAR_WORD0 = 0x28E30, //
|
||||
EG_CB_COLOR7_CLEAR_WORD1 = 0x28E34, //
|
||||
EG_CB_COLOR7_CLEAR_WORD2 = 0x28E38, //
|
||||
EG_CB_COLOR7_CLEAR_WORD3 = 0x28E3C, //
|
||||
EG_CB_COLOR8_BASE = 0x28E40, //
|
||||
EG_CB_COLOR8_PITCH = 0x28E44, //
|
||||
EG_CB_COLOR8_SLICE = 0x28E48, //
|
||||
EG_CB_COLOR8_VIEW = 0x28E4C, //
|
||||
EG_CB_COLOR8_INFO = 0x28E50, //
|
||||
EG_CB_COLOR8_ATTRIB = 0x28E54, //
|
||||
EG_CB_COLOR8_DIM = 0x28E58, //
|
||||
EG_CB_COLOR9_BASE = 0x28E5C, //
|
||||
EG_CB_COLOR9_PITCH = 0x28E60, //
|
||||
EG_CB_COLOR9_SLICE = 0x28E64, //
|
||||
EG_CB_COLOR9_VIEW = 0x28E68, //
|
||||
EG_CB_COLOR9_INFO = 0x28E6C, //
|
||||
EG_CB_COLOR9_ATTRIB = 0x28E70, //
|
||||
EG_CB_COLOR9_DIM = 0x28E74, //
|
||||
EG_CB_COLOR10_BASE = 0x28E78, //
|
||||
EG_CB_COLOR10_PITCH = 0x28E7C, //
|
||||
EG_CB_COLOR10_SLICE = 0x28E80, //
|
||||
EG_CB_COLOR10_VIEW = 0x28E84, //
|
||||
EG_CB_COLOR10_INFO = 0x28E88, //
|
||||
EG_CB_COLOR10_ATTRIB = 0x28E8C, //
|
||||
EG_CB_COLOR10_DIM = 0x28E90, //
|
||||
EG_CB_COLOR11_BASE = 0x28E94, //
|
||||
EG_CB_COLOR11_PITCH = 0x28E98, //
|
||||
EG_CB_COLOR11_SLICE = 0x28E9C, //
|
||||
EG_CB_COLOR11_VIEW = 0x28EA0, //
|
||||
EG_CB_COLOR11_INFO = 0x28EA4, //
|
||||
EG_CB_COLOR11_ATTRIB = 0x28EA8, //
|
||||
EG_CB_COLOR11_DIM = 0x28EAC, //
|
||||
|
||||
/* Registers from CP block: */
|
||||
EG_COHER_DEST_BASE_0 = 0x28248, // SAME
|
||||
EG_COHER_DEST_BASE_1 = 0x2824C, // SAME
|
||||
EG_CP_PERFMON_CNTX_CNTL = 0x28358, //
|
||||
|
||||
/* Config: */
|
||||
EG_SPI_CONFIG_CNTL = 0x9100, // DIFF
|
||||
EG_SPI_CONFIG_CNTL_1 = 0x913C, // DIFF
|
||||
EG_CP_PERFMON_CNTL = 0x87FC, // SAME
|
||||
EG_SQ_MS_FIFO_SIZES = 0x8CF0, // SAME
|
||||
EG_SQ_CONFIG = 0x8C00, // DIFF
|
||||
EG_SQ_GPR_RESOURCE_MGMT_1 = 0x8C04, // SAME
|
||||
EG_SQ_GPR_RESOURCE_MGMT_2 = 0x8C08, // SAME
|
||||
EG_SQ_THREAD_RESOURCE_MGMT = 0x8C18, // SAME 0x8C0C,
|
||||
EG_SQ_STACK_RESOURCE_MGMT_1 = 0x8C20, // SAME 0x8C10,
|
||||
EG_SQ_STACK_RESOURCE_MGMT_2 = 0x8C24, // SAME 0x8C14,
|
||||
EG_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ = 0x8D8C, // DIFF
|
||||
EG_SQ_LDS_RESOURCE_MGMT = 0x8E2C, //
|
||||
EG_SQ_GPR_RESOURCE_MGMT_3 = 0x8C0C, //
|
||||
EG_SQ_STACK_RESOURCE_MGMT_3 = 0x8C28, //
|
||||
EG_SQ_THREAD_RESOURCE_MGMT_2 = 0x8C1C, //
|
||||
EG_VGT_CACHE_INVALIDATION = 0x88C4, // DIFF
|
||||
EG_VGT_GS_VERTEX_REUSE = 0x88D4, // SAME
|
||||
EG_PA_SC_FORCE_EOV_MAX_CNTS = 0x8B24, // SAME
|
||||
EG_PA_SC_LINE_STIPPLE_STATE = 0x8B10, // SAME
|
||||
EG_PA_CL_ENHANCE = 0x8A14, // SAME
|
||||
|
||||
/* Tex border color */
|
||||
EG_TD_PS_BORDER_COLOR_RED = 0xA404,
|
||||
EG_TD_PS_BORDER_COLOR_GREEN = 0xA408,
|
||||
EG_TD_PS_BORDER_COLOR_BLUE = 0xA40C,
|
||||
EG_TD_PS_BORDER_COLOR_ALPHA = 0xA410,
|
||||
|
||||
/* const */
|
||||
EG_SQ_VTX_CONSTANT_WORD0_0 = 0x30000, // 0x38000
|
||||
};
|
||||
|
||||
#endif /* _EVERGREEN_OFF_H_ */
|
||||
|
|
@ -0,0 +1,193 @@
|
|||
/*
|
||||
* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Authors:
|
||||
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
|
||||
#include "main/glheader.h"
|
||||
#include "main/imports.h"
|
||||
#include "program/program.h"
|
||||
|
||||
#include "tnl/tnl.h"
|
||||
|
||||
#include "r600_context.h"
|
||||
#include "r600_emit.h"
|
||||
|
||||
#include "evergreen_oglprog.h"
|
||||
#include "evergreen_fragprog.h"
|
||||
#include "evergreen_vertprog.h"
|
||||
|
||||
|
||||
static void evergreen_freeVertProgCache(GLcontext *ctx, struct r700_vertex_program_cont *cache)
|
||||
{
|
||||
struct evergreen_vertex_program *tmp, *vp = cache->progs;
|
||||
|
||||
while (vp) {
|
||||
tmp = vp->next;
|
||||
/* Release DMA region */
|
||||
r600DeleteShader(ctx, vp->shaderbo);
|
||||
|
||||
if(NULL != vp->constbo0)
|
||||
{
|
||||
r600DeleteShader(ctx, vp->constbo0);
|
||||
}
|
||||
|
||||
/* Clean up */
|
||||
Clean_Up_Assembler(&(vp->r700AsmCode));
|
||||
Clean_Up_Shader(&(vp->r700Shader));
|
||||
|
||||
_mesa_reference_vertprog(ctx, &vp->mesa_program, NULL);
|
||||
free(vp);
|
||||
vp = tmp;
|
||||
}
|
||||
}
|
||||
|
||||
static struct gl_program *evergreenNewProgram(GLcontext * ctx,
|
||||
GLenum target,
|
||||
GLuint id)
|
||||
{
|
||||
struct gl_program *pProgram = NULL;
|
||||
|
||||
struct evergreen_vertex_program_cont *vpc;
|
||||
struct evergreen_fragment_program *fp;
|
||||
|
||||
radeon_print(RADEON_SHADER, RADEON_VERBOSE,
|
||||
"%s %u, %u\n", __func__, target, id);
|
||||
|
||||
switch (target)
|
||||
{
|
||||
case GL_VERTEX_STATE_PROGRAM_NV:
|
||||
case GL_VERTEX_PROGRAM_ARB:
|
||||
vpc = CALLOC_STRUCT(evergreen_vertex_program_cont);
|
||||
pProgram = _mesa_init_vertex_program(ctx,
|
||||
&vpc->mesa_program,
|
||||
target,
|
||||
id);
|
||||
|
||||
break;
|
||||
case GL_FRAGMENT_PROGRAM_NV:
|
||||
case GL_FRAGMENT_PROGRAM_ARB:
|
||||
fp = CALLOC_STRUCT(evergreen_fragment_program);
|
||||
pProgram = _mesa_init_fragment_program(ctx,
|
||||
&fp->mesa_program,
|
||||
target,
|
||||
id);
|
||||
fp->translated = GL_FALSE;
|
||||
fp->loaded = GL_FALSE;
|
||||
|
||||
fp->shaderbo = NULL;
|
||||
|
||||
fp->constbo0 = NULL;
|
||||
|
||||
break;
|
||||
default:
|
||||
_mesa_problem(ctx, "Bad target in evergreenNewProgram");
|
||||
}
|
||||
|
||||
return pProgram;
|
||||
}
|
||||
|
||||
static void evergreenDeleteProgram(GLcontext * ctx, struct gl_program *prog)
|
||||
{
|
||||
struct evergreen_vertex_program_cont *vpc = (struct evergreen_vertex_program_cont *)prog;
|
||||
struct evergreen_fragment_program * fp;
|
||||
|
||||
radeon_print(RADEON_SHADER, RADEON_VERBOSE,
|
||||
"%s %p\n", __func__, prog);
|
||||
|
||||
switch (prog->Target)
|
||||
{
|
||||
case GL_VERTEX_STATE_PROGRAM_NV:
|
||||
case GL_VERTEX_PROGRAM_ARB:
|
||||
evergreen_freeVertProgCache(ctx, vpc);
|
||||
break;
|
||||
case GL_FRAGMENT_PROGRAM_NV:
|
||||
case GL_FRAGMENT_PROGRAM_ARB:
|
||||
fp = (struct evergreen_fragment_program*)prog;
|
||||
/* Release DMA region */
|
||||
|
||||
r600DeleteShader(ctx, fp->shaderbo);
|
||||
|
||||
if(NULL != fp->constbo0)
|
||||
{
|
||||
r600DeleteShader(ctx, fp->constbo0);
|
||||
}
|
||||
|
||||
/* Clean up */
|
||||
Clean_Up_Assembler(&(fp->r700AsmCode));
|
||||
Clean_Up_Shader(&(fp->r700Shader));
|
||||
break;
|
||||
default:
|
||||
_mesa_problem(ctx, "Bad target in evergreenNewProgram");
|
||||
}
|
||||
|
||||
_mesa_delete_program(ctx, prog);
|
||||
}
|
||||
|
||||
static GLboolean
|
||||
evergreenProgramStringNotify(GLcontext * ctx, GLenum target, struct gl_program *prog)
|
||||
{
|
||||
struct evergreen_vertex_program_cont *vpc = (struct evergreen_vertex_program_cont *)prog;
|
||||
struct evergreen_fragment_program * fp = (struct evergreen_fragment_program*)prog;
|
||||
|
||||
switch (target) {
|
||||
case GL_VERTEX_PROGRAM_ARB:
|
||||
evergreen_freeVertProgCache(ctx, vpc);
|
||||
vpc->progs = NULL;
|
||||
break;
|
||||
case GL_FRAGMENT_PROGRAM_ARB:
|
||||
r600DeleteShader(ctx, fp->shaderbo);
|
||||
|
||||
if(NULL != fp->constbo0)
|
||||
{
|
||||
r600DeleteShader(ctx, fp->constbo0);
|
||||
fp->constbo0 = NULL;
|
||||
}
|
||||
|
||||
Clean_Up_Assembler(&(fp->r700AsmCode));
|
||||
Clean_Up_Shader(&(fp->r700Shader));
|
||||
fp->translated = GL_FALSE;
|
||||
fp->loaded = GL_FALSE;
|
||||
fp->shaderbo = NULL;
|
||||
break;
|
||||
}
|
||||
|
||||
/* XXX check if program is legal, within limits */
|
||||
return GL_TRUE;
|
||||
}
|
||||
|
||||
static GLboolean evergreenIsProgramNative(GLcontext * ctx, GLenum target, struct gl_program *prog)
|
||||
{
|
||||
|
||||
return GL_TRUE;
|
||||
}
|
||||
|
||||
void evergreenInitShaderFuncs(struct dd_function_table *functions)
|
||||
{
|
||||
functions->NewProgram = evergreenNewProgram;
|
||||
functions->DeleteProgram = evergreenDeleteProgram;
|
||||
functions->ProgramStringNotify = evergreenProgramStringNotify;
|
||||
functions->IsProgramNative = evergreenIsProgramNative;
|
||||
}
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Authors:
|
||||
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef _EVERGREEN_OGLPROG_H_
|
||||
#define _EVERGREEN_OGLPROG_H_
|
||||
#include "r600_context.h"
|
||||
|
||||
extern void evergreenInitShaderFuncs(struct dd_function_table *functions);
|
||||
|
||||
#endif /*_EVERGREEN_OGLPROG_H_*/
|
||||
|
|
@ -0,0 +1,937 @@
|
|||
/*
|
||||
* Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Authors:
|
||||
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
|
||||
*/
|
||||
|
||||
#include "main/glheader.h"
|
||||
#include "main/state.h"
|
||||
#include "main/imports.h"
|
||||
#include "main/enums.h"
|
||||
#include "main/macros.h"
|
||||
#include "main/context.h"
|
||||
#include "main/dd.h"
|
||||
#include "main/simple_list.h"
|
||||
#include "main/api_arrayelt.h"
|
||||
#include "swrast/swrast.h"
|
||||
#include "swrast_setup/swrast_setup.h"
|
||||
#include "vbo/vbo.h"
|
||||
|
||||
#include "tnl/tnl.h"
|
||||
#include "tnl/t_vp_build.h"
|
||||
#include "tnl/t_context.h"
|
||||
#include "tnl/t_vertex.h"
|
||||
#include "vbo/vbo_context.h"
|
||||
|
||||
#include "r600_context.h"
|
||||
#include "r600_cmdbuf.h"
|
||||
|
||||
#include "evergreen_vertprog.h"
|
||||
|
||||
#include "evergreen_state.h"
|
||||
#include "evergreen_tex.h"
|
||||
#include "evergreen_off.h"
|
||||
|
||||
#include "radeon_buffer_objects.h"
|
||||
#include "radeon_common_context.h"
|
||||
|
||||
static unsigned int evergreenPrimitiveType(int prim) //same
|
||||
{
|
||||
switch (prim & PRIM_MODE_MASK)
|
||||
{
|
||||
case GL_POINTS:
|
||||
return DI_PT_POINTLIST;
|
||||
break;
|
||||
case GL_LINES:
|
||||
return DI_PT_LINELIST;
|
||||
break;
|
||||
case GL_LINE_STRIP:
|
||||
return DI_PT_LINESTRIP;
|
||||
break;
|
||||
case GL_LINE_LOOP:
|
||||
return DI_PT_LINELOOP;
|
||||
break;
|
||||
case GL_TRIANGLES:
|
||||
return DI_PT_TRILIST;
|
||||
break;
|
||||
case GL_TRIANGLE_STRIP:
|
||||
return DI_PT_TRISTRIP;
|
||||
break;
|
||||
case GL_TRIANGLE_FAN:
|
||||
return DI_PT_TRIFAN;
|
||||
break;
|
||||
case GL_QUADS:
|
||||
return DI_PT_QUADLIST;
|
||||
break;
|
||||
case GL_QUAD_STRIP:
|
||||
return DI_PT_QUADSTRIP;
|
||||
break;
|
||||
case GL_POLYGON:
|
||||
return DI_PT_POLYGON;
|
||||
break;
|
||||
default:
|
||||
assert(0);
|
||||
return -1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static int evergreenNumVerts(int num_verts, int prim) //same
|
||||
{
|
||||
int verts_off = 0;
|
||||
|
||||
switch (prim & PRIM_MODE_MASK) {
|
||||
case GL_POINTS:
|
||||
verts_off = 0;
|
||||
break;
|
||||
case GL_LINES:
|
||||
verts_off = num_verts % 2;
|
||||
break;
|
||||
case GL_LINE_STRIP:
|
||||
if (num_verts < 2)
|
||||
verts_off = num_verts;
|
||||
break;
|
||||
case GL_LINE_LOOP:
|
||||
if (num_verts < 2)
|
||||
verts_off = num_verts;
|
||||
break;
|
||||
case GL_TRIANGLES:
|
||||
verts_off = num_verts % 3;
|
||||
break;
|
||||
case GL_TRIANGLE_STRIP:
|
||||
if (num_verts < 3)
|
||||
verts_off = num_verts;
|
||||
break;
|
||||
case GL_TRIANGLE_FAN:
|
||||
if (num_verts < 3)
|
||||
verts_off = num_verts;
|
||||
break;
|
||||
case GL_QUADS:
|
||||
verts_off = num_verts % 4;
|
||||
break;
|
||||
case GL_QUAD_STRIP:
|
||||
if (num_verts < 4)
|
||||
verts_off = num_verts;
|
||||
else
|
||||
verts_off = num_verts % 2;
|
||||
break;
|
||||
case GL_POLYGON:
|
||||
if (num_verts < 3)
|
||||
verts_off = num_verts;
|
||||
break;
|
||||
default:
|
||||
assert(0);
|
||||
return -1;
|
||||
break;
|
||||
}
|
||||
|
||||
return num_verts - verts_off;
|
||||
}
|
||||
|
||||
static void evergreenRunRenderPrimitive(GLcontext * ctx, int start, int end, int prim) //same
|
||||
{
|
||||
context_t *context = EVERGREEN_CONTEXT(ctx);
|
||||
BATCH_LOCALS(&context->radeon);
|
||||
int type, total_emit;
|
||||
int num_indices;
|
||||
uint32_t vgt_draw_initiator = 0;
|
||||
uint32_t vgt_index_type = 0;
|
||||
uint32_t vgt_primitive_type = 0;
|
||||
uint32_t vgt_num_indices = 0;
|
||||
|
||||
type = evergreenPrimitiveType(prim);
|
||||
num_indices = evergreenNumVerts(end - start, prim);
|
||||
|
||||
radeon_print(RADEON_RENDER, RADEON_TRACE,
|
||||
"%s type %x num_indices %d\n",
|
||||
__func__, type, num_indices);
|
||||
|
||||
if (type < 0 || num_indices <= 0)
|
||||
return;
|
||||
|
||||
SETfield(vgt_primitive_type, type,
|
||||
VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask);
|
||||
|
||||
SETfield(vgt_index_type, DI_INDEX_SIZE_32_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
|
||||
|
||||
if(GL_TRUE != context->ind_buf.is_32bit)
|
||||
{
|
||||
SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
|
||||
}
|
||||
|
||||
vgt_num_indices = num_indices;
|
||||
SETfield(vgt_draw_initiator, DI_SRC_SEL_DMA, SOURCE_SELECT_shift, SOURCE_SELECT_mask);
|
||||
SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask);
|
||||
|
||||
total_emit = 3 /* VGT_PRIMITIVE_TYPE */
|
||||
+ 2 /* VGT_INDEX_TYPE */
|
||||
+ 2 /* NUM_INSTANCES */
|
||||
+ 5 + 2; /* DRAW_INDEX */
|
||||
|
||||
BEGIN_BATCH_NO_AUTOSTATE(total_emit);
|
||||
// prim
|
||||
R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE, 1);
|
||||
R600_OUT_BATCH(vgt_primitive_type);
|
||||
// index type
|
||||
R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
|
||||
R600_OUT_BATCH(vgt_index_type);
|
||||
// num instances
|
||||
R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
|
||||
R600_OUT_BATCH(1);
|
||||
// draw packet
|
||||
R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX, 3));
|
||||
R600_OUT_BATCH(context->ind_buf.bo_offset);
|
||||
R600_OUT_BATCH(0);
|
||||
R600_OUT_BATCH(vgt_num_indices);
|
||||
R600_OUT_BATCH(vgt_draw_initiator);
|
||||
R600_OUT_BATCH_RELOC(context->ind_buf.bo_offset,
|
||||
context->ind_buf.bo,
|
||||
context->ind_buf.bo_offset,
|
||||
RADEON_GEM_DOMAIN_GTT, 0, 0);
|
||||
END_BATCH();
|
||||
COMMIT_BATCH();
|
||||
}
|
||||
|
||||
static void evergreenRunRenderPrimitiveImmediate(GLcontext * ctx, int start, int end, int prim) //same
|
||||
{
|
||||
context_t *context = EVERGREEN_CONTEXT(ctx);
|
||||
BATCH_LOCALS(&context->radeon);
|
||||
int type, i;
|
||||
uint32_t num_indices, total_emit = 0;
|
||||
uint32_t vgt_draw_initiator = 0;
|
||||
uint32_t vgt_index_type = 0;
|
||||
uint32_t vgt_primitive_type = 0;
|
||||
uint32_t vgt_num_indices = 0;
|
||||
|
||||
type = evergreenPrimitiveType(prim);
|
||||
num_indices = evergreenNumVerts(end - start, prim);
|
||||
|
||||
radeon_print(RADEON_RENDER, RADEON_TRACE,
|
||||
"%s type %x num_indices %d\n",
|
||||
__func__, type, num_indices);
|
||||
|
||||
if (type < 0 || num_indices <= 0)
|
||||
return;
|
||||
|
||||
SETfield(vgt_primitive_type, type,
|
||||
VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask);
|
||||
|
||||
if (num_indices > 0xffff)
|
||||
{
|
||||
SETfield(vgt_index_type, DI_INDEX_SIZE_32_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
|
||||
}
|
||||
else
|
||||
{
|
||||
SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
|
||||
}
|
||||
|
||||
vgt_num_indices = num_indices;
|
||||
SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask);
|
||||
|
||||
if (start == 0)
|
||||
{
|
||||
SETfield(vgt_draw_initiator, DI_SRC_SEL_AUTO_INDEX, SOURCE_SELECT_shift, SOURCE_SELECT_mask);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (num_indices > 0xffff)
|
||||
{
|
||||
total_emit += num_indices;
|
||||
}
|
||||
else
|
||||
{
|
||||
total_emit += (num_indices + 1) / 2;
|
||||
}
|
||||
SETfield(vgt_draw_initiator, DI_SRC_SEL_IMMEDIATE, SOURCE_SELECT_shift, SOURCE_SELECT_mask);
|
||||
}
|
||||
|
||||
total_emit += 3 /* VGT_PRIMITIVE_TYPE */
|
||||
+ 2 /* VGT_INDEX_TYPE */
|
||||
+ 2 /* NUM_INSTANCES */
|
||||
+ 3; /* DRAW */
|
||||
|
||||
BEGIN_BATCH_NO_AUTOSTATE(total_emit);
|
||||
// prim
|
||||
R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE, 1);
|
||||
R600_OUT_BATCH(vgt_primitive_type);
|
||||
// index type
|
||||
R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
|
||||
R600_OUT_BATCH(vgt_index_type);
|
||||
// num instances
|
||||
R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
|
||||
R600_OUT_BATCH(1);
|
||||
// draw packet
|
||||
if(start == 0)
|
||||
{
|
||||
R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1));
|
||||
R600_OUT_BATCH(vgt_num_indices);
|
||||
R600_OUT_BATCH(vgt_draw_initiator);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (num_indices > 0xffff)
|
||||
{
|
||||
R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (num_indices + 1)));
|
||||
R600_OUT_BATCH(vgt_num_indices);
|
||||
R600_OUT_BATCH(vgt_draw_initiator);
|
||||
for (i = start; i < (start + num_indices); i++)
|
||||
{
|
||||
R600_OUT_BATCH(i);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (((num_indices + 1) / 2) + 1)));
|
||||
R600_OUT_BATCH(vgt_num_indices);
|
||||
R600_OUT_BATCH(vgt_draw_initiator);
|
||||
for (i = start; i < (start + num_indices); i += 2)
|
||||
{
|
||||
if ((i + 1) == (start + num_indices))
|
||||
{
|
||||
R600_OUT_BATCH(i);
|
||||
}
|
||||
else
|
||||
{
|
||||
R600_OUT_BATCH(((i + 1) << 16) | (i));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
END_BATCH();
|
||||
COMMIT_BATCH();
|
||||
}
|
||||
|
||||
#define CONVERT( TYPE, MACRO ) do { \
|
||||
GLuint i, j, sz; \
|
||||
sz = input->Size; \
|
||||
if (input->Normalized) { \
|
||||
for (i = 0; i < count; i++) { \
|
||||
const TYPE *in = (TYPE *)src_ptr; \
|
||||
for (j = 0; j < sz; j++) { \
|
||||
*dst_ptr++ = MACRO(*in); \
|
||||
in++; \
|
||||
} \
|
||||
src_ptr += stride; \
|
||||
} \
|
||||
} else { \
|
||||
for (i = 0; i < count; i++) { \
|
||||
const TYPE *in = (TYPE *)src_ptr; \
|
||||
for (j = 0; j < sz; j++) { \
|
||||
*dst_ptr++ = (GLfloat)(*in); \
|
||||
in++; \
|
||||
} \
|
||||
src_ptr += stride; \
|
||||
} \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
/**
|
||||
* Convert attribute data type to float
|
||||
* If the attribute uses named buffer object replace the bo with newly allocated bo
|
||||
*/
|
||||
static void evergreenConvertAttrib(GLcontext *ctx, int count,
|
||||
const struct gl_client_array *input,
|
||||
struct StreamDesc *attr)
|
||||
{
|
||||
context_t *context = R700_CONTEXT(ctx);
|
||||
const GLvoid *src_ptr;
|
||||
GLboolean mapped_named_bo = GL_FALSE;
|
||||
GLfloat *dst_ptr;
|
||||
GLuint stride;
|
||||
|
||||
stride = (input->StrideB == 0) ? evergreen_getTypeSize(input->Type) * input->Size : input->StrideB;
|
||||
|
||||
/* Convert value for first element only */
|
||||
if (input->StrideB == 0)
|
||||
{
|
||||
count = 1;
|
||||
}
|
||||
|
||||
if (input->BufferObj->Name)
|
||||
{
|
||||
if (!input->BufferObj->Pointer)
|
||||
{
|
||||
ctx->Driver.MapBuffer(ctx, GL_ARRAY_BUFFER, GL_READ_ONLY_ARB, input->BufferObj);
|
||||
mapped_named_bo = GL_TRUE;
|
||||
}
|
||||
|
||||
src_ptr = ADD_POINTERS(input->BufferObj->Pointer, input->Ptr);
|
||||
}
|
||||
else
|
||||
{
|
||||
src_ptr = input->Ptr;
|
||||
}
|
||||
|
||||
radeonAllocDmaRegion(&context->radeon, &attr->bo, &attr->bo_offset,
|
||||
sizeof(GLfloat) * input->Size * count, 32);
|
||||
|
||||
radeon_bo_map(attr->bo, 1);
|
||||
|
||||
dst_ptr = (GLfloat *)ADD_POINTERS(attr->bo->ptr, attr->bo_offset);
|
||||
|
||||
assert(src_ptr != NULL);
|
||||
|
||||
switch (input->Type)
|
||||
{
|
||||
case GL_DOUBLE:
|
||||
CONVERT(GLdouble, (GLfloat));
|
||||
break;
|
||||
case GL_UNSIGNED_INT:
|
||||
CONVERT(GLuint, UINT_TO_FLOAT);
|
||||
break;
|
||||
case GL_INT:
|
||||
CONVERT(GLint, INT_TO_FLOAT);
|
||||
break;
|
||||
case GL_UNSIGNED_SHORT:
|
||||
CONVERT(GLushort, USHORT_TO_FLOAT);
|
||||
break;
|
||||
case GL_SHORT:
|
||||
CONVERT(GLshort, SHORT_TO_FLOAT);
|
||||
break;
|
||||
case GL_UNSIGNED_BYTE:
|
||||
assert(input->Format != GL_BGRA);
|
||||
CONVERT(GLubyte, UBYTE_TO_FLOAT);
|
||||
break;
|
||||
case GL_BYTE:
|
||||
CONVERT(GLbyte, BYTE_TO_FLOAT);
|
||||
break;
|
||||
default:
|
||||
assert(0);
|
||||
break;
|
||||
}
|
||||
|
||||
radeon_bo_unmap(attr->bo);
|
||||
|
||||
if (mapped_named_bo)
|
||||
{
|
||||
ctx->Driver.UnmapBuffer(ctx, GL_ARRAY_BUFFER, input->BufferObj);
|
||||
}
|
||||
}
|
||||
|
||||
static void evergreenFixupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer *mesa_ind_buf)
|
||||
{
|
||||
context_t *context = EVERGREEN_CONTEXT(ctx);
|
||||
GLvoid *src_ptr;
|
||||
GLuint *out;
|
||||
int i;
|
||||
GLboolean mapped_named_bo = GL_FALSE;
|
||||
|
||||
if (mesa_ind_buf->obj->Name && !mesa_ind_buf->obj->Pointer)
|
||||
{
|
||||
ctx->Driver.MapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER, GL_READ_ONLY_ARB, mesa_ind_buf->obj);
|
||||
mapped_named_bo = GL_TRUE;
|
||||
assert(mesa_ind_buf->obj->Pointer != NULL);
|
||||
}
|
||||
src_ptr = ADD_POINTERS(mesa_ind_buf->obj->Pointer, mesa_ind_buf->ptr);
|
||||
|
||||
if (mesa_ind_buf->type == GL_UNSIGNED_BYTE)
|
||||
{
|
||||
GLuint size = sizeof(GLushort) * ((mesa_ind_buf->count + 1) & ~1);
|
||||
GLubyte *in = (GLubyte *)src_ptr;
|
||||
|
||||
radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo,
|
||||
&context->ind_buf.bo_offset, size, 4);
|
||||
|
||||
radeon_bo_map(context->ind_buf.bo, 1);
|
||||
assert(context->ind_buf.bo->ptr != NULL);
|
||||
out = (GLuint *)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset);
|
||||
|
||||
for (i = 0; i + 1 < mesa_ind_buf->count; i += 2)
|
||||
{
|
||||
*out++ = in[i] | in[i + 1] << 16;
|
||||
}
|
||||
|
||||
if (i < mesa_ind_buf->count)
|
||||
{
|
||||
*out++ = in[i];
|
||||
}
|
||||
|
||||
radeon_bo_unmap(context->ind_buf.bo);
|
||||
#if MESA_BIG_ENDIAN
|
||||
}
|
||||
else
|
||||
{ /* if (mesa_ind_buf->type == GL_UNSIGNED_SHORT) */
|
||||
GLushort *in = (GLushort *)src_ptr;
|
||||
GLuint size = sizeof(GLushort) * ((mesa_ind_buf->count + 1) & ~1);
|
||||
|
||||
radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo,
|
||||
&context->ind_buf.bo_offset, size, 4);
|
||||
|
||||
radeon_bo_map(context->ind_buf.bo, 1);
|
||||
assert(context->ind_buf.bo->ptr != NULL);
|
||||
out = (GLuint *)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset);
|
||||
|
||||
for (i = 0; i + 1 < mesa_ind_buf->count; i += 2)
|
||||
{
|
||||
*out++ = in[i] | in[i + 1] << 16;
|
||||
}
|
||||
|
||||
if (i < mesa_ind_buf->count)
|
||||
{
|
||||
*out++ = in[i];
|
||||
}
|
||||
radeon_bo_unmap(context->ind_buf.bo);
|
||||
#endif
|
||||
}
|
||||
|
||||
context->ind_buf.is_32bit = GL_FALSE;
|
||||
context->ind_buf.count = mesa_ind_buf->count;
|
||||
|
||||
if (mapped_named_bo)
|
||||
{
|
||||
ctx->Driver.UnmapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER, mesa_ind_buf->obj);
|
||||
}
|
||||
}
|
||||
|
||||
static GLboolean evergreen_check_fallbacks(GLcontext *ctx) //same
|
||||
{
|
||||
if (ctx->RenderMode != GL_RENDER)
|
||||
return GL_TRUE;
|
||||
|
||||
return GL_FALSE;
|
||||
}
|
||||
|
||||
/* start 3d, idle, cb/db flush */
|
||||
#define PRE_EMIT_STATE_BUFSZ 5 + 5 + 14
|
||||
|
||||
static GLuint evergreenPredictRenderSize(GLcontext* ctx,
|
||||
const struct _mesa_prim *prim,
|
||||
const struct _mesa_index_buffer *ib,
|
||||
GLuint nr_prims)
|
||||
{
|
||||
context_t *context = EVERGREEN_CONTEXT(ctx);
|
||||
GLboolean flushed;
|
||||
GLuint dwords, i;
|
||||
GLuint state_size;
|
||||
|
||||
dwords = PRE_EMIT_STATE_BUFSZ;
|
||||
if (ib)
|
||||
dwords += nr_prims * 14;
|
||||
else {
|
||||
for (i = 0; i < nr_prims; ++i)
|
||||
{
|
||||
if (prim[i].start == 0)
|
||||
dwords += 10;
|
||||
else if (prim[i].count > 0xffff)
|
||||
dwords += prim[i].count + 10;
|
||||
else
|
||||
dwords += ((prim[i].count + 1) / 2) + 10;
|
||||
}
|
||||
}
|
||||
|
||||
state_size = radeonCountStateEmitSize(&context->radeon);
|
||||
flushed = rcommonEnsureCmdBufSpace(&context->radeon,
|
||||
dwords + state_size,
|
||||
__FUNCTION__);
|
||||
if (flushed)
|
||||
dwords += radeonCountStateEmitSize(&context->radeon);
|
||||
else
|
||||
dwords += state_size;
|
||||
|
||||
radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s: total prediction size is %d.\n", __FUNCTION__, dwords);
|
||||
return dwords;
|
||||
|
||||
}
|
||||
|
||||
static void evergreenSetupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer *mesa_ind_buf)
|
||||
{
|
||||
context_t *context = EVERGREEN_CONTEXT(ctx);
|
||||
|
||||
if (!mesa_ind_buf) {
|
||||
context->ind_buf.bo = NULL;
|
||||
return;
|
||||
}
|
||||
|
||||
#if MESA_BIG_ENDIAN
|
||||
if (mesa_ind_buf->type == GL_UNSIGNED_INT)
|
||||
#else
|
||||
if (mesa_ind_buf->type != GL_UNSIGNED_BYTE)
|
||||
#endif
|
||||
{
|
||||
const GLvoid *src_ptr;
|
||||
GLvoid *dst_ptr;
|
||||
GLboolean mapped_named_bo = GL_FALSE;
|
||||
|
||||
if (mesa_ind_buf->obj->Name && !mesa_ind_buf->obj->Pointer)
|
||||
{
|
||||
ctx->Driver.MapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER, GL_READ_ONLY_ARB, mesa_ind_buf->obj);
|
||||
assert(mesa_ind_buf->obj->Pointer != NULL);
|
||||
mapped_named_bo = GL_TRUE;
|
||||
}
|
||||
|
||||
src_ptr = ADD_POINTERS(mesa_ind_buf->obj->Pointer, mesa_ind_buf->ptr);
|
||||
|
||||
const GLuint size = mesa_ind_buf->count * getTypeSize(mesa_ind_buf->type);
|
||||
|
||||
radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo,
|
||||
&context->ind_buf.bo_offset, size, 4);
|
||||
radeon_bo_map(context->ind_buf.bo, 1);
|
||||
assert(context->ind_buf.bo->ptr != NULL);
|
||||
dst_ptr = ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset);
|
||||
|
||||
memcpy(dst_ptr, src_ptr, size);
|
||||
|
||||
radeon_bo_unmap(context->ind_buf.bo);
|
||||
context->ind_buf.is_32bit = (mesa_ind_buf->type == GL_UNSIGNED_INT);
|
||||
context->ind_buf.count = mesa_ind_buf->count;
|
||||
|
||||
if (mapped_named_bo)
|
||||
{
|
||||
ctx->Driver.UnmapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER, mesa_ind_buf->obj);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
evergreenFixupIndexBuffer(ctx, mesa_ind_buf);
|
||||
}
|
||||
}
|
||||
|
||||
static void evergreenAlignDataToDword(GLcontext *ctx,
|
||||
const struct gl_client_array *input,
|
||||
int count,
|
||||
struct StreamDesc *attr)
|
||||
{
|
||||
context_t *context = EVERGREEN_CONTEXT(ctx);
|
||||
const int dst_stride = (input->StrideB + 3) & ~3;
|
||||
const int size = getTypeSize(input->Type) * input->Size * count;
|
||||
GLboolean mapped_named_bo = GL_FALSE;
|
||||
|
||||
radeonAllocDmaRegion(&context->radeon, &attr->bo, &attr->bo_offset, size, 32);
|
||||
|
||||
radeon_bo_map(attr->bo, 1);
|
||||
|
||||
if (!input->BufferObj->Pointer)
|
||||
{
|
||||
ctx->Driver.MapBuffer(ctx, GL_ARRAY_BUFFER, GL_READ_ONLY_ARB, input->BufferObj);
|
||||
mapped_named_bo = GL_TRUE;
|
||||
}
|
||||
|
||||
{
|
||||
GLvoid *src_ptr = ADD_POINTERS(input->BufferObj->Pointer, input->Ptr);
|
||||
GLvoid *dst_ptr = ADD_POINTERS(attr->bo->ptr, attr->bo_offset);
|
||||
int i;
|
||||
|
||||
for (i = 0; i < count; ++i)
|
||||
{
|
||||
memcpy(dst_ptr, src_ptr, input->StrideB);
|
||||
src_ptr += input->StrideB;
|
||||
dst_ptr += dst_stride;
|
||||
}
|
||||
}
|
||||
|
||||
radeon_bo_unmap(attr->bo);
|
||||
if (mapped_named_bo)
|
||||
{
|
||||
ctx->Driver.UnmapBuffer(ctx, GL_ARRAY_BUFFER, input->BufferObj);
|
||||
}
|
||||
|
||||
attr->stride = dst_stride;
|
||||
}
|
||||
|
||||
static void evergreenSetupStreams(GLcontext *ctx, const struct gl_client_array *input[], int count)
|
||||
{
|
||||
context_t *context = EVERGREEN_CONTEXT(ctx);
|
||||
GLuint stride;
|
||||
int ret;
|
||||
int i, index;
|
||||
|
||||
EVERGREEN_STATECHANGE(context, vtx);
|
||||
|
||||
for(index = 0; index < context->nNumActiveAos; index++)
|
||||
{
|
||||
struct radeon_aos *aos = &context->radeon.tcl.aos[index];
|
||||
i = context->stream_desc[index].element;
|
||||
|
||||
stride = (input[i]->StrideB == 0) ? getTypeSize(input[i]->Type) * input[i]->Size : input[i]->StrideB;
|
||||
|
||||
if (input[i]->Type == GL_DOUBLE || input[i]->Type == GL_UNSIGNED_INT || input[i]->Type == GL_INT ||
|
||||
#if MESA_BIG_ENDIAN
|
||||
getTypeSize(input[i]->Type) != 4 ||
|
||||
#endif
|
||||
stride < 4)
|
||||
{
|
||||
evergreenConvertAttrib(ctx, count, input[i], &context->stream_desc[index]);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (input[i]->BufferObj->Name)
|
||||
{
|
||||
if (stride % 4 != 0)
|
||||
{
|
||||
assert(((intptr_t) input[i]->Ptr) % input[i]->StrideB == 0);
|
||||
evergreenAlignDataToDword(ctx, input[i], count, &context->stream_desc[index]);
|
||||
context->stream_desc[index].is_named_bo = GL_FALSE;
|
||||
}
|
||||
else
|
||||
{
|
||||
context->stream_desc[index].stride = input[i]->StrideB;
|
||||
context->stream_desc[index].bo_offset = (intptr_t) input[i]->Ptr;
|
||||
context->stream_desc[index].bo = get_radeon_buffer_object(input[i]->BufferObj)->bo;
|
||||
context->stream_desc[index].is_named_bo = GL_TRUE;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
int size;
|
||||
int local_count = count;
|
||||
uint32_t *dst;
|
||||
|
||||
if (input[i]->StrideB == 0)
|
||||
{
|
||||
size = getTypeSize(input[i]->Type) * input[i]->Size;
|
||||
local_count = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
size = getTypeSize(input[i]->Type) * input[i]->Size * local_count;
|
||||
}
|
||||
|
||||
radeonAllocDmaRegion(&context->radeon, &context->stream_desc[index].bo,
|
||||
&context->stream_desc[index].bo_offset, size, 32);
|
||||
|
||||
radeon_bo_map(context->stream_desc[index].bo, 1);
|
||||
assert(context->stream_desc[index].bo->ptr != NULL);
|
||||
|
||||
|
||||
dst = (uint32_t *)ADD_POINTERS(context->stream_desc[index].bo->ptr,
|
||||
context->stream_desc[index].bo_offset);
|
||||
|
||||
switch (context->stream_desc[index].dwords)
|
||||
{
|
||||
case 1:
|
||||
radeonEmitVec4(dst, input[i]->Ptr, input[i]->StrideB, local_count);
|
||||
break;
|
||||
case 2:
|
||||
radeonEmitVec8(dst, input[i]->Ptr, input[i]->StrideB, local_count);
|
||||
break;
|
||||
case 3:
|
||||
radeonEmitVec12(dst, input[i]->Ptr, input[i]->StrideB, local_count);
|
||||
break;
|
||||
case 4:
|
||||
radeonEmitVec16(dst, input[i]->Ptr, input[i]->StrideB, local_count);
|
||||
break;
|
||||
default:
|
||||
assert(0);
|
||||
break;
|
||||
}
|
||||
|
||||
radeon_bo_unmap(context->stream_desc[index].bo);
|
||||
}
|
||||
}
|
||||
|
||||
aos->count = context->stream_desc[index].stride == 0 ? 1 : count;
|
||||
aos->stride = context->stream_desc[index].stride / sizeof(float);
|
||||
aos->components = context->stream_desc[index].dwords;
|
||||
aos->bo = context->stream_desc[index].bo;
|
||||
aos->offset = context->stream_desc[index].bo_offset;
|
||||
|
||||
if(context->stream_desc[index].is_named_bo)
|
||||
{
|
||||
radeon_cs_space_add_persistent_bo(context->radeon.cmdbuf.cs,
|
||||
context->stream_desc[index].bo,
|
||||
RADEON_GEM_DOMAIN_GTT, 0);
|
||||
}
|
||||
}
|
||||
|
||||
ret = radeon_cs_space_check_with_bo(context->radeon.cmdbuf.cs,
|
||||
first_elem(&context->radeon.dma.reserved)->bo,
|
||||
RADEON_GEM_DOMAIN_GTT, 0);
|
||||
}
|
||||
|
||||
static void evergreenFreeData(GLcontext *ctx)
|
||||
{
|
||||
/* Need to zero tcl.aos[n].bo and tcl.elt_dma_bo
|
||||
* to prevent double unref in radeonReleaseArrays
|
||||
* called during context destroy
|
||||
*/
|
||||
context_t *context = EVERGREEN_CONTEXT(ctx);
|
||||
|
||||
int i;
|
||||
|
||||
for (i = 0; i < context->nNumActiveAos; i++)
|
||||
{
|
||||
if (!context->stream_desc[i].is_named_bo)
|
||||
{
|
||||
radeon_bo_unref(context->stream_desc[i].bo);
|
||||
}
|
||||
context->radeon.tcl.aos[i].bo = NULL;
|
||||
}
|
||||
|
||||
if(context->vp_Constbo != NULL)
|
||||
{
|
||||
radeon_bo_unref(context->vp_Constbo);
|
||||
context->vp_Constbo = NULL;
|
||||
}
|
||||
if(context->fp_Constbo != NULL)
|
||||
{
|
||||
radeon_bo_unref(context->fp_Constbo);
|
||||
context->fp_Constbo = NULL;
|
||||
}
|
||||
|
||||
if (context->ind_buf.bo != NULL)
|
||||
{
|
||||
radeon_bo_unref(context->ind_buf.bo);
|
||||
}
|
||||
}
|
||||
|
||||
static GLboolean evergreenTryDrawPrims(GLcontext *ctx,
|
||||
const struct gl_client_array *arrays[],
|
||||
const struct _mesa_prim *prim,
|
||||
GLuint nr_prims,
|
||||
const struct _mesa_index_buffer *ib,
|
||||
GLuint min_index,
|
||||
GLuint max_index )
|
||||
{
|
||||
context_t *context = EVERGREEN_CONTEXT(ctx);
|
||||
radeonContextPtr radeon = &context->radeon;
|
||||
GLuint i, id = 0;
|
||||
struct radeon_renderbuffer *rrb;
|
||||
|
||||
if (ctx->NewState)
|
||||
_mesa_update_state( ctx );
|
||||
|
||||
if (evergreen_check_fallbacks(ctx))
|
||||
return GL_FALSE;
|
||||
|
||||
_tnl_UpdateFixedFunctionProgram(ctx);
|
||||
evergreenSetVertexFormat(ctx, arrays, max_index + 1);
|
||||
|
||||
|
||||
/* shaders need to be updated before buffers are validated */
|
||||
evergreenUpdateShaders(ctx);
|
||||
if (!evergreenValidateBuffers(ctx))
|
||||
return GL_FALSE;
|
||||
|
||||
/* always emit CB base to prevent
|
||||
* lock ups on some chips.
|
||||
*/
|
||||
EVERGREEN_STATECHANGE(context, cb);
|
||||
/* mark vtx as dirty since it changes per-draw */
|
||||
EVERGREEN_STATECHANGE(context, vtx);
|
||||
|
||||
evergreenSetScissor(context);
|
||||
|
||||
evergreenSetupVertexProgram(ctx);
|
||||
evergreenSetupFragmentProgram(ctx);
|
||||
evergreenUpdateShaderStates(ctx);
|
||||
|
||||
GLuint emit_end = evergreenPredictRenderSize(ctx, prim, ib, nr_prims)
|
||||
+ context->radeon.cmdbuf.cs->cdw;
|
||||
|
||||
evergreenSetupIndexBuffer(ctx, ib);
|
||||
|
||||
evergreenSetupStreams(ctx, arrays, max_index + 1);
|
||||
|
||||
radeonEmitState(radeon);
|
||||
|
||||
radeon_debug_add_indent();
|
||||
|
||||
for (i = 0; i < nr_prims; ++i)
|
||||
{
|
||||
/* richard test disable */
|
||||
#if 0
|
||||
if (context->ind_buf.bo)
|
||||
evergreenRunRenderPrimitive(ctx,
|
||||
prim[i].start,
|
||||
prim[i].start + prim[i].count,
|
||||
prim[i].mode);
|
||||
else
|
||||
#endif //0
|
||||
//-------------
|
||||
evergreenRunRenderPrimitiveImmediate(ctx,
|
||||
prim[i].start,
|
||||
prim[i].start + prim[i].count,
|
||||
prim[i].mode);
|
||||
}
|
||||
|
||||
radeon_debug_remove_indent();
|
||||
|
||||
/* Flush render op cached for last several quads. */
|
||||
/* XXX drm should handle this in fence submit */
|
||||
|
||||
//evergreeWaitForIdleClean(context);
|
||||
|
||||
rrb = radeon_get_colorbuffer(&context->radeon);
|
||||
if (rrb && rrb->bo)
|
||||
r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM,
|
||||
CB_ACTION_ENA_bit | (1 << (id + 6)));
|
||||
|
||||
rrb = radeon_get_depthbuffer(&context->radeon);
|
||||
if (rrb && rrb->bo)
|
||||
r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM,
|
||||
DB_ACTION_ENA_bit | DB_DEST_BASE_ENA_bit);
|
||||
|
||||
evergreenFreeData(ctx);
|
||||
|
||||
if (emit_end < context->radeon.cmdbuf.cs->cdw)
|
||||
{
|
||||
WARN_ONCE("Rendering was %d commands larger than predicted size."
|
||||
" We might overflow command buffer.\n", context->radeon.cmdbuf.cs->cdw - emit_end);
|
||||
}
|
||||
|
||||
return GL_TRUE;
|
||||
}
|
||||
|
||||
static void evergreenDrawPrims(GLcontext *ctx,
|
||||
const struct gl_client_array *arrays[],
|
||||
const struct _mesa_prim *prim,
|
||||
GLuint nr_prims,
|
||||
const struct _mesa_index_buffer *ib,
|
||||
GLboolean index_bounds_valid,
|
||||
GLuint min_index,
|
||||
GLuint max_index)
|
||||
{
|
||||
GLboolean retval = GL_FALSE;
|
||||
|
||||
/* This check should get folded into just the places that
|
||||
* min/max index are really needed.
|
||||
*/
|
||||
if (!index_bounds_valid) {
|
||||
vbo_get_minmax_index(ctx, prim, ib, &min_index, &max_index);
|
||||
}
|
||||
|
||||
if (min_index) {
|
||||
vbo_rebase_prims( ctx, arrays, prim, nr_prims, ib, min_index, max_index, evergreenDrawPrims );
|
||||
return;
|
||||
}
|
||||
|
||||
/* Make an attempt at drawing */
|
||||
retval = evergreenTryDrawPrims(ctx, arrays, prim, nr_prims, ib, min_index, max_index);
|
||||
|
||||
/* If failed run tnl pipeline - it should take care of fallbacks */
|
||||
if (!retval) {
|
||||
_swsetup_Wakeup(ctx);
|
||||
_tnl_draw_prims(ctx, arrays, prim, nr_prims, ib, min_index, max_index);
|
||||
}
|
||||
}
|
||||
|
||||
void evergreenInitDraw(GLcontext *ctx)
|
||||
{
|
||||
struct vbo_context *vbo = vbo_context(ctx);
|
||||
|
||||
/* to be enabled */
|
||||
vbo->draw_prims = evergreenDrawPrims;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,735 @@
|
|||
/*
|
||||
* Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Authors:
|
||||
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef _EVERGREEN_SQ_H_
|
||||
#define _EVERGREEN_SQ_H_
|
||||
|
||||
enum{
|
||||
//CF
|
||||
EG_CF_WORD0__ADDR_shift = 0,
|
||||
EG_CF_WORD0__ADDR_mask = 0xFFFFFF,
|
||||
EG_CF_WORD0__JUMPTABLE_SEL_shift = 24,
|
||||
EG_CF_WORD0__JUMPTABLE_SEL_mask = 0x7 << 24,
|
||||
|
||||
EG_CF_WORD1__POP_COUNT_shift = 0, //3 bits
|
||||
EG_CF_WORD1__POP_COUNT_mask = 0x7,
|
||||
EG_CF_WORD1__CF_CONST_shift = 3, //5 bits
|
||||
EG_CF_WORD1__CF_CONST_mask = 0x1F << 3,
|
||||
EG_CF_WORD1__COND_shift = 8, //2 bits
|
||||
EG_CF_WORD1__COND_mask = 0x3 << 8,
|
||||
EG_CF_WORD1__COUNT_shift = 10,//6 bits
|
||||
EG_CF_WORD1__COUNT_mask = 0x3F << 10,
|
||||
EG_CF_WORD1__reserved_shift = 16,//4 bits
|
||||
EG_CF_WORD1__VPM_shift = 20,//1 bit
|
||||
EG_CF_WORD1__VPM_bit = 1 << 20,
|
||||
EG_CF_WORD1__EOP_shift = 21,//1 bit
|
||||
EG_CF_WORD1__EOP_bit = 1 << 21,
|
||||
EG_CF_WORD1__CF_INST_shift = 22,//8 bits
|
||||
EG_CF_WORD1__CF_INST_mask = 0xFF << 22,
|
||||
EG_CF_WORD1__WQM_shift = 30,//1 bit
|
||||
EG_CF_WORD1__WQM_bit = 1 << 30,
|
||||
EG_CF_WORD1__BARRIER_shift = 31,//1 bit
|
||||
EG_CF_WORD1__BARRIER_bit = 1 << 31,
|
||||
|
||||
EG_CF_INST_NOP = 0,
|
||||
EG_CF_INST_TC = 1,
|
||||
EG_CF_INST_VC = 2,
|
||||
EG_CF_INST_GDS = 3,
|
||||
EG_CF_INST_LOOP_START = 4,
|
||||
EG_CF_INST_LOOP_END = 5,
|
||||
EG_CF_INST_LOOP_START_DX10 = 6,
|
||||
EG_CF_INST_LOOP_START_NO_AL = 7,
|
||||
EG_CF_INST_LOOP_CONTINUE = 8,
|
||||
EG_CF_INST_LOOP_BREAK = 9,
|
||||
EG_CF_INST_JUMP = 10,
|
||||
EG_CF_INST_PUSH = 11,
|
||||
EG_CF_INST_Reserved_12 = 12,
|
||||
EG_CF_INST_ELSE = 13,
|
||||
EG_CF_INST_POP = 14,
|
||||
EG_CF_INST_Reserved_15 = 15,
|
||||
EG_CF_INST_Reserved_16 = 16,
|
||||
EG_CF_INST_Reserved_17 = 17,
|
||||
EG_CF_INST_CALL = 18,
|
||||
EG_CF_INST_CALL_FS = 19,
|
||||
EG_CF_INST_RETURN = 20,
|
||||
EG_CF_INST_EMIT_VERTEX = 21,
|
||||
EG_CF_INST_EMIT_CUT_VERTEX = 22,
|
||||
EG_CF_INST_CUT_VERTEX = 23,
|
||||
EG_CF_INST_KILL = 24,
|
||||
EG_CF_INST_Reserved_25 = 25,
|
||||
EG_CF_INST_WAIT_ACK = 26,
|
||||
EG_CF_INST_TC_ACK = 27,
|
||||
EG_CF_INST_VC_ACK = 28,
|
||||
EG_CF_INST_JUMPTABLE = 29,
|
||||
EG_CF_INST_GLOBAL_WAVE_SYNC = 30,
|
||||
EG_CF_INST_HALT = 31,
|
||||
|
||||
//TEX
|
||||
EG_TEX_WORD0__TEX_INST_shift = 0, //5 bits
|
||||
EG_TEX_WORD0__TEX_INST_mask = 0x1F,
|
||||
EG_TEX_WORD0__INST_MOD_shift = 5, //2 bits
|
||||
EG_TEX_WORD0__INST_MOD_mask = 0x3 << 5,
|
||||
EG_TEX_WORD0__FWQ_shift = 7, //1 bit
|
||||
EG_TEX_WORD0__FWQ_bit = 1 << 7,
|
||||
EG_TEX_WORD0__RESOURCE_ID_shift = 8, //8 bits
|
||||
EG_TEX_WORD0__RESOURCE_ID_mask = 0xFF << 8,
|
||||
EG_TEX_WORD0__SRC_GPR_shift = 16,//7 bits
|
||||
EG_TEX_WORD0__SRC_GPR_mask = 0x7F << 16,
|
||||
EG_TEX_WORD0__SRC_REL_shift = 23,//1 bit
|
||||
EG_TEX_WORD0__SRC_REL_bit = 1 << 23,
|
||||
EG_TEX_WORD0__ALT_CONST_shift = 24,//1 bit
|
||||
EG_TEX_WORD0__ALT_CONST_bit = 1 << 24,
|
||||
EG_TEX_WORD0__RIM_shift = 25,//2 bits
|
||||
EG_TEX_WORD0__RIM_mask = 0x3 << 25,
|
||||
EG_TEX_WORD0__SIM_shift = 27,//2 bits
|
||||
EG_TEX_WORD0__SIM_mask = 0x3 << 27,
|
||||
EG_TEX_WORD0__Reserved_shift = 29,//3 bits
|
||||
EG_TEX_WORD0__Reserved_mask = 0x7 << 29,
|
||||
|
||||
EG_TEX_INST_Reserved_0 = 0,
|
||||
EG_TEX_INST_Reserved_1 = 1,
|
||||
EG_TEX_INST_Reserved_2 = 2,
|
||||
EG_TEX_INST_LD = 3,
|
||||
EG_TEX_INST_GET_TEXTURE_RESINFO = 4,
|
||||
EG_TEX_INST_GET_NUMBER_OF_SAMPLES= 5,
|
||||
EG_TEX_INST_GET_COMP_TEX_LOD = 6,
|
||||
EG_TEX_INST_GET_GRADIENTS_H = 7,
|
||||
EG_TEX_INST_GET_GRADIENTS_V = 8,
|
||||
EG_TEX_INST_SET_TEXTURE_OFFSETS = 9,
|
||||
EG_TEX_INST_KEEP_GRADIENTS = 10,
|
||||
EG_TEX_INST_SET_GRADIENTS_H = 11,
|
||||
EG_TEX_INST_SET_GRADIENTS_V = 12,
|
||||
EG_TEX_INST_Reserved_13 = 13,
|
||||
EG_TEX_INST_Reserved_14 = 14,
|
||||
EG_TEX_INST_Reserved_15 = 15,
|
||||
EG_TEX_INST_SAMPLE = 16,
|
||||
EG_TEX_INST_SAMPLE_L = 17,
|
||||
EG_TEX_INST_SAMPLE_LB = 18,
|
||||
EG_TEX_INST_SAMPLE_LZ = 19,
|
||||
EG_TEX_INST_SAMPLE_G = 20,
|
||||
EG_TEX_INST_GATHER4 = 21,
|
||||
EG_TEX_INST_SAMPLE_G_LB = 22,
|
||||
EG_TEX_INST_GATHER4_O = 23,
|
||||
EG_TEX_INST_SAMPLE_C = 24,
|
||||
EG_TEX_INST_SAMPLE_C_L = 25,
|
||||
EG_TEX_INST_SAMPLE_C_LB = 26,
|
||||
EG_TEX_INST_SAMPLE_C_LZ = 27,
|
||||
EG_TEX_INST_SAMPLE_C_G = 28,
|
||||
EG_TEX_INST_GATHER4_C = 29,
|
||||
EG_TEX_INST_SAMPLE_C_G_LB = 30,
|
||||
EG_TEX_INST_GATHER4_C_O = 31,
|
||||
|
||||
EG_TEX_WORD1__DST_GPR_shift = 0, //7 bits
|
||||
EG_TEX_WORD1__DST_GPR_mask = 0x7F,
|
||||
EG_TEX_WORD1__DST_REL_shift = 7, //1 bit
|
||||
EG_TEX_WORD1__DST_REL_bit = 1 << 7,
|
||||
EG_TEX_WORD1__Reserved_shift = 8, //1 bit
|
||||
EG_TEX_WORD1__Reserved_bit = 1 << 8,
|
||||
EG_TEX_WORD1__DST_SEL_X_shift = 9, //3 bits
|
||||
EG_TEX_WORD1__DST_SEL_X_mask = 0x7 << 9,
|
||||
EG_TEX_WORD1__DST_SEL_Y_shift = 12,//3 bits
|
||||
EG_TEX_WORD1__DST_SEL_Y_mask = 0x7 << 12,
|
||||
EG_TEX_WORD1__DST_SEL_Z_shift = 15,//3 bits
|
||||
EG_TEX_WORD1__DST_SEL_Z_mask = 0x7 << 15,
|
||||
EG_TEX_WORD1__DST_SEL_W_shift = 18,//3 bits
|
||||
EG_TEX_WORD1__DST_SEL_W_mask = 0x7 << 18,
|
||||
EG_TEX_WORD1__LOD_BIAS_shift = 21,//7 bits
|
||||
EG_TEX_WORD1__LOD_BIAS_mask = 0x7F << 21,
|
||||
EG_TEX_WORD1__COORD_TYPE_X_shift = 28,//1 bit
|
||||
EG_TEX_WORD1__COORD_TYPE_X_bit = 1 << 28,
|
||||
EG_TEX_WORD1__COORD_TYPE_Y_shift = 29,//1 bit
|
||||
EG_TEX_WORD1__COORD_TYPE_Y_bit = 1 << 29,
|
||||
EG_TEX_WORD1__COORD_TYPE_Z_shift = 30,//1 bit
|
||||
EG_TEX_WORD1__COORD_TYPE_Z_bit = 1 << 30,
|
||||
EG_TEX_WORD1__COORD_TYPE_W_shift = 31,//1 bit
|
||||
EG_TEX_WORD1__COORD_TYPE_W_bit = 1 << 31,
|
||||
|
||||
EG_TEX_WORD2__OFFSET_X_shift = 0, //5 bits
|
||||
EG_TEX_WORD2__OFFSET_X_mask = 0x1F,
|
||||
EG_TEX_WORD2__OFFSET_Y_shift = 5, //5 bits
|
||||
EG_TEX_WORD2__OFFSET_Y_mask = 0x1F << 5,
|
||||
EG_TEX_WORD2__OFFSET_Z_shift = 10,//5 bits
|
||||
EG_TEX_WORD2__OFFSET_Z_mask = 0x1F << 10,
|
||||
EG_TEX_WORD2__SAMPLER_ID_shift = 15,//5 bits
|
||||
EG_TEX_WORD2__SAMPLER_ID_mask = 0x1F << 15,
|
||||
EG_TEX_WORD2__SRC_SEL_X_shift = 20,//3 bits
|
||||
EG_TEX_WORD2__SRC_SEL_X_mask = 0x7 << 20,
|
||||
EG_TEX_WORD2__SRC_SEL_Y_shift = 23,//3 bits
|
||||
EG_TEX_WORD2__SRC_SEL_Y_mask = 0x7 << 23,
|
||||
EG_TEX_WORD2__SRC_SEL_Z_shift = 26,//3 bits
|
||||
EG_TEX_WORD2__SRC_SEL_Z_mask = 0x7 << 26,
|
||||
EG_TEX_WORD2__SRC_SEL_W_shift = 29,//3 bits
|
||||
EG_TEX_WORD2__SRC_SEL_W_mask = 0x7 << 29,
|
||||
|
||||
//VTX
|
||||
EG_VTX_WORD0__VC_INST_shift = 0, //5 bits
|
||||
EG_VTX_WORD0__VC_INST_mask = 0x1F,
|
||||
EG_VTX_WORD0__FETCH_TYPE_shift = 5, //2 bits
|
||||
EG_VTX_WORD0__FETCH_TYPE_mask = 0x3 << 5,
|
||||
EG_VTX_WORD0__FWQ_shift = 7, //1 bit
|
||||
EG_VTX_WORD0__FWQ_bit = 1 << 7,
|
||||
EG_VTX_WORD0__BUFFER_ID_shift = 8, //8 bits
|
||||
EG_VTX_WORD0__BUFFER_ID_mask = 0xFF << 8,
|
||||
EG_VTX_WORD0__SRC_GPR_shift = 16,//7 bits
|
||||
EG_VTX_WORD0__SRC_GPR_mask = 0x7F << 16,
|
||||
EG_VTX_WORD0__SRC_REL_shift = 23,//1 bit
|
||||
EG_VTX_WORD0__SRC_REL_bit = 1 << 23,
|
||||
EG_VTX_WORD0__SRC_SEL_X_shift = 24,//2 bits
|
||||
EG_VTX_WORD0__SRC_SEL_X_mask = 0x3 << 24,
|
||||
EG_VTX_WORD0__MFC_shift = 26,//6 bits
|
||||
EG_VTX_WORD0__MFC_mask = 0x3F << 26,
|
||||
|
||||
EG_VC_INST_FETCH = 0,
|
||||
EG_VC_INST_SEMANTIC = 1,
|
||||
EG_VC_INST_Reserved_2 = 2,
|
||||
EG_VC_INST_Reserved_3 = 3,
|
||||
EG_VC_INST_Reserved_4 = 4,
|
||||
EG_VC_INST_Reserved_5 = 5,
|
||||
EG_VC_INST_Reserved_6 = 6,
|
||||
EG_VC_INST_Reserved_7 = 7,
|
||||
EG_VC_INST_Reserved_8 = 8,
|
||||
EG_VC_INST_Reserved_9 = 9,
|
||||
EG_VC_INST_Reserved_10 = 10,
|
||||
EG_VC_INST_Reserved_11 = 11,
|
||||
EG_VC_INST_Reserved_12 = 12,
|
||||
EG_VC_INST_Reserved_13 = 13,
|
||||
EG_VC_INST_GET_BUFFER_RESINFO = 14,
|
||||
|
||||
EG_VTX_FETCH_VERTEX_DATA = 0,
|
||||
EG_VTX_FETCH_INSTANCE_DATA = 1,
|
||||
EG_VTX_FETCH_NO_INDEX_OFFSET = 2,
|
||||
|
||||
EG_VTX_WORD1_SEM__SEMANTIC_ID_shift = 0, //8 bits
|
||||
EG_VTX_WORD1_SEM__SEMANTIC_ID_mask = 0xFF,
|
||||
EG_VTX_WORD1_GPR__DST_GPR_shift = 0, //7 bits
|
||||
EG_VTX_WORD1_GPR__DST_GPR_mask = 0x7F,
|
||||
EG_VTX_WORD1_GPR__DST_REL_shift = 7, //1 bit
|
||||
EG_VTX_WORD1_GPR__DST_REL_bit = 1 << 7,
|
||||
EG_VTX_WORD1__Reserved_shift = 8, //1 bit
|
||||
EG_VTX_WORD1__Reserved_bit = 1 << 8,
|
||||
EG_VTX_WORD1__DST_SEL_X_shift = 9, //3 bits
|
||||
EG_VTX_WORD1__DST_SEL_X_mask = 0x7 << 9,
|
||||
EG_VTX_WORD1__DST_SEL_Y_shift = 12,//3 bits
|
||||
EG_VTX_WORD1__DST_SEL_Y_mask = 0x7 << 12,
|
||||
EG_VTX_WORD1__DST_SEL_Z_shift = 15,//3 bits
|
||||
EG_VTX_WORD1__DST_SEL_Z_mask = 0x7 << 15,
|
||||
EG_VTX_WORD1__DST_SEL_W_shift = 18,//3 bits
|
||||
EG_VTX_WORD1__DST_SEL_W_mask = 0x7 << 18,
|
||||
EG_VTX_WORD1__UCF_shift = 21,//1 bit
|
||||
EG_VTX_WORD1__UCF_bit = 1 << 21,
|
||||
EG_VTX_WORD1__DATA_FORMAT_shift = 22,//6 bits
|
||||
EG_VTX_WORD1__DATA_FORMAT_mask = 0x3F << 22,
|
||||
EG_VTX_WORD1__NFA_shift = 28,//2 bits
|
||||
EG_VTX_WORD1__NFA_mask = 0x3 << 28,
|
||||
EG_VTX_WORD1__FCA_shift = 30,//1 bit
|
||||
EG_VTX_WORD1__FCA_bit = 1 << 30,
|
||||
EG_VTX_WORD1__SMA_shift = 31,//1 bit
|
||||
EG_VTX_WORD1__SMA_bit = 1 << 31,
|
||||
|
||||
EG_VTX_WORD2__OFFSET_shift = 0, //16 bits
|
||||
EG_VTX_WORD2__OFFSET_mask = 0xFFFF,
|
||||
EG_VTX_WORD2__ENDIAN_SWAP_shift = 16,//2 bits
|
||||
EG_VTX_WORD2__ENDIAN_SWAP_mask = 0x3 << 16,
|
||||
EG_VTX_WORD2__CBNS_shift = 18,//1 bit
|
||||
EG_VTX_WORD2__CBNS_bit = 1 << 18,
|
||||
EG_VTX_WORD2__MEGA_FETCH_shift = 19,//1 bit
|
||||
EG_VTX_WORD2__MEGA_FETCH_mask = 1 << 19,
|
||||
EG_VTX_WORD2__ALT_CONST_shift = 20,//1 bit
|
||||
EG_VTX_WORD2__ALT_CONST_mask = 1 << 20,
|
||||
EG_VTX_WORD2__BIM_shift = 21,//2 bits
|
||||
EG_VTX_WORD2__BIM_mask = 0x3 << 21,
|
||||
EG_VTX_WORD2__Reserved_shift = 23,//9 bits
|
||||
EG_VTX_WORD2__Reserved_mask = 0x1FF << 23,
|
||||
|
||||
//CF_ALU
|
||||
EG_CF_ALU_WORD0__ADDR_shift = 0, //22 bits
|
||||
EG_CF_ALU_WORD0__ADDR_mask = 0x3FFFFF,
|
||||
EG_CF_ALU_WORD0__KCACHE_BANK0_shift = 22,//4 bits
|
||||
EG_CF_ALU_WORD0__KCACHE_BANK0_mask = 0xF << 22,
|
||||
EG_CF_ALU_WORD0__KCACHE_BANK1_shift = 26,//4 bits
|
||||
EG_CF_ALU_WORD0__KCACHE_BANK1_mask = 0xF << 26,
|
||||
EG_CF_ALU_WORD0__KCACHE_MODE0_shift = 30,//2 bits
|
||||
EG_CF_ALU_WORD0__KCACHE_MODE0_mask = 0x3 << 30,
|
||||
|
||||
EG_CF_ALU_WORD1__KCACHE_MODE1_shift = 0, //2 bits
|
||||
EG_CF_ALU_WORD1__KCACHE_MODE1_mask = 0x3,
|
||||
EG_CF_ALU_WORD1__KCACHE_ADDR0_shift = 2, //8 bits
|
||||
EG_CF_ALU_WORD1__KCACHE_ADDR0_mask = 0xFF << 2,
|
||||
EG_CF_ALU_WORD1__KCACHE_ADDR1_shift = 10, //8 bits
|
||||
EG_CF_ALU_WORD1__KCACHE_ADDR1_mask = 0xFF << 10,
|
||||
EG_CF_ALU_WORD1__COUNT_shift = 18, //7 bits
|
||||
EG_CF_ALU_WORD1__COUNT_mask = 0x7F << 18,
|
||||
EG_CF_ALU_WORD1__ALT_CONST_shift = 25, //1 bit
|
||||
EG_CF_ALU_WORD1__ALT_CONST_bit = 1 << 25,
|
||||
EG_CF_ALU_WORD1__CF_INST_shift = 26, //4 bits
|
||||
EG_CF_ALU_WORD1__CF_INST_mask = 0xF << 26,
|
||||
EG_CF_ALU_WORD1__WQM_shift = 30, //1 bit
|
||||
EG_CF_ALU_WORD1__WQM_bit = 1 << 30,
|
||||
EG_CF_ALU_WORD1__BARRIER_shift = 31, //1 bit
|
||||
EG_CF_ALU_WORD1__BARRIER_bit = 1 << 31,
|
||||
|
||||
EG_CF_INST_ALU = 8,
|
||||
EG_CF_INST_ALU_PUSH_BEFORE = 9,
|
||||
EG_CF_INST_ALU_POP_AFTER = 10,
|
||||
EG_CF_INST_ALU_POP2_AFTER = 11,
|
||||
EG_CF_INST_ALU_EXTENDED = 12,
|
||||
EG_CF_INST_ALU_CONTINUE = 13,
|
||||
EG_CF_INST_ALU_BREAK = 14,
|
||||
EG_CF_INST_ALU_ELSE_AFTER = 15,
|
||||
|
||||
EG_CF_ALU_WORD0_EXT__Reserved0_shift = 0, //4 bits
|
||||
EG_CF_ALU_WORD0_EXT__Reserved0_mask = 0xF,
|
||||
EG_CF_ALU_WORD0_EXT__KBIM0_shift = 4, //2 bits
|
||||
EG_CF_ALU_WORD0_EXT__KBIM0_mask = 0x3 << 4,
|
||||
EG_CF_ALU_WORD0_EXT__KBIM1_shift = 6, //2 bits
|
||||
EG_CF_ALU_WORD0_EXT__KBIM1_mask = 0x3 << 6,
|
||||
EG_CF_ALU_WORD0_EXT__KBIM2_shift = 8, //2 bits
|
||||
EG_CF_ALU_WORD0_EXT__KBIM2_mask = 0x3 << 8,
|
||||
EG_CF_ALU_WORD0_EXT__KBIM3_shift = 10,//2 bits
|
||||
EG_CF_ALU_WORD0_EXT__KBIM3_mask = 0x3 << 10,
|
||||
EG_CF_ALU_WORD0_EXT__Reserved12_shift = 12,//10 bits
|
||||
EG_CF_ALU_WORD0_EXT__Reserved12_mask = 0x3FF << 12,
|
||||
EG_CF_ALU_WORD0_EXT__KCACHE_BANK2_shift = 22,//4 bits
|
||||
EG_CF_ALU_WORD0_EXT__KCACHE_BANK2_mask = 0xF << 22,
|
||||
EG_CF_ALU_WORD0_EXT__KCACHE_BANK3_shift = 26,//4 bits
|
||||
EG_CF_ALU_WORD0_EXT__KCACHE_BANK3_mask = 0xF << 26,
|
||||
EG_CF_ALU_WORD0_EXT__KCACHE_MODE2_shift = 30,//2 btis
|
||||
EG_CF_ALU_WORD0_EXT__KCACHE_MODE2_mask = 0x3 << 30,
|
||||
|
||||
EG_CF_ALU_WORD1_EXT__KCACHE_MODE3_shift = 0, //2 bits
|
||||
EG_CF_ALU_WORD1_EXT__KCACHE_MODE3_mask = 0x3,
|
||||
EG_CF_ALU_WORD1_EXT__KCACHE_ADDR2_shift = 2, //8 bits
|
||||
EG_CF_ALU_WORD1_EXT__KCACHE_ADDR2_mask = 0xFF << 2,
|
||||
EG_CF_ALU_WORD1_EXT__KCACHE_ADDR3_shift = 10, //8 bits
|
||||
EG_CF_ALU_WORD1_EXT__KCACHE_ADDR3_mask = 0xFF << 10,
|
||||
EG_CF_ALU_WORD1_EXT__Reserved18_shift = 18, //8 bits
|
||||
EG_CF_ALU_WORD1_EXT__Reserved18_mask = 0xFF << 18,
|
||||
EG_CF_ALU_WORD1_EXT__CF_INST_shift = 26, //4 bits
|
||||
EG_CF_ALU_WORD1_EXT__CF_INST_mask = 0xF << 26,
|
||||
EG_CF_ALU_WORD1_EXT__Reserved30_shift = 30, //1 bit
|
||||
EG_CF_ALU_WORD1_EXT__Reserved30_bit = 1 << 30,
|
||||
EG_CF_ALU_WORD1_EXT__BARRIER_shift = 31, //1 bit
|
||||
EG_CF_ALU_WORD1_EXT__BARRIER_bit = 1 << 31,
|
||||
|
||||
//ALU
|
||||
EG_ALU_WORD0__SRC0_SEL_shift = 0, //9 bits
|
||||
EG_ALU_WORD0__SRC0_SEL_mask = 0x1FF,
|
||||
EG_ALU_WORD0__SRC1_SEL_shift = 13,//9 bits
|
||||
EG_ALU_WORD0__SRC1_SEL_mask = 0x1FF << 13,
|
||||
EG_ALU_WORD0__SRC0_REL_shift = 9, //1 bit
|
||||
EG_ALU_WORD0__SRC0_REL_bit = 1 << 9,
|
||||
EG_ALU_WORD0__SRC1_REL_shift = 22,//1 bit
|
||||
EG_ALU_WORD0__SRC1_REL_bit = 1 << 22,
|
||||
EG_ALU_WORD0__SRC0_CHAN_shift = 10,//2 bits
|
||||
EG_ALU_WORD0__SRC0_CHAN_mask = 0x3 << 10,
|
||||
EG_ALU_WORD0__SRC1_CHAN_shift = 23,//2 bits
|
||||
EG_ALU_WORD0__SRC1_CHAN_mask = 0x3 << 23,
|
||||
EG_ALU_WORD0__SRC0_NEG_shift = 12,//1 bit
|
||||
EG_ALU_WORD0__SRC0_NEG_bit = 1 << 12,
|
||||
EG_ALU_WORD0__SRC1_NEG_shift = 25,//1 bit
|
||||
EG_ALU_WORD0__SRC1_NEG_bit = 1 << 25,
|
||||
EG_ALU_WORD0__INDEX_MODE_shift = 26,//3 bits
|
||||
EG_ALU_WORD0__INDEX_MODE_mask = 0x7 << 26,
|
||||
EG_ALU_WORD0__PRED_SEL_shift = 29,//2 bits
|
||||
EG_ALU_WORD0__PRED_SEL_mask = 0x3 << 29,
|
||||
EG_ALU_WORD0__LAST_shift = 31,//1 bit
|
||||
EG_ALU_WORD0__LAST_bit = 1 << 31,
|
||||
|
||||
EG_ALU_WORD1_OP2__SRC0_ABS_shift = 0, //1 bit
|
||||
EG_ALU_WORD1_OP2__SRC0_ABS_bit = 1,
|
||||
EG_ALU_WORD1_OP2__SRC1_ABS_shift = 1, //1 bit
|
||||
EG_ALU_WORD1_OP2__SRC1_ABS_bit = 1 << 1,
|
||||
EG_ALU_WORD1_OP2__UEM_shift = 2, //1 bit
|
||||
EG_ALU_WORD1_OP2__UEM_bit = 1 << 2,
|
||||
EG_ALU_WORD1_OP2__UPDATE_PRED_shift = 3, //1 bit
|
||||
EG_ALU_WORD1_OP2__UPDATE_PRED_bit = 1 << 3,
|
||||
EG_ALU_WORD1_OP2__WRITE_MASK_shift = 4, //1 bit
|
||||
EG_ALU_WORD1_OP2__WRITE_MASK_bit = 1 << 4,
|
||||
EG_ALU_WORD1_OP2__OMOD_shift = 5, //2 bits
|
||||
EG_ALU_WORD1_OP2__OMOD_mask = 0x3 << 5,
|
||||
EG_ALU_WORD1_OP2__ALU_INST_shift = 7, //11 bits
|
||||
EG_ALU_WORD1_OP2__ALU_INST_mask = 0x7FF << 7,
|
||||
|
||||
EG_ALU_WORD1__BANK_SWIZZLE_shift = 18,//3 bits
|
||||
EG_ALU_WORD1__BANK_SWIZZLE_mask = 0x7 << 18,
|
||||
EG_ALU_WORD1__DST_GPR_shift = 21,//7 bits
|
||||
EG_ALU_WORD1__DST_GPR_mask = 0x7F << 21,
|
||||
EG_ALU_WORD1__DST_REL_shift = 28,//1 bit
|
||||
EG_ALU_WORD1__DST_REL_mask = 1 << 28,
|
||||
EG_ALU_WORD1__DST_CHAN_shift = 29,//2 bits
|
||||
EG_ALU_WORD1__DST_CHAN_mask = 0x3 << 29,
|
||||
EG_ALU_WORD1__CLAMP_shift = 31,//1 bits
|
||||
EG_ALU_WORD1__CLAMP_mask = 1 << 31,
|
||||
|
||||
EG_ALU_WORD1_OP3__SRC2_SEL_shift = 0, //9 bits
|
||||
EG_ALU_WORD1_OP3__SRC2_SEL_mask = 0x1FF,
|
||||
EG_ALU_WORD1_OP3__SRC2_REL_shift = 9, //1 bit
|
||||
EG_ALU_WORD1_OP3__SRC2_REL_bit = 1 << 9,
|
||||
EG_ALU_WORD1_OP3__SRC2_CHAN_shift = 10,//2 bits
|
||||
EG_ALU_WORD1_OP3__SRC2_CHAN_mask = 0x3 << 10,
|
||||
EG_ALU_WORD1_OP3__SRC2_NEG_shift = 12,//1 bit
|
||||
EG_ALU_WORD1_OP3__SRC2_NEG_bit = 1 << 12,
|
||||
EG_ALU_WORD1_OP3__ALU_INST_shift = 13,//5 bits
|
||||
EG_ALU_WORD1_OP3__ALU_INST_mask = 0x1F << 13,
|
||||
|
||||
EG_OP3_INST_BFE_UINT = 4,
|
||||
EG_OP3_INST_BFE_INT = 5,
|
||||
EG_OP3_INST_BFI_INT = 6,
|
||||
EG_OP3_INST_FMA = 7,
|
||||
EG_OP3_INST_CNDNE_64 = 9,
|
||||
EG_OP3_INST_FMA_64 = 10,
|
||||
EG_OP3_INST_LERP_UINT = 11,
|
||||
EG_OP3_INST_BIT_ALIGN_INT = 12,
|
||||
EG_OP3_INST_BYTE_ALIGN_INT = 13,
|
||||
EG_OP3_INST_SAD_ACCUM_UINT = 14,
|
||||
EG_OP3_INST_SAD_ACCUM_HI_UINT = 15,
|
||||
EG_OP3_INST_MULADD_UINT24 = 16,
|
||||
EG_OP3_INST_LDS_IDX_OP = 17,
|
||||
EG_OP3_INST_MULADD = 20,
|
||||
EG_OP3_INST_MULADD_M2 = 21,
|
||||
EG_OP3_INST_MULADD_M4 = 22,
|
||||
EG_OP3_INST_MULADD_D2 = 23,
|
||||
EG_OP3_INST_MULADD_IEEE = 24,
|
||||
EG_OP3_INST_CNDE = 25,
|
||||
EG_OP3_INST_CNDGT = 26,
|
||||
EG_OP3_INST_CNDGE = 27,
|
||||
EG_OP3_INST_CNDE_INT = 28,
|
||||
EG_OP3_INST_CMNDGT_INT = 29,
|
||||
EG_OP3_INST_CMNDGE_INT = 30,
|
||||
EG_OP3_INST_MUL_LIT = 31,
|
||||
|
||||
EG_OP2_INST_ADD = 0,
|
||||
EG_OP2_INST_MUL = 1,
|
||||
EG_OP2_INST_MUL_IEEE = 2,
|
||||
EG_OP2_INST_MAX = 3,
|
||||
EG_OP2_INST_MIN = 4,
|
||||
EG_OP2_INST_MAX_DX10 = 5,
|
||||
EG_OP2_INST_MIN_DX10 = 6,
|
||||
EG_OP2_INST_SETE = 8,
|
||||
EG_OP2_INST_SETGT = 9,
|
||||
EG_OP2_INST_SETGE = 10,
|
||||
EG_OP2_INST_SETNE = 11,
|
||||
EG_OP2_INST_SETE_DX10 = 12,
|
||||
EG_OP2_INST_SETGT_DX10 = 13,
|
||||
EG_OP2_INST_SETGE_DX10 = 14,
|
||||
EG_OP2_INST_SETNE_DX10 = 15,
|
||||
EG_OP2_INST_FRACT = 16,
|
||||
EG_OP2_INST_TRUNC = 17,
|
||||
EG_OP2_INST_CEIL = 18,
|
||||
EG_OP2_INST_RNDNE = 19,
|
||||
EG_OP2_INST_FLOOR = 20,
|
||||
EG_OP2_INST_ASHR_INT = 21,
|
||||
EG_OP2_INST_LSHR_INT = 22,
|
||||
EG_OP2_INST_LSHL_INT = 23,
|
||||
EG_OP2_INST_MOV = 25,
|
||||
EG_OP2_INST_NOP = 26,
|
||||
EG_OP2_INST_MUL_64 = 27,
|
||||
EG_OP2_INST_FLT64_TO_FLT32 = 28,
|
||||
EG_OP2_INST_FLT32_TO_FLT64 = 29,
|
||||
EG_OP2_INST_PRED_SETGT_UINT = 30,
|
||||
EG_OP2_INST_PRED_SETGE_UINT = 31,
|
||||
EG_OP2_INST_PRED_SETE = 32,
|
||||
EG_OP2_INST_PRED_SETGT = 33,
|
||||
EG_OP2_INST_PRED_SETGE = 34,
|
||||
EG_OP2_INST_PRED_SETNE = 35,
|
||||
EG_OP2_INST_PRED_SET_INV = 36,
|
||||
EG_OP2_INST_PRED_SET_POP = 37,
|
||||
EG_OP2_INST_PRED_SET_CLR = 38,
|
||||
EG_OP2_INST_PRED_SET_RESTORE = 39,
|
||||
EG_OP2_INST_PRED_SETE_PUSH = 40,
|
||||
EG_OP2_INST_PRED_SETGT_PUSH = 41,
|
||||
EG_OP2_INST_PRED_SETGE_PUSH = 42,
|
||||
EG_OP2_INST_PRED_SETNE_PUSH = 43,
|
||||
EG_OP2_INST_KILLE = 44,
|
||||
EG_OP2_INST_KILLGT = 45,
|
||||
EG_OP2_INST_KILLGE = 46,
|
||||
EG_OP2_INST_KILLNE = 47,
|
||||
EG_OP2_INST_AND_INT = 48,
|
||||
EG_OP2_INST_OR_INT = 49,
|
||||
EG_OP2_INST_XOR_INT = 50,
|
||||
EG_OP2_INST_NOT_INT = 51,
|
||||
EG_OP2_INST_ADD_INT = 52,
|
||||
EG_OP2_INST_SUB_INT = 53,
|
||||
EG_OP2_INST_MAX_INT = 54,
|
||||
EG_OP2_INST_MIN_INT = 55,
|
||||
EG_OP2_INST_MAX_UINT = 56,
|
||||
EG_OP2_INST_MIN_UINT = 57,
|
||||
EG_OP2_INST_SETE_INT = 58,
|
||||
EG_OP2_INST_SETGT_INT = 59,
|
||||
EG_OP2_INST_SETGE_INT = 60,
|
||||
EG_OP2_INST_SETNE_INT = 61,
|
||||
EG_OP2_INST_SETGT_UINT = 62,
|
||||
EG_OP2_INST_SETGE_UINT = 63,
|
||||
EG_OP2_INST_KILLGT_UINT = 64,
|
||||
EG_OP2_INST_KILLGE_UINT = 65,
|
||||
EG_OP2_INST_PREDE_INT = 66,
|
||||
EG_OP2_INST_PRED_SETGT_INT = 67,
|
||||
EG_OP2_INST_PRED_SETGE_INT = 68,
|
||||
EG_OP2_INST_PRED_SETNE_INT = 69,
|
||||
EG_OP2_INST_KILLE_INT = 70,
|
||||
EG_OP2_INST_KILLGT_INT = 71,
|
||||
EG_OP2_INST_KILLGE_INT = 72,
|
||||
EG_OP2_INST_KILLNE_INT = 73,
|
||||
EG_OP2_INST_PRED_SETE_PUSH_INT = 74,
|
||||
EG_OP2_INST_PRED_SETGT_PUSH_INT = 75,
|
||||
EG_OP2_INST_PRED_SETGE_PUSH_INT = 76,
|
||||
EG_OP2_INST_PRED_SETNE_PUSH_INT = 77,
|
||||
EG_OP2_INST_PRED_SETLT_PUSH_INT = 78,
|
||||
EG_OP2_INST_PRED_SETLE_PUSH_INT = 79,
|
||||
EG_OP2_INST_FLT_TO_INT = 80,
|
||||
EG_OP2_INST_BFREV_INT = 81,
|
||||
EG_OP2_INST_ADDC_UINT = 82,
|
||||
EG_OP2_INST_SUBB_UINT = 83,
|
||||
EG_OP2_INST_GROUP_BARRIER = 84,
|
||||
EG_OP2_INST_GROUP_SEQ_BEGIN = 85,
|
||||
EG_OP2_INST_GROUP_SEQ_END = 86,
|
||||
EG_OP2_INST_SET_MODE = 87,
|
||||
EG_OP2_INST_SET_CF_IDX0 = 88,
|
||||
EG_OP2_INST_SET_CF_IDX1 = 89,
|
||||
EG_OP2_INST_SET_LDS_SIZE = 90,
|
||||
EG_OP2_INST_EXP_IEEE = 129,
|
||||
EG_OP2_INST_LOG_CLAMPED = 130,
|
||||
EG_OP2_INST_LOG_IEEE = 131,
|
||||
EG_OP2_INST_RECIP_CLAMPED = 132,
|
||||
EG_OP2_INST_RECIP_FF = 133,
|
||||
EG_OP2_INST_RECIP_IEEE = 134,
|
||||
EG_OP2_INST_RECIPSQRT_CLAMPED = 135,
|
||||
EG_OP2_INST_RECIPSQRT_FF = 136,
|
||||
EG_OP2_INST_RECIPSQRT_IEEE = 137,
|
||||
EG_OP2_INST_SQRT_IEEE = 138,
|
||||
EG_OP2_INST_SIN = 141,
|
||||
EG_OP2_INST_COS = 142,
|
||||
EG_OP2_INST_MULLO_INT = 143,
|
||||
EG_OP2_INST_MULHI_INT = 144,
|
||||
EG_OP2_INST_MULLO_UINT = 145,
|
||||
EG_OP2_INST_MULHI_UINT = 146,
|
||||
EG_OP2_INST_RECIP_INT = 147,
|
||||
EG_OP2_INST_RECIP_UINT = 148,
|
||||
EG_OP2_INST_RECIP_64 = 149,
|
||||
EG_OP2_INST_RECIP_CLAMPED_64 = 150,
|
||||
EG_OP2_INST_RECIPSQRT_64 = 151,
|
||||
EG_OP2_INST_RECIPSQRT_CLAMPED_64 = 152,
|
||||
EG_OP2_INST_SQRT_64 = 153,
|
||||
EG_OP2_INST_FLT_TO_UINT = 154,
|
||||
EG_OP2_INST_INT_TO_FLT = 155,
|
||||
EG_OP2_INST_UINT_TO_FLT = 156,
|
||||
EG_OP2_INST_BFM_INT = 160,
|
||||
EG_OP2_INST_FLT32_TO_FLT16 = 162,
|
||||
EG_OP2_INST_FLT16_TO_FLT32 = 163,
|
||||
EG_OP2_INST_UBYTE0_FLT = 164,
|
||||
EG_OP2_INST_UBYTE1_FLT = 165,
|
||||
EG_OP2_INST_UBYTE2_FLT = 166,
|
||||
EG_OP2_INST_UBYTE3_FLT = 167,
|
||||
EG_OP2_INST_BCNT_INT = 170,
|
||||
EG_OP2_INST_FFBH_UINT = 171,
|
||||
EG_OP2_INST_FFBL_INT = 172,
|
||||
EG_OP2_INST_FFBH_INT = 173,
|
||||
EG_OP2_INST_FLT_TO_UINT4 = 174,
|
||||
EG_OP2_INST_DOT_IEEE = 175,
|
||||
EG_OP2_INST_FLT_TO_INT_RPI = 176,
|
||||
EG_OP2_INST_FLT_TO_INT_FLOOR = 177,
|
||||
EG_OP2_INST_MULHI_UINT24 = 178,
|
||||
EG_OP2_INST_MBCNT_32HI_INT = 179,
|
||||
EG_OP2_INST_OFFSET_TO_FLT = 180,
|
||||
EG_OP2_INST_MUL_UINT24 = 181,
|
||||
EG_OP2_INST_BCNT_ACCUM_PREV_INT = 182,
|
||||
EG_OP2_INST_MBCNT_32LO_ACCUM_PREV_INT = 183,
|
||||
EG_OP2_INST_SETE_64 = 184,
|
||||
EG_OP2_INST_SETNE_64 = 185,
|
||||
EG_OP2_INST_SETGT_64 = 186,
|
||||
EG_OP2_INST_SETGE_64 = 187,
|
||||
EG_OP2_INST_MIN_64 = 188,
|
||||
EG_OP2_INST_MAX_64 = 189,
|
||||
EG_OP2_INST_DOT4 = 190,
|
||||
EG_OP2_INST_DOT4_IEEE = 191,
|
||||
EG_OP2_INST_CUBE = 192,
|
||||
EG_OP2_INST_MAX4 = 193,
|
||||
EG_OP2_INST_FREXP_64 = 196,
|
||||
EG_OP2_INST_LDEXP_64 = 197,
|
||||
EG_OP2_INST_FRACT_64 = 198,
|
||||
EG_OP2_INST_PRED_SETGT_64 = 199,
|
||||
EG_OP2_INST_PRED_SETE_64 = 200,
|
||||
EG_OP2_INST_PRED_SETGE_64 = 201,
|
||||
EG_OP2_INST_MUL_64_2 = 202, //same as prev?
|
||||
EG_OP2_INST_ADD_64 = 203,
|
||||
EG_OP2_INST_MOVA_INT = 204,
|
||||
EG_OP2_INST_FLT64_TO_FLT32_2 = 205, //same as prev?
|
||||
EG_OP2_INST_FLT32_TO_FLT64_2 = 206, //same as prev?
|
||||
EG_OP2_INST_SAD_ACCUM_PREV_UINT = 207,
|
||||
EG_OP2_INST_DOT = 208,
|
||||
EG_OP2_INST_MUL_PREV = 209,
|
||||
EG_OP2_INST_MUL_IEEE_PREV = 210,
|
||||
EG_OP2_INST_ADD_PREV = 211,
|
||||
EG_OP2_INST_MULADD_PREV = 212,
|
||||
EG_OP2_INST_MULADD_IEEE_PREV = 213,
|
||||
EG_OP2_INST_INTERP_XY = 214,
|
||||
EG_OP2_INST_INTERP_ZW = 215,
|
||||
EG_OP2_INST_INTERP_X = 216,
|
||||
EG_OP2_INST_INTERP_Z = 217,
|
||||
EG_OP2_INST_STORE_FLAGS = 218,
|
||||
EG_OP2_INST_LOAD_STORE_FLAGS = 219,
|
||||
EG_OP2_INST_LDS_1A = 220,
|
||||
EG_OP2_INST_LDS_1A1D = 221,
|
||||
EG_OP2_INST_LDS_2A = 223,
|
||||
EG_OP2_INST_INTERP_LOAD_P0 = 224,
|
||||
EG_OP2_INST_INTERP_LOAD_P10 = 225,
|
||||
EG_OP2_INST_INTERP_LOAD_P20 = 226,
|
||||
|
||||
EG_SRC_SEL__GPR_start = 0,
|
||||
EG_SRC_SEL__GPR_end = 127,
|
||||
EG_SRC_SEL__KCONST_BANK0_start = 128,
|
||||
EG_SRC_SEL__KCONST_BANK0_end = 159,
|
||||
EG_SRC_SEL__KCONST_BANK1_start = 160,
|
||||
EG_SRC_SEL__KCONST_BANK1_end = 191,
|
||||
EG_SRC_SEL__INLINE_satrt = 192,
|
||||
EG_SRC_SEL__INLINE_end = 255,
|
||||
EG_SRC_SEL__KCONST_BANK2_start = 256,
|
||||
EG_SRC_SEL__KCONST_BANK2_end = 287,
|
||||
EG_SRC_SEL__KCONST_BANK3_start = 288,
|
||||
EG_SRC_SEL__KCONST_BANK3_end = 319,
|
||||
EG_SRC_SEL__ALU_SRC_LDS_OQ_A = 219,
|
||||
EG_SRC_SEL__ALU_SRC_LDS_OQ_B = 220,
|
||||
EG_SRC_SEL__ALU_SRC_LDS_OQ_A_POP = 221,
|
||||
EG_SRC_SEL__ALU_SRC_LDS_OQ_B_POP = 222,
|
||||
EG_SRC_SEL__ALU_SRC_LDS_DIRECT_A = 223,
|
||||
EG_SRC_SEL__ALU_SRC_LDS_DIRECT_B = 224,
|
||||
EG_SRC_SEL__ALU_SRC_TIME_HI = 227,
|
||||
EG_SRC_SEL__ALU_SRC_TIME_LO = 228,
|
||||
EG_SRC_SEL__ALU_SRC_MASK_HI = 229,
|
||||
EG_SRC_SEL__ALU_SRC_MASK_LO = 230,
|
||||
EG_SRC_SEL__ALU_SRC_HW_WAVE_ID = 231,
|
||||
EG_SRC_SEL__ALU_SRC_SIMD_ID = 232,
|
||||
EG_SRC_SEL__ALU_SRC_SE_ID = 233,
|
||||
EG_SRC_SEL__ALU_SRC_HW_THREADGRP_ID = 234,
|
||||
EG_SRC_SEL__ALU_SRC_WAVE_ID_IN_GRP = 235,
|
||||
EG_SRC_SEL__ALU_SRC_NUM_THREADGRP_WAVES = 236,
|
||||
EG_SRC_SEL__ALU_SRC_HW_ALU_ODD = 237,
|
||||
EG_SRC_SEL__ALU_SRC_LOOP_IDX = 238,
|
||||
EG_SRC_SEL__ALU_SRC_PARAM_BASE_ADDR = 240,
|
||||
EG_SRC_SEL__ALU_SRC_NEW_PRIM_MASK = 241,
|
||||
EG_SRC_SEL__ALU_SRC_PRIM_MASK_HI = 242,
|
||||
EG_SRC_SEL__ALU_SRC_PRIM_MASK_LO = 243,
|
||||
EG_SRC_SEL__ALU_SRC_1_DBL_L = 244,
|
||||
EG_SRC_SEL__ALU_SRC_1_DBL_M = 245,
|
||||
EG_SRC_SEL__ALU_SRC_0_5_DBL_L = 246,
|
||||
EG_SRC_SEL__ALU_SRC_0_5_DBL_M = 247,
|
||||
EG_SRC_SEL__ALU_SRC_0 = 248,
|
||||
EG_SRC_SEL__ALU_SRC_1 = 249,
|
||||
EG_SRC_SEL__ALU_SRC_1_INT = 250,
|
||||
EG_SRC_SEL__ALU_SRC_M_1_INT = 251,
|
||||
EG_SRC_SEL__ALU_SRC_0_5 = 252,
|
||||
EG_SRC_SEL__ALU_SRC_LITERAL = 253,
|
||||
EG_SRC_SEL__ALU_SRC_PV = 254,
|
||||
EG_SRC_SEL__ALU_SRC_PS = 255,
|
||||
|
||||
//ALLOC_EXPORT
|
||||
EG_CF_ALLOC_EXPORT_WORD0__ARRAY_BASE_shift = 0, //13 bits
|
||||
EG_CF_ALLOC_EXPORT_WORD0__ARRAY_BASE_mask = 0x1FFF,
|
||||
EG_CF_ALLOC_EXPORT_WORD0__TYPE_shift = 13,//2 bits
|
||||
EG_CF_ALLOC_EXPORT_WORD0__TYPE_mask = 0x3 << 13,
|
||||
EG_CF_ALLOC_EXPORT_WORD0__RW_GPR_shift = 15,//7 bits
|
||||
EG_CF_ALLOC_EXPORT_WORD0__RW_GPR_mask = 0x7F << 15,
|
||||
EG_CF_ALLOC_EXPORT_WORD0__RW_REL_shift = 22,//1 bit
|
||||
EG_CF_ALLOC_EXPORT_WORD0__RW_REL_bit = 1 << 22,
|
||||
EG_CF_ALLOC_EXPORT_WORD0__INDEX_GPR_shift = 23,//7 bits
|
||||
EG_CF_ALLOC_EXPORT_WORD0__INDEX_GPR_mask = 0x7F << 23,
|
||||
EG_CF_ALLOC_EXPORT_WORD0__ELEM_SIZE_shift = 30,//2 bits
|
||||
EG_CF_ALLOC_EXPORT_WORD0__ELEM_SIZE_mask = 0x3 << 30,
|
||||
|
||||
EG_CF_ALLOC_EXPORT_WORD1_BUF__ARRAY_SIZE_shift = 0, //12 bits
|
||||
EG_CF_ALLOC_EXPORT_WORD1_BUF__ARRAY_SIZE_mask = 0xFFF,
|
||||
EG_CF_ALLOC_EXPORT_WORD1_BUF__COMP_MASK_shift = 12, //4 bits
|
||||
EG_CF_ALLOC_EXPORT_WORD1_BUF__COMP_MASK_mask = 0xF << 12,
|
||||
|
||||
EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_X_shift = 0, //3 bits
|
||||
EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_X_mask = 0x7,
|
||||
EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Y_shift = 3, //3 bits
|
||||
EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Y_mask = 0x7 << 3,
|
||||
EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Z_shift = 6, //3 bits
|
||||
EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Z_mask = 0x7 << 6,
|
||||
EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_W_shift = 9, //3 bits
|
||||
EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_W_mask = 0x7 << 9,
|
||||
EG_CF_ALLOC_EXPORT_WORD1_SWIZ__Resreve_shift = 12,//4 bits
|
||||
EG_CF_ALLOC_EXPORT_WORD1_SWIZ__Resreve_mask = 0xF << 12,
|
||||
|
||||
EG_CF_ALLOC_EXPORT_WORD1__BURST_COUNT_shift = 16, //4 bits
|
||||
EG_CF_ALLOC_EXPORT_WORD1__BURST_COUNT_mask = 0xF << 16,
|
||||
EG_CF_ALLOC_EXPORT_WORD1__VPM_shift = 20, //1 bit
|
||||
EG_CF_ALLOC_EXPORT_WORD1__VPM_bit = 1 << 20,
|
||||
EG_CF_ALLOC_EXPORT_WORD1__EOP_shift = 21, //1 bit
|
||||
EG_CF_ALLOC_EXPORT_WORD1__EOP_bit = 1 << 21,
|
||||
EG_CF_ALLOC_EXPORT_WORD1__CF_INST_shift = 22, //8 bits
|
||||
EG_CF_ALLOC_EXPORT_WORD1__CF_INST_mask = 0xFF << 22,
|
||||
EG_CF_ALLOC_EXPORT_WORD1__MARK_shift = 30, //1 bit
|
||||
EG_CF_ALLOC_EXPORT_WORD1__MARK_bit = 1 << 30,
|
||||
EG_CF_ALLOC_EXPORT_WORD1__BARRIER_shift = 31, //1 bit
|
||||
EG_CF_ALLOC_EXPORT_WORD1__BARRIER_bit = 1 << 31,
|
||||
|
||||
EG_CF_INST_MEM_STREAM0_BUF0 = 64 ,
|
||||
EG_CF_INST_MEM_STREAM0_BUF1 = 65,
|
||||
EG_CF_INST_MEM_STREAM0_BUF2 = 66,
|
||||
EG_CF_INST_MEM_STREAM0_BUF3 = 67,
|
||||
EG_CF_INST_MEM_STREAM1_BUF0 = 68,
|
||||
EG_CF_INST_MEM_STREAM1_BUF1 = 69,
|
||||
EG_CF_INST_MEM_STREAM1_BUF2 = 70,
|
||||
EG_CF_INST_MEM_STREAM1_BUF3 = 71,
|
||||
EG_CF_INST_MEM_STREAM2_BUF0 = 72,
|
||||
EG_CF_INST_MEM_STREAM2_BUF1 = 73,
|
||||
EG_CF_INST_MEM_STREAM2_BUF2 = 74,
|
||||
EG_CF_INST_MEM_STREAM2_BUF3 = 75,
|
||||
EG_CF_INST_MEM_STREAM3_BUF0 = 76,
|
||||
EG_CF_INST_MEM_STREAM3_BUF1 = 77,
|
||||
EG_CF_INST_MEM_STREAM3_BUF2 = 78,
|
||||
EG_CF_INST_MEM_STREAM3_BUF3 = 79,
|
||||
EG_CF_INST_MEM_WR_SCRATCH = 80,
|
||||
EG_CF_INST_MEM_RING = 82,
|
||||
EG_CF_INST_EXPORT = 83,
|
||||
EG_CF_INST_EXPORT_DONE = 84,
|
||||
EG_CF_INST_MEM_EXPORT = 85,
|
||||
EG_CF_INST_MEM_RAT = 86,
|
||||
EG_CF_INST_MEM_RAT_CACHELESS = 87,
|
||||
EG_CF_INST_MEM_RING1 = 88,
|
||||
EG_CF_INST_MEM_RING2 = 89,
|
||||
EG_CF_INST_MEM_RING3 = 90,
|
||||
EG_CF_INST_MEM_EXPORT_COMBINED = 91,
|
||||
EG_CF_INST_MEM_RAT_COMBINED_CACHELESS = 92,
|
||||
|
||||
EG_EXPORT_PIXEL = 0,
|
||||
EG_EXPORT_WRITE = 0,
|
||||
EG_EXPORT_POS = 1,
|
||||
EG_EXPORT_WRITE_IND = 1,
|
||||
EG_EXPORT_PARAM = 2,
|
||||
EG_EXPORT_WRITE_ACK = 2,
|
||||
EG_EXPORT_WRITE_IND_ACK = 3,
|
||||
|
||||
/* PS interp param source */
|
||||
EG_ALU_SRC_PARAM_BASE = 0x000001c0,
|
||||
EG_ALU_SRC_PARAM_SIZE = 0x00000021,
|
||||
};
|
||||
|
||||
#endif //_EVERGREEN_SQ_H_
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,47 @@
|
|||
/*
|
||||
* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Authors:
|
||||
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef _EVERGREEN_STATE_H_
|
||||
#define _EVERGREEN_STATE_H_
|
||||
|
||||
#include "main/mtypes.h"
|
||||
|
||||
#include "r600_context.h"
|
||||
|
||||
extern void evergreenUpdateStateParameters(GLcontext * ctx, GLuint new_state);
|
||||
extern void evergreenUpdateShaders(GLcontext * ctx);
|
||||
extern void evergreenUpdateShaderStates(GLcontext * ctx);
|
||||
|
||||
extern void evergreeUpdateShaders(GLcontext * ctx);
|
||||
|
||||
extern void evergreenUpdateViewportOffset(GLcontext * ctx);
|
||||
|
||||
extern void evergreenInitState(GLcontext * ctx);
|
||||
extern void evergreenInitStateFuncs (radeonContextPtr radeon, struct dd_function_table *functions);
|
||||
|
||||
extern void evergreenSetScissor(context_t *context);
|
||||
|
||||
#endif /* _EVERGREEN_STATE_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Authors:
|
||||
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef _EVERGREEN_TEX_H_
|
||||
#define _EVERGREEN_TEX_H_
|
||||
|
||||
extern GLboolean evergreenValidateBuffers(GLcontext * ctx);
|
||||
|
||||
extern void evergreenUpdateTextureState(GLcontext * ctx);
|
||||
extern void evergreenInitTextureFuncs(radeonContextPtr radeon, struct dd_function_table *functions);
|
||||
extern void evergreenSetTexOffset(__DRIcontext * pDRICtx, GLint texname,
|
||||
unsigned long long offset, GLint depth, GLuint pitch);
|
||||
extern void evergreenSetTexBuffer(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_format, __DRIdrawable *dPriv);
|
||||
|
||||
#endif /* _EVERGREEN_TEX_H_ */
|
||||
|
|
@ -0,0 +1,729 @@
|
|||
/*
|
||||
* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Authors:
|
||||
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
|
||||
*/
|
||||
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdarg.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
|
||||
#include "main/imports.h"
|
||||
#include "main/mtypes.h"
|
||||
|
||||
#include "tnl/t_context.h"
|
||||
#include "program/program.h"
|
||||
#include "program/prog_parameter.h"
|
||||
#include "program/prog_statevars.h"
|
||||
|
||||
#include "radeon_debug.h"
|
||||
#include "r600_context.h"
|
||||
#include "r600_cmdbuf.h"
|
||||
#include "program/programopt.h"
|
||||
|
||||
#include "r700_debug.h"
|
||||
#include "evergreen_vertprog.h"
|
||||
|
||||
unsigned int evergreen_Map_Vertex_Output(r700_AssemblerBase *pAsm,
|
||||
struct gl_vertex_program *mesa_vp,
|
||||
unsigned int unStart)
|
||||
{
|
||||
unsigned int i;
|
||||
unsigned int unBit;
|
||||
unsigned int unTotal = unStart;
|
||||
|
||||
//!!!!!!! THE ORDER MATCH FS INPUT
|
||||
|
||||
unBit = 1 << VERT_RESULT_HPOS;
|
||||
if(mesa_vp->Base.OutputsWritten & unBit)
|
||||
{
|
||||
pAsm->ucVP_OutputMap[VERT_RESULT_HPOS] = unTotal++;
|
||||
}
|
||||
|
||||
unBit = 1 << VERT_RESULT_COL0;
|
||||
if(mesa_vp->Base.OutputsWritten & unBit)
|
||||
{
|
||||
pAsm->ucVP_OutputMap[VERT_RESULT_COL0] = unTotal++;
|
||||
}
|
||||
|
||||
unBit = 1 << VERT_RESULT_COL1;
|
||||
if(mesa_vp->Base.OutputsWritten & unBit)
|
||||
{
|
||||
pAsm->ucVP_OutputMap[VERT_RESULT_COL1] = unTotal++;
|
||||
}
|
||||
|
||||
//TODO : dealing back face.
|
||||
unBit = 1 << VERT_RESULT_BFC0;
|
||||
if(mesa_vp->Base.OutputsWritten & unBit)
|
||||
{
|
||||
pAsm->ucVP_OutputMap[VERT_RESULT_BFC0] = unTotal++;
|
||||
}
|
||||
|
||||
unBit = 1 << VERT_RESULT_BFC1;
|
||||
if(mesa_vp->Base.OutputsWritten & unBit)
|
||||
{
|
||||
pAsm->ucVP_OutputMap[VERT_RESULT_BFC1] = unTotal++;
|
||||
}
|
||||
|
||||
//TODO : dealing fog.
|
||||
unBit = 1 << VERT_RESULT_FOGC;
|
||||
if(mesa_vp->Base.OutputsWritten & unBit)
|
||||
{
|
||||
pAsm->ucVP_OutputMap[VERT_RESULT_FOGC] = unTotal++;
|
||||
}
|
||||
|
||||
//TODO : dealing point size.
|
||||
unBit = 1 << VERT_RESULT_PSIZ;
|
||||
if(mesa_vp->Base.OutputsWritten & unBit)
|
||||
{
|
||||
pAsm->ucVP_OutputMap[VERT_RESULT_PSIZ] = unTotal++;
|
||||
}
|
||||
|
||||
for(i=0; i<8; i++)
|
||||
{
|
||||
unBit = 1 << (VERT_RESULT_TEX0 + i);
|
||||
if(mesa_vp->Base.OutputsWritten & unBit)
|
||||
{
|
||||
pAsm->ucVP_OutputMap[VERT_RESULT_TEX0 + i] = unTotal++;
|
||||
}
|
||||
}
|
||||
|
||||
for(i=VERT_RESULT_VAR0; i<VERT_RESULT_MAX; i++)
|
||||
{
|
||||
unBit = 1 << i;
|
||||
if(mesa_vp->Base.OutputsWritten & unBit)
|
||||
{
|
||||
pAsm->ucVP_OutputMap[i] = unTotal++;
|
||||
}
|
||||
}
|
||||
|
||||
return (unTotal - unStart);
|
||||
}
|
||||
|
||||
unsigned int evergreen_Map_Vertex_Input(r700_AssemblerBase *pAsm,
|
||||
struct gl_vertex_program *mesa_vp,
|
||||
unsigned int unStart)
|
||||
{
|
||||
int i;
|
||||
unsigned int unBit;
|
||||
unsigned int unTotal = unStart;
|
||||
for(i=0; i<VERT_ATTRIB_MAX; i++)
|
||||
{
|
||||
unBit = 1 << i;
|
||||
if(mesa_vp->Base.InputsRead & unBit)
|
||||
{
|
||||
pAsm->ucVP_AttributeMap[i] = unTotal++;
|
||||
}
|
||||
}
|
||||
return (unTotal - unStart);
|
||||
}
|
||||
|
||||
GLboolean evergreen_Process_Vertex_Program_Vfetch_Instructions(
|
||||
struct evergreen_vertex_program *vp,
|
||||
struct gl_vertex_program *mesa_vp)
|
||||
{
|
||||
int i;
|
||||
unsigned int unBit;
|
||||
VTX_FETCH_METHOD vtxFetchMethod;
|
||||
vtxFetchMethod.bEnableMini = GL_FALSE;
|
||||
vtxFetchMethod.mega_fetch_remainder = 0;
|
||||
|
||||
for(i=0; i<VERT_ATTRIB_MAX; i++)
|
||||
{
|
||||
unBit = 1 << i;
|
||||
if(mesa_vp->Base.InputsRead & unBit)
|
||||
{
|
||||
assemble_vfetch_instruction(&vp->r700AsmCode,
|
||||
i,
|
||||
vp->r700AsmCode.ucVP_AttributeMap[i],
|
||||
vp->aos_desc[i].size,
|
||||
vp->aos_desc[i].type,
|
||||
&vtxFetchMethod);
|
||||
}
|
||||
}
|
||||
|
||||
return GL_TRUE;
|
||||
}
|
||||
|
||||
GLboolean evergreen_Process_Vertex_Program_Vfetch_Instructions2(
|
||||
GLcontext *ctx,
|
||||
struct evergreen_vertex_program *vp,
|
||||
struct gl_vertex_program *mesa_vp)
|
||||
{
|
||||
int i;
|
||||
context_t *context = R700_CONTEXT(ctx);
|
||||
|
||||
VTX_FETCH_METHOD vtxFetchMethod;
|
||||
vtxFetchMethod.bEnableMini = GL_FALSE;
|
||||
vtxFetchMethod.mega_fetch_remainder = 0;
|
||||
|
||||
for(i=0; i<context->nNumActiveAos; i++)
|
||||
{
|
||||
EG_assemble_vfetch_instruction(&vp->r700AsmCode,
|
||||
vp->r700AsmCode.ucVP_AttributeMap[context->stream_desc[i].element],
|
||||
context->stream_desc[i].type,
|
||||
context->stream_desc[i].size,
|
||||
context->stream_desc[i].element,
|
||||
context->stream_desc[i]._signed,
|
||||
context->stream_desc[i].normalize,
|
||||
context->stream_desc[i].format,
|
||||
&vtxFetchMethod);
|
||||
}
|
||||
|
||||
return GL_TRUE;
|
||||
}
|
||||
|
||||
void evergreen_Map_Vertex_Program(GLcontext *ctx,
|
||||
struct evergreen_vertex_program *vp,
|
||||
struct gl_vertex_program *mesa_vp)
|
||||
{
|
||||
GLuint ui;
|
||||
r700_AssemblerBase *pAsm = &(vp->r700AsmCode);
|
||||
unsigned int num_inputs;
|
||||
|
||||
// R0 will always be used for index into vertex buffer
|
||||
pAsm->number_used_registers = 1;
|
||||
pAsm->starting_vfetch_register_number = pAsm->number_used_registers;
|
||||
|
||||
// Map Inputs: Add 1 to mapping since R0 is used for index
|
||||
num_inputs = evergreen_Map_Vertex_Input(pAsm, mesa_vp, pAsm->number_used_registers);
|
||||
pAsm->number_used_registers += num_inputs;
|
||||
|
||||
// Create VFETCH instructions for inputs
|
||||
if (GL_TRUE != evergreen_Process_Vertex_Program_Vfetch_Instructions2(ctx, vp, mesa_vp) )
|
||||
{
|
||||
radeon_error("Calling evergreen_Process_Vertex_Program_Vfetch_Instructions2 return error. \n");
|
||||
return;
|
||||
}
|
||||
|
||||
// Map Outputs
|
||||
pAsm->number_of_exports = evergreen_Map_Vertex_Output(pAsm, mesa_vp, pAsm->number_used_registers);
|
||||
|
||||
pAsm->starting_export_register_number = pAsm->number_used_registers;
|
||||
|
||||
pAsm->number_used_registers += pAsm->number_of_exports;
|
||||
|
||||
pAsm->pucOutMask = (unsigned char*) MALLOC(pAsm->number_of_exports);
|
||||
|
||||
for(ui=0; ui<pAsm->number_of_exports; ui++)
|
||||
{
|
||||
pAsm->pucOutMask[ui] = 0x0;
|
||||
}
|
||||
|
||||
/* Map temporary registers (GPRs) */
|
||||
pAsm->starting_temp_register_number = pAsm->number_used_registers;
|
||||
|
||||
if(mesa_vp->Base.NumNativeTemporaries >= mesa_vp->Base.NumTemporaries)
|
||||
{ /* arb uses NumNativeTemporaries */
|
||||
pAsm->number_used_registers += mesa_vp->Base.NumNativeTemporaries;
|
||||
}
|
||||
else
|
||||
{ /* fix func t_vp uses NumTemporaries */
|
||||
pAsm->number_used_registers += mesa_vp->Base.NumTemporaries;
|
||||
}
|
||||
|
||||
pAsm->flag_reg_index = pAsm->number_used_registers++;
|
||||
|
||||
pAsm->uFirstHelpReg = pAsm->number_used_registers;
|
||||
}
|
||||
|
||||
GLboolean evergreen_Find_Instruction_Dependencies_vp(struct evergreen_vertex_program *vp,
|
||||
struct gl_vertex_program *mesa_vp)
|
||||
{
|
||||
GLuint i, j;
|
||||
GLint * puiTEMPwrites;
|
||||
struct prog_instruction *pILInst;
|
||||
InstDeps *pInstDeps;
|
||||
|
||||
puiTEMPwrites = (GLint*) MALLOC(sizeof(GLuint)*mesa_vp->Base.NumTemporaries);
|
||||
for(i=0; i<mesa_vp->Base.NumTemporaries; i++)
|
||||
{
|
||||
puiTEMPwrites[i] = -1;
|
||||
}
|
||||
|
||||
pInstDeps = (InstDeps*)MALLOC(sizeof(InstDeps)*mesa_vp->Base.NumInstructions);
|
||||
|
||||
for(i=0; i<mesa_vp->Base.NumInstructions; i++)
|
||||
{
|
||||
pInstDeps[i].nDstDep = -1;
|
||||
pILInst = &(mesa_vp->Base.Instructions[i]);
|
||||
|
||||
//Dst
|
||||
if(pILInst->DstReg.File == PROGRAM_TEMPORARY)
|
||||
{
|
||||
//Set lastwrite for the temp
|
||||
puiTEMPwrites[pILInst->DstReg.Index] = i;
|
||||
}
|
||||
|
||||
//Src
|
||||
for(j=0; j<3; j++)
|
||||
{
|
||||
if(pILInst->SrcReg[j].File == PROGRAM_TEMPORARY)
|
||||
{
|
||||
//Set dep.
|
||||
pInstDeps[i].nSrcDeps[j] = puiTEMPwrites[pILInst->SrcReg[j].Index];
|
||||
}
|
||||
else
|
||||
{
|
||||
pInstDeps[i].nSrcDeps[j] = -1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
vp->r700AsmCode.pInstDeps = pInstDeps;
|
||||
|
||||
FREE(puiTEMPwrites);
|
||||
|
||||
return GL_TRUE;
|
||||
}
|
||||
|
||||
struct evergreen_vertex_program* evergreenTranslateVertexShader(GLcontext *ctx,
|
||||
struct gl_vertex_program *mesa_vp)
|
||||
{
|
||||
context_t *context = EVERGREEN_CONTEXT(ctx);
|
||||
|
||||
struct evergreen_vertex_program *vp;
|
||||
unsigned int i;
|
||||
|
||||
vp = calloc(1, sizeof(*vp));
|
||||
vp->mesa_program = _mesa_clone_vertex_program(ctx, mesa_vp);
|
||||
|
||||
vp->constbo0 = NULL;
|
||||
|
||||
if (mesa_vp->IsPositionInvariant)
|
||||
{
|
||||
_mesa_insert_mvp_code(ctx, vp->mesa_program);
|
||||
}
|
||||
|
||||
for(i=0; i<context->nNumActiveAos; i++)
|
||||
{
|
||||
vp->aos_desc[i].size = context->stream_desc[i].size;
|
||||
vp->aos_desc[i].stride = context->stream_desc[i].stride;
|
||||
vp->aos_desc[i].type = context->stream_desc[i].type;
|
||||
vp->aos_desc[i].format = context->stream_desc[i].format;
|
||||
}
|
||||
|
||||
if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
|
||||
{
|
||||
vp->r700AsmCode.bR6xx = 1;
|
||||
}
|
||||
|
||||
//Init_Program
|
||||
Init_r700_AssemblerBase(SPT_VP, &(vp->r700AsmCode), &(vp->r700Shader) );
|
||||
|
||||
vp->r700AsmCode.bUseMemConstant = GL_TRUE;
|
||||
vp->r700AsmCode.unAsic = 8;
|
||||
|
||||
evergreen_Map_Vertex_Program(ctx, vp, vp->mesa_program );
|
||||
|
||||
if(GL_FALSE == evergreen_Find_Instruction_Dependencies_vp(vp, vp->mesa_program))
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
InitShaderProgram(&(vp->r700AsmCode));
|
||||
|
||||
for(i=0; i < MAX_SAMPLERS; i++)
|
||||
{
|
||||
vp->r700AsmCode.SamplerUnits[i] = vp->mesa_program->Base.SamplerUnits[i];
|
||||
}
|
||||
|
||||
vp->r700AsmCode.unCurNumILInsts = vp->mesa_program->Base.NumInstructions;
|
||||
|
||||
if(GL_FALSE == AssembleInstr(0,
|
||||
0,
|
||||
vp->mesa_program->Base.NumInstructions,
|
||||
&(vp->mesa_program->Base.Instructions[0]),
|
||||
&(vp->r700AsmCode)) )
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if(GL_FALSE == Process_Vertex_Exports(&(vp->r700AsmCode), vp->mesa_program->Base.OutputsWritten) )
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if( GL_FALSE == RelocProgram(&(vp->r700AsmCode), &(vp->mesa_program->Base)) )
|
||||
{
|
||||
return GL_FALSE;
|
||||
}
|
||||
|
||||
vp->r700Shader.nRegs = (vp->r700AsmCode.number_used_registers == 0) ? 0
|
||||
: (vp->r700AsmCode.number_used_registers - 1);
|
||||
|
||||
vp->r700Shader.nParamExports = vp->r700AsmCode.number_of_exports;
|
||||
|
||||
vp->translated = GL_TRUE;
|
||||
|
||||
return vp;
|
||||
}
|
||||
|
||||
void evergreenSelectVertexShader(GLcontext *ctx)
|
||||
{
|
||||
context_t *context = EVERGREEN_CONTEXT(ctx);
|
||||
struct evergreen_vertex_program_cont *vpc;
|
||||
struct evergreen_vertex_program *vp;
|
||||
unsigned int i;
|
||||
GLboolean match;
|
||||
GLbitfield InputsRead;
|
||||
|
||||
vpc = (struct evergreen_vertex_program_cont *)ctx->VertexProgram._Current;
|
||||
|
||||
InputsRead = vpc->mesa_program.Base.InputsRead;
|
||||
if (vpc->mesa_program.IsPositionInvariant)
|
||||
{
|
||||
InputsRead |= VERT_BIT_POS;
|
||||
}
|
||||
|
||||
for (vp = vpc->progs; vp; vp = vp->next)
|
||||
{
|
||||
match = GL_TRUE;
|
||||
for(i=0; i<context->nNumActiveAos; i++)
|
||||
{
|
||||
if (vp->aos_desc[i].size != context->stream_desc[i].size ||
|
||||
vp->aos_desc[i].format != context->stream_desc[i].format)
|
||||
{
|
||||
match = GL_FALSE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (match)
|
||||
{
|
||||
context->selected_vp = vp;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
vp = evergreenTranslateVertexShader(ctx, &(vpc->mesa_program));
|
||||
if(!vp)
|
||||
{
|
||||
radeon_error("Failed to translate vertex shader. \n");
|
||||
return;
|
||||
}
|
||||
vp->next = vpc->progs;
|
||||
vpc->progs = vp;
|
||||
context->selected_vp = vp;
|
||||
return;
|
||||
}
|
||||
|
||||
int evergreen_getTypeSize(GLenum type)
|
||||
{
|
||||
switch (type)
|
||||
{
|
||||
case GL_DOUBLE:
|
||||
return sizeof(GLdouble);
|
||||
case GL_FLOAT:
|
||||
return sizeof(GLfloat);
|
||||
case GL_INT:
|
||||
return sizeof(GLint);
|
||||
case GL_UNSIGNED_INT:
|
||||
return sizeof(GLuint);
|
||||
case GL_SHORT:
|
||||
return sizeof(GLshort);
|
||||
case GL_UNSIGNED_SHORT:
|
||||
return sizeof(GLushort);
|
||||
case GL_BYTE:
|
||||
return sizeof(GLbyte);
|
||||
case GL_UNSIGNED_BYTE:
|
||||
return sizeof(GLubyte);
|
||||
default:
|
||||
assert(0);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static void evergreenTranslateAttrib(GLcontext *ctx, GLuint unLoc, int count, const struct gl_client_array *input)
|
||||
{
|
||||
context_t *context = EVERGREEN_CONTEXT(ctx);
|
||||
|
||||
StreamDesc * pStreamDesc = &(context->stream_desc[context->nNumActiveAos]);
|
||||
|
||||
GLuint stride;
|
||||
|
||||
stride = (input->StrideB == 0) ? evergreen_getTypeSize(input->Type) * input->Size
|
||||
: input->StrideB;
|
||||
|
||||
if (input->Type == GL_DOUBLE || input->Type == GL_UNSIGNED_INT || input->Type == GL_INT ||
|
||||
#if MESA_BIG_ENDIAN
|
||||
evergreen_getTypeSize(input->Type) != 4 ||
|
||||
#endif
|
||||
stride < 4)
|
||||
{
|
||||
pStreamDesc->type = GL_FLOAT;
|
||||
|
||||
if (input->StrideB == 0)
|
||||
{
|
||||
pStreamDesc->stride = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
pStreamDesc->stride = sizeof(GLfloat) * input->Size;
|
||||
}
|
||||
pStreamDesc->dwords = input->Size;
|
||||
pStreamDesc->is_named_bo = GL_FALSE;
|
||||
}
|
||||
else
|
||||
{
|
||||
pStreamDesc->type = input->Type;
|
||||
pStreamDesc->dwords = (evergreen_getTypeSize(input->Type) * input->Size + 3)/ 4;
|
||||
if (!input->BufferObj->Name)
|
||||
{
|
||||
if (input->StrideB == 0)
|
||||
{
|
||||
pStreamDesc->stride = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
pStreamDesc->stride = (evergreen_getTypeSize(pStreamDesc->type) * input->Size + 3) & ~3;
|
||||
}
|
||||
|
||||
pStreamDesc->is_named_bo = GL_FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
pStreamDesc->size = input->Size;
|
||||
pStreamDesc->dst_loc = context->nNumActiveAos;
|
||||
pStreamDesc->element = unLoc;
|
||||
pStreamDesc->format = input->Format;
|
||||
|
||||
switch (pStreamDesc->type)
|
||||
{ //GetSurfaceFormat
|
||||
case GL_FLOAT:
|
||||
pStreamDesc->_signed = 0;
|
||||
pStreamDesc->normalize = GL_FALSE;
|
||||
break;
|
||||
case GL_SHORT:
|
||||
pStreamDesc->_signed = 1;
|
||||
pStreamDesc->normalize = input->Normalized;
|
||||
break;
|
||||
case GL_BYTE:
|
||||
pStreamDesc->_signed = 1;
|
||||
pStreamDesc->normalize = input->Normalized;
|
||||
break;
|
||||
case GL_UNSIGNED_SHORT:
|
||||
pStreamDesc->_signed = 0;
|
||||
pStreamDesc->normalize = input->Normalized;
|
||||
break;
|
||||
case GL_UNSIGNED_BYTE:
|
||||
pStreamDesc->_signed = 0;
|
||||
pStreamDesc->normalize = input->Normalized;
|
||||
break;
|
||||
default:
|
||||
case GL_INT:
|
||||
case GL_UNSIGNED_INT:
|
||||
case GL_DOUBLE:
|
||||
assert(0);
|
||||
break;
|
||||
}
|
||||
context->nNumActiveAos++;
|
||||
}
|
||||
|
||||
void evergreenSetVertexFormat(GLcontext *ctx, const struct gl_client_array *arrays[], int count)
|
||||
{
|
||||
context_t *context = EVERGREEN_CONTEXT(ctx);
|
||||
struct evergreen_vertex_program *vpc
|
||||
= (struct evergreen_vertex_program *)ctx->VertexProgram._Current;
|
||||
|
||||
struct gl_vertex_program * mesa_vp = (struct gl_vertex_program *)&(vpc->mesa_program);
|
||||
unsigned int unLoc = 0;
|
||||
unsigned int unBit = mesa_vp->Base.InputsRead;
|
||||
context->nNumActiveAos = 0;
|
||||
|
||||
if (mesa_vp->IsPositionInvariant)
|
||||
{
|
||||
unBit |= VERT_BIT_POS;
|
||||
}
|
||||
|
||||
while(unBit)
|
||||
{
|
||||
if(unBit & 1)
|
||||
{
|
||||
evergreenTranslateAttrib(ctx, unLoc, count, arrays[unLoc]);
|
||||
}
|
||||
|
||||
unBit >>= 1;
|
||||
++unLoc;
|
||||
}
|
||||
context->radeon.tcl.aos_count = context->nNumActiveAos;
|
||||
}
|
||||
|
||||
void * evergreenGetActiveVpShaderBo(GLcontext * ctx)
|
||||
{
|
||||
context_t *context = EVERGREEN_CONTEXT(ctx);
|
||||
struct evergreen_vertex_program *vp = context->selected_vp;;
|
||||
|
||||
if (vp)
|
||||
return vp->shaderbo;
|
||||
else
|
||||
return NULL;
|
||||
}
|
||||
|
||||
void * evergreenGetActiveVpShaderConstBo(GLcontext * ctx)
|
||||
{
|
||||
context_t *context = EVERGREEN_CONTEXT(ctx);
|
||||
struct evergreen_vertex_program *vp = context->selected_vp;;
|
||||
|
||||
if (vp)
|
||||
return vp->constbo0;
|
||||
else
|
||||
return NULL;
|
||||
}
|
||||
|
||||
GLboolean evergreenSetupVertexProgram(GLcontext * ctx)
|
||||
{
|
||||
context_t *context = EVERGREEN_CONTEXT(ctx);
|
||||
EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
|
||||
struct evergreen_vertex_program *vp = context->selected_vp;
|
||||
|
||||
struct gl_program_parameter_list *paramList;
|
||||
unsigned int unNumParamData;
|
||||
unsigned int ui;
|
||||
|
||||
if(GL_FALSE == vp->loaded)
|
||||
{
|
||||
if(vp->r700Shader.bNeedsAssembly == GL_TRUE)
|
||||
{
|
||||
Assemble( &(vp->r700Shader) );
|
||||
}
|
||||
|
||||
/* Load vp to gpu */
|
||||
r600EmitShader(ctx,
|
||||
&(vp->shaderbo),
|
||||
(GLvoid *)(vp->r700Shader.pProgram),
|
||||
vp->r700Shader.uShaderBinaryDWORDSize,
|
||||
"VS");
|
||||
|
||||
vp->loaded = GL_TRUE;
|
||||
}
|
||||
|
||||
EVERGREEN_STATECHANGE(context, vs);
|
||||
|
||||
/* TODO : enable this after MemUse fixed *=
|
||||
(context->chipobj.MemUse)(context, vp->shadercode.buf->id);
|
||||
*/
|
||||
|
||||
evergreen->SQ_PGM_RESOURCES_VS.u32All = 0;
|
||||
SETbit(evergreen->SQ_PGM_RESOURCES_VS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit);
|
||||
|
||||
evergreen->vs.SQ_ALU_CONST_CACHE_VS_0.u32All = 0; /* set from buffer object. */
|
||||
|
||||
evergreen->vs.SQ_PGM_START_VS.u32All = 0;
|
||||
|
||||
SETfield(evergreen->SQ_PGM_RESOURCES_VS.u32All, vp->r700Shader.nRegs + 1,
|
||||
NUM_GPRS_shift, NUM_GPRS_mask);
|
||||
|
||||
if(vp->r700Shader.uStackSize) /* we don't use branch for now, it should be zero. */
|
||||
{
|
||||
SETfield(evergreen->SQ_PGM_RESOURCES_VS.u32All, vp->r700Shader.uStackSize,
|
||||
STACK_SIZE_shift, STACK_SIZE_mask);
|
||||
}
|
||||
|
||||
EVERGREEN_STATECHANGE(context, spi);
|
||||
|
||||
SETfield(evergreen->SPI_VS_OUT_CONFIG.u32All,
|
||||
vp->r700Shader.nParamExports ? (vp->r700Shader.nParamExports - 1) : 0,
|
||||
VS_EXPORT_COUNT_shift, VS_EXPORT_COUNT_mask);
|
||||
SETfield(evergreen->SPI_PS_IN_CONTROL_0.u32All, vp->r700Shader.nParamExports,
|
||||
NUM_INTERP_shift, NUM_INTERP_mask);
|
||||
|
||||
/*
|
||||
SETbit(evergreen->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
|
||||
CLEARbit(evergreen->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
|
||||
*/
|
||||
|
||||
/* sent out shader constants. */
|
||||
paramList = vp->mesa_program->Base.Parameters;
|
||||
|
||||
if(NULL != paramList) {
|
||||
/* vp->mesa_program was cloned, not updated by glsl shader api. */
|
||||
/* _mesa_reference_program has already checked glsl shProg is ok and set ctx->VertexProgem._Current */
|
||||
/* so, use ctx->VertexProgem._Current */
|
||||
struct gl_program_parameter_list *paramListOrginal =
|
||||
ctx->VertexProgram._Current->Base.Parameters;
|
||||
|
||||
_mesa_load_state_parameters(ctx, paramList);
|
||||
|
||||
if (paramList->NumParameters > EVERGREEN_MAX_DX9_CONSTS)
|
||||
return GL_FALSE;
|
||||
|
||||
EVERGREEN_STATECHANGE(context, vs);
|
||||
|
||||
evergreen->vs.num_consts = paramList->NumParameters;
|
||||
|
||||
unNumParamData = paramList->NumParameters;
|
||||
|
||||
for(ui=0; ui<unNumParamData; ui++) {
|
||||
if(paramList->Parameters[ui].Type == PROGRAM_UNIFORM)
|
||||
{
|
||||
evergreen->vs.consts[ui][0].f32All = paramListOrginal->ParameterValues[ui][0];
|
||||
evergreen->vs.consts[ui][1].f32All = paramListOrginal->ParameterValues[ui][1];
|
||||
evergreen->vs.consts[ui][2].f32All = paramListOrginal->ParameterValues[ui][2];
|
||||
evergreen->vs.consts[ui][3].f32All = paramListOrginal->ParameterValues[ui][3];
|
||||
}
|
||||
else
|
||||
{
|
||||
evergreen->vs.consts[ui][0].f32All = paramList->ParameterValues[ui][0];
|
||||
evergreen->vs.consts[ui][1].f32All = paramList->ParameterValues[ui][1];
|
||||
evergreen->vs.consts[ui][2].f32All = paramList->ParameterValues[ui][2];
|
||||
evergreen->vs.consts[ui][3].f32All = paramList->ParameterValues[ui][3];
|
||||
}
|
||||
}
|
||||
|
||||
radeonAllocDmaRegion(&context->radeon,
|
||||
&context->vp_Constbo,
|
||||
&context->vp_bo_offset,
|
||||
256,
|
||||
256);
|
||||
r600EmitShaderConsts(ctx,
|
||||
context->vp_Constbo,
|
||||
context->vp_bo_offset,
|
||||
(GLvoid *)&(evergreen->vs.consts[0][0]),
|
||||
unNumParamData * 4 * 4);
|
||||
} else
|
||||
evergreen->vs.num_consts = 0;
|
||||
|
||||
COMPILED_SUB * pCompiledSub;
|
||||
GLuint uj;
|
||||
GLuint unConstOffset = evergreen->vs.num_consts;
|
||||
for(ui=0; ui<vp->r700AsmCode.unNumPresub; ui++)
|
||||
{
|
||||
pCompiledSub = vp->r700AsmCode.presubs[ui].pCompiledSub;
|
||||
|
||||
evergreen->vs.num_consts += pCompiledSub->NumParameters;
|
||||
|
||||
for(uj=0; uj<pCompiledSub->NumParameters; uj++)
|
||||
{
|
||||
evergreen->vs.consts[uj + unConstOffset][0].f32All = pCompiledSub->ParameterValues[uj][0];
|
||||
evergreen->vs.consts[uj + unConstOffset][1].f32All = pCompiledSub->ParameterValues[uj][1];
|
||||
evergreen->vs.consts[uj + unConstOffset][2].f32All = pCompiledSub->ParameterValues[uj][2];
|
||||
evergreen->vs.consts[uj + unConstOffset][3].f32All = pCompiledSub->ParameterValues[uj][3];
|
||||
}
|
||||
unConstOffset += pCompiledSub->NumParameters;
|
||||
}
|
||||
|
||||
return GL_TRUE;
|
||||
}
|
||||
|
|
@ -0,0 +1,107 @@
|
|||
/*
|
||||
* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Authors:
|
||||
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _EVERGREEN_VERTPROG_H_
|
||||
#define _EVERGREEN_VERTPROG_H_
|
||||
|
||||
#include "main/glheader.h"
|
||||
#include "main/mtypes.h"
|
||||
|
||||
#include "r700_shader.h"
|
||||
#include "r700_assembler.h"
|
||||
|
||||
typedef struct evergreenArrayDesc //TEMP
|
||||
{
|
||||
GLint size; //number of data element
|
||||
GLenum type; //data element type
|
||||
GLsizei stride;
|
||||
GLenum format; //GL_RGBA or GL_BGRA
|
||||
} evergreenArrayDesc;
|
||||
|
||||
struct evergreen_vertex_program
|
||||
{
|
||||
struct gl_vertex_program *mesa_program; /* Must be first */
|
||||
|
||||
struct evergreen_vertex_program *next;
|
||||
|
||||
r700_AssemblerBase r700AsmCode;
|
||||
R700_Shader r700Shader;
|
||||
|
||||
GLboolean translated;
|
||||
GLboolean loaded;
|
||||
|
||||
void * shaderbo;
|
||||
|
||||
GLuint K0used;
|
||||
void * constbo0;
|
||||
|
||||
evergreenArrayDesc aos_desc[VERT_ATTRIB_MAX];
|
||||
};
|
||||
|
||||
struct evergreen_vertex_program_cont
|
||||
{
|
||||
struct gl_vertex_program mesa_program;
|
||||
|
||||
struct evergreen_vertex_program *progs;
|
||||
};
|
||||
|
||||
//Internal
|
||||
unsigned int evergreen_Map_Vertex_Output(r700_AssemblerBase *pAsm,
|
||||
struct gl_vertex_program *mesa_vp,
|
||||
unsigned int unStart);
|
||||
unsigned int evergreen_Map_Vertex_Input(r700_AssemblerBase *pAsm,
|
||||
struct gl_vertex_program *mesa_vp,
|
||||
unsigned int unStart);
|
||||
GLboolean evergreen_Process_Vertex_Program_Vfetch_Instructions(
|
||||
struct evergreen_vertex_program *vp,
|
||||
struct gl_vertex_program *mesa_vp);
|
||||
GLboolean evergreen_Process_Vertex_Program_Vfetch_Instructions2(
|
||||
GLcontext *ctx,
|
||||
struct evergreen_vertex_program *vp,
|
||||
struct gl_vertex_program *mesa_vp);
|
||||
void evergreen_Map_Vertex_Program(GLcontext *ctx,
|
||||
struct evergreen_vertex_program *vp,
|
||||
struct gl_vertex_program *mesa_vp);
|
||||
GLboolean evergreen_Find_Instruction_Dependencies_vp(struct evergreen_vertex_program *vp,
|
||||
struct gl_vertex_program *mesa_vp);
|
||||
|
||||
struct evergreen_vertex_program* evergreenTranslateVertexShader(GLcontext *ctx,
|
||||
struct gl_vertex_program *mesa_vp);
|
||||
|
||||
/* Interface */
|
||||
extern void evergreenSelectVertexShader(GLcontext *ctx);
|
||||
extern void evergreenSetVertexFormat(GLcontext *ctx, const struct gl_client_array *arrays[], int count);
|
||||
|
||||
extern GLboolean evergreenSetupVertexProgram(GLcontext * ctx);
|
||||
|
||||
extern void * evergreenGetActiveVpShaderBo(GLcontext * ctx);
|
||||
|
||||
extern void * evergreenGetActiveVpShaderConstBo(GLcontext * ctx);
|
||||
|
||||
extern int evergreen_getTypeSize(GLenum type);
|
||||
|
||||
#endif /* _EVERGREEN_VERTPROG_H_ */
|
||||
|
|
@ -473,7 +473,14 @@ void r600InitCmdBuf(context_t *r600) /* from rcommonInitCmdBuf */
|
|||
radeonContextPtr rmesa = &r600->radeon;
|
||||
GLuint size;
|
||||
|
||||
r600InitAtoms(r600);
|
||||
if(r600->radeon.radeonScreen->chip_family >= CHIP_FAMILY_CEDAR)
|
||||
{
|
||||
evergreenInitAtoms(r600);
|
||||
}
|
||||
else
|
||||
{
|
||||
r600InitAtoms(r600);
|
||||
}
|
||||
|
||||
/* Initialize command buffer */
|
||||
size = 256 * driQueryOptioni(&rmesa->optionCache,
|
||||
|
|
|
|||
|
|
@ -190,6 +190,46 @@ do { \
|
|||
#define R600_OUT_BATCH_REGSEQ(reg, count) \
|
||||
R600_OUT_BATCH_REGS((reg), (count))
|
||||
|
||||
/* evergreen */
|
||||
#define EVERGREEN_OUT_BATCH_REGS(reg, num) \
|
||||
do { \
|
||||
if ((reg) >= R600_SET_CONFIG_REG_OFFSET && (reg) < R600_SET_CONFIG_REG_END) { \
|
||||
R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, (num))); \
|
||||
R600_OUT_BATCH(((reg) - R600_SET_CONFIG_REG_OFFSET) >> 2); \
|
||||
} else if ((reg) >= R600_SET_CONTEXT_REG_OFFSET && (reg) < R600_SET_CONTEXT_REG_END) { \
|
||||
R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONTEXT_REG, (num))); \
|
||||
R600_OUT_BATCH(((reg) - R600_SET_CONTEXT_REG_OFFSET) >> 2); \
|
||||
} else if ((reg) >= EG_SET_RESOURCE_OFFSET && (reg) < EG_SET_RESOURCE_END) { \
|
||||
R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, (num))); \
|
||||
R600_OUT_BATCH(((reg) - EG_SET_RESOURCE_OFFSET) >> 2); \
|
||||
} else if ((reg) >= EG_SET_LOOP_CONST_OFFSET && (reg) < EG_SET_LOOP_CONST_END) { \
|
||||
R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_LOOP_CONST, (num))); \
|
||||
R600_OUT_BATCH(((reg) - EG_SET_LOOP_CONST_OFFSET) >> 2); \
|
||||
} else if ((reg) >= R600_SET_SAMPLER_OFFSET && (reg) < R600_SET_SAMPLER_END) { \
|
||||
R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, (num))); \
|
||||
R600_OUT_BATCH(((reg) - R600_SET_SAMPLER_OFFSET) >> 2); \
|
||||
} else if ((reg) >= R600_SET_CTL_CONST_OFFSET && (reg) < R600_SET_CTL_CONST_END) { \
|
||||
R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, (num))); \
|
||||
R600_OUT_BATCH(((reg) - R600_SET_CTL_CONST_OFFSET) >> 2); \
|
||||
} else if ((reg) >= EG_SET_BOOL_CONST_OFFSET && (reg) < EG_SET_BOOL_CONST_END) { \
|
||||
R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_BOOL_CONST, (num))); \
|
||||
R600_OUT_BATCH(((reg) - EG_SET_BOOL_CONST_OFFSET) >> 2); \
|
||||
} else { \
|
||||
R600_OUT_BATCH(CP_PACKET0((reg), (num))); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
/** Single register write to command buffer; requires 3 dwords for most things. */
|
||||
#define EVERGREEN_OUT_BATCH_REGVAL(reg, val) \
|
||||
EVERGREEN_OUT_BATCH_REGS((reg), 1); \
|
||||
R600_OUT_BATCH((val))
|
||||
|
||||
/** Continuous register range write to command buffer; requires 1 dword,
|
||||
* expects count dwords afterwards for register contents. */
|
||||
#define EVERGREEN_OUT_BATCH_REGSEQ(reg, count) \
|
||||
EVERGREEN_OUT_BATCH_REGS((reg), (count))
|
||||
|
||||
|
||||
extern void r600InitCmdBuf(context_t *r600);
|
||||
|
||||
#endif /* __R600_CMDBUF_H__ */
|
||||
|
|
|
|||
|
|
@ -66,6 +66,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|||
#include "r700_state.h"
|
||||
#include "r700_ioctl.h"
|
||||
|
||||
#include "evergreen_context.h"
|
||||
#include "evergreen_state.h"
|
||||
#include "evergreen_tex.h"
|
||||
#include "evergreen_ioctl.h"
|
||||
#include "evergreen_oglprog.h"
|
||||
|
||||
#include "utils.h"
|
||||
|
||||
|
|
@ -247,6 +252,19 @@ static void r600_init_vtbl(radeonContextPtr radeon)
|
|||
|
||||
static void r600InitConstValues(GLcontext *ctx, radeonScreenPtr screen)
|
||||
{
|
||||
context_t *context = R700_CONTEXT(ctx);
|
||||
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
|
||||
|
||||
if( (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_CEDAR)
|
||||
&&(context->radeon.radeonScreen->chip_family <= CHIP_FAMILY_HEMLOCK) )
|
||||
{
|
||||
r700->bShaderUseMemConstant = GL_TRUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
r700->bShaderUseMemConstant = GL_FALSE;
|
||||
}
|
||||
|
||||
ctx->Const.MaxTextureImageUnits = 16;
|
||||
/* 8 per clause on r6xx, 16 on r7xx
|
||||
* but I think mesa only supports 8 at the moment
|
||||
|
|
@ -381,18 +399,45 @@ GLboolean r600CreateContext(gl_api api,
|
|||
r600ParseOptions(r600, screen);
|
||||
|
||||
r600->radeon.radeonScreen = screen;
|
||||
r600_init_vtbl(&r600->radeon);
|
||||
|
||||
if(screen->chip_family >= CHIP_FAMILY_CEDAR)
|
||||
{
|
||||
evergreen_init_vtbl(&r600->radeon);
|
||||
}
|
||||
else
|
||||
{
|
||||
r600_init_vtbl(&r600->radeon);
|
||||
}
|
||||
|
||||
/* Init default driver functions then plug in our R600-specific functions
|
||||
* (the texture functions are especially important)
|
||||
*/
|
||||
_mesa_init_driver_functions(&functions);
|
||||
|
||||
r700InitStateFuncs(&r600->radeon, &functions);
|
||||
r600InitTextureFuncs(&r600->radeon, &functions);
|
||||
r700InitShaderFuncs(&functions);
|
||||
if(screen->chip_family >= CHIP_FAMILY_CEDAR)
|
||||
{
|
||||
evergreenCreateChip(r600);
|
||||
evergreenInitStateFuncs(&r600->radeon, &functions);
|
||||
evergreenInitTextureFuncs(&r600->radeon, &functions);
|
||||
evergreenInitShaderFuncs(&functions);
|
||||
}
|
||||
else
|
||||
{
|
||||
r700InitStateFuncs(&r600->radeon, &functions);
|
||||
r600InitTextureFuncs(&r600->radeon, &functions);
|
||||
r700InitShaderFuncs(&functions);
|
||||
}
|
||||
|
||||
radeonInitQueryObjFunctions(&functions);
|
||||
r700InitIoctlFuncs(&functions);
|
||||
|
||||
if(screen->chip_family >= CHIP_FAMILY_CEDAR)
|
||||
{
|
||||
evergreenInitIoctlFuncs(&functions);
|
||||
}
|
||||
else
|
||||
{
|
||||
r700InitIoctlFuncs(&functions);
|
||||
}
|
||||
radeonInitBufferObjectFuncs(&functions);
|
||||
|
||||
if (!radeonInitContext(&r600->radeon, &functions,
|
||||
|
|
@ -435,16 +480,46 @@ GLboolean r600CreateContext(gl_api api,
|
|||
|
||||
radeon_init_debug();
|
||||
|
||||
r700InitDraw(ctx);
|
||||
if(screen->chip_family >= CHIP_FAMILY_CEDAR)
|
||||
{
|
||||
evergreenInitDraw(ctx);
|
||||
}
|
||||
else
|
||||
{
|
||||
r700InitDraw(ctx);
|
||||
}
|
||||
|
||||
radeon_fbo_init(&r600->radeon);
|
||||
radeonInitSpanFuncs( ctx );
|
||||
r600InitCmdBuf(r600);
|
||||
r700InitState(r600->radeon.glCtx);
|
||||
|
||||
if(screen->chip_family >= CHIP_FAMILY_CEDAR)
|
||||
{
|
||||
evergreenInitState(r600->radeon.glCtx);
|
||||
}
|
||||
else
|
||||
{
|
||||
r700InitState(r600->radeon.glCtx);
|
||||
}
|
||||
|
||||
r600InitGLExtensions(ctx);
|
||||
|
||||
return GL_TRUE;
|
||||
}
|
||||
|
||||
void r600DestroyContext(__DRIcontext *driContextPriv )
|
||||
{
|
||||
void *pChip;
|
||||
context_t *context = (context_t *) driContextPriv->driverPrivate;
|
||||
|
||||
assert(context);
|
||||
|
||||
pChip = context->pChip;
|
||||
|
||||
/* destroy context first, free pChip, in case there are things flush to asic. */
|
||||
radeonDestroyContext(driContextPriv);
|
||||
|
||||
FREE(pChip);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -53,6 +53,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|||
#include "r700_oglprog.h"
|
||||
#include "r700_vertprog.h"
|
||||
|
||||
#include "evergreen_chip.h"
|
||||
|
||||
struct r600_context;
|
||||
typedef struct r600_context context_t;
|
||||
|
||||
|
|
@ -63,6 +65,10 @@ typedef struct r600_context context_t;
|
|||
#include "tnl_dd/t_dd_vertex.h"
|
||||
#undef TAG
|
||||
|
||||
#define FORCE_CF_TEX_BARRIER 1
|
||||
|
||||
/* #define GENERATE_SHADER_FOR_2D 1 */
|
||||
|
||||
#define R600_FALLBACK_NONE 0
|
||||
#define R600_FALLBACK_TCL 1
|
||||
#define R600_FALLBACK_RAST 2
|
||||
|
|
@ -103,6 +109,24 @@ struct r600_hw_state {
|
|||
struct radeon_state_atom tx_brdr_clr;
|
||||
};
|
||||
|
||||
struct evergreen_hw_state {
|
||||
struct radeon_state_atom one_time_init;
|
||||
struct radeon_state_atom init;
|
||||
struct radeon_state_atom pa;
|
||||
struct radeon_state_atom vgt;
|
||||
struct radeon_state_atom tp;
|
||||
struct radeon_state_atom sq;
|
||||
struct radeon_state_atom vs;
|
||||
struct radeon_state_atom spi;
|
||||
struct radeon_state_atom sx;
|
||||
struct radeon_state_atom tx;
|
||||
struct radeon_state_atom db;
|
||||
struct radeon_state_atom cb;
|
||||
struct radeon_state_atom vtx;
|
||||
struct radeon_state_atom cp;
|
||||
struct radeon_state_atom timestamp;
|
||||
};
|
||||
|
||||
typedef struct StreamDesc
|
||||
{
|
||||
GLint size; //number of data element
|
||||
|
|
@ -141,6 +165,9 @@ struct r600_context {
|
|||
|
||||
struct r600_hw_state atoms;
|
||||
|
||||
struct evergreen_hw_state evergreen_atoms;
|
||||
void * pChip;
|
||||
|
||||
struct r700_vertex_program *selected_vp;
|
||||
|
||||
/* Vertex buffers
|
||||
|
|
@ -150,16 +177,29 @@ struct r600_context {
|
|||
struct r700_index_buffer ind_buf;
|
||||
struct radeon_bo *blit_bo;
|
||||
GLboolean blit_bo_loaded;
|
||||
|
||||
/* Shader const buffer */
|
||||
struct radeon_bo * vp_Constbo;
|
||||
int vp_bo_offset;
|
||||
struct radeon_bo * fp_Constbo;
|
||||
int fp_bo_offset;
|
||||
};
|
||||
|
||||
#define EVERGREEN_CONTEXT(ctx) ((context_t *)(ctx->DriverCtx))
|
||||
|
||||
#define R700_CONTEXT(ctx) ((context_t *)(ctx->DriverCtx))
|
||||
#define GL_CONTEXT(context) ((GLcontext *)(context->radeon.glCtx))
|
||||
|
||||
#define GET_EVERGREEN_CHIP(context) ((EVERGREEN_CHIP_CONTEXT*)(context->pChip))
|
||||
|
||||
extern GLboolean r600CreateContext(gl_api api,
|
||||
const __GLcontextModes * glVisual,
|
||||
__DRIcontext * driContextPriv,
|
||||
void *sharedContextPrivate);
|
||||
|
||||
extern void r600DestroyContext(__DRIcontext *driContextPriv );
|
||||
extern void evergreenCreateChip(context_t *context);
|
||||
|
||||
#define R700_CONTEXT_STATES(context) ((R700_CHIP_CONTEXT *)(&context->hw))
|
||||
|
||||
#define R600_NEWPRIM( rmesa ) \
|
||||
|
|
@ -175,6 +215,13 @@ do { \
|
|||
r600->radeon.hw.is_dirty = GL_TRUE; \
|
||||
} while(0)
|
||||
|
||||
#define EVERGREEN_STATECHANGE(r600, ATOM) \
|
||||
do { \
|
||||
R600_NEWPRIM(r600); \
|
||||
r600->evergreen_atoms.ATOM.dirty = GL_TRUE; \
|
||||
r600->radeon.hw.is_dirty = GL_TRUE; \
|
||||
} while(0)
|
||||
|
||||
extern GLboolean r700SyncSurf(context_t *context,
|
||||
struct radeon_bo *pbo,
|
||||
uint32_t read_domain,
|
||||
|
|
@ -187,6 +234,9 @@ extern void r700Start3D(context_t *context);
|
|||
extern void r600InitAtoms(context_t *context);
|
||||
extern void r700InitDraw(GLcontext *ctx);
|
||||
|
||||
extern void evergreenInitAtoms(context_t *context);
|
||||
extern void evergreenInitDraw(GLcontext *ctx);
|
||||
|
||||
#define RADEON_D_CAPTURE 0
|
||||
#define RADEON_D_PLAYBACK 1
|
||||
#define RADEON_D_PLAYBACK_RAW 2
|
||||
|
|
|
|||
|
|
@ -49,6 +49,72 @@ void r600EmitCacheFlush(context_t *rmesa)
|
|||
{
|
||||
}
|
||||
|
||||
GLboolean r600AllocShaderConsts(GLcontext * ctx,
|
||||
void ** constbo,
|
||||
int sizeinBYTE,
|
||||
char * szShaderUsage)
|
||||
{
|
||||
radeonContextPtr radeonctx = RADEON_CONTEXT(ctx);
|
||||
struct radeon_bo * pbo;
|
||||
uint32_t *out;
|
||||
|
||||
if(sizeinBYTE < 64) /* SQ_ALU_CONST_BUFFER_SIZE need 64 bytes at least to be non 0 */
|
||||
{
|
||||
sizeinBYTE = 64;
|
||||
}
|
||||
|
||||
shader_again_alloc:
|
||||
pbo = radeon_bo_open(radeonctx->radeonScreen->bom,
|
||||
0,
|
||||
sizeinBYTE,
|
||||
256,
|
||||
RADEON_GEM_DOMAIN_GTT,
|
||||
0);
|
||||
|
||||
radeon_print(RADEON_SHADER, RADEON_NORMAL, "%s %p size %d: %s\n", __func__, pbo, sizeinBYTE, szShaderUsage);
|
||||
|
||||
if (!pbo) {
|
||||
radeon_print(RADEON_MEMORY | RADEON_CS, RADEON_IMPORTANT, "No memory for buffer object. Flushing command buffer.\n");
|
||||
rcommonFlushCmdBuf(radeonctx, __FUNCTION__);
|
||||
goto shader_again_alloc;
|
||||
}
|
||||
|
||||
radeon_cs_space_add_persistent_bo(radeonctx->cmdbuf.cs,
|
||||
pbo,
|
||||
RADEON_GEM_DOMAIN_GTT, 0);
|
||||
|
||||
if (radeon_cs_space_check_with_bo(radeonctx->cmdbuf.cs,
|
||||
pbo,
|
||||
RADEON_GEM_DOMAIN_GTT, 0)) {
|
||||
radeon_error("failure to revalidate BOs - badness\n");
|
||||
return GL_FALSE;
|
||||
}
|
||||
|
||||
*constbo = (void*)pbo;
|
||||
|
||||
return GL_TRUE;
|
||||
}
|
||||
GLboolean r600EmitShaderConsts(GLcontext * ctx,
|
||||
void * constbo,
|
||||
int bo_offset,
|
||||
GLvoid * data,
|
||||
int sizeinBYTE)
|
||||
{
|
||||
struct radeon_bo * pbo = (struct radeon_bo *)constbo;
|
||||
uint8_t *out;
|
||||
|
||||
radeon_bo_map(pbo, 1);
|
||||
|
||||
out = (uint8_t*)(pbo->ptr);
|
||||
out = (uint8_t*)ADD_POINTERS(pbo->ptr, bo_offset);
|
||||
|
||||
memcpy(out, data, sizeinBYTE);
|
||||
|
||||
radeon_bo_unmap(pbo);
|
||||
|
||||
return GL_TRUE;
|
||||
}
|
||||
|
||||
GLboolean r600EmitShader(GLcontext * ctx,
|
||||
void ** shaderbo,
|
||||
GLvoid * data,
|
||||
|
|
|
|||
|
|
@ -52,4 +52,14 @@ extern GLboolean r600EmitShader(GLcontext * ctx,
|
|||
extern GLboolean r600DeleteShader(GLcontext * ctx,
|
||||
void * shaderbo);
|
||||
|
||||
extern GLboolean r600AllocShaderConsts(GLcontext * ctx,
|
||||
void ** constbo,
|
||||
int sizeinBYTE,
|
||||
char * szShaderUsage);
|
||||
GLboolean r600EmitShaderConsts(GLcontext * ctx,
|
||||
void * constbo,
|
||||
int bo_offset,
|
||||
GLvoid * data,
|
||||
int sizeinBYTE);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -50,6 +50,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|||
#include "r700_fragprog.h"
|
||||
#include "r700_vertprog.h"
|
||||
|
||||
#include "evergreen_tex.h"
|
||||
|
||||
void r600UpdateTextureState(GLcontext * ctx);
|
||||
|
||||
void r600UpdateTextureState(GLcontext * ctx)
|
||||
|
|
@ -878,6 +880,18 @@ GLboolean r600ValidateBuffers(GLcontext * ctx)
|
|||
RADEON_GEM_DOMAIN_GTT, 0);
|
||||
}
|
||||
|
||||
pbo = (struct radeon_bo *)r700GetActiveFpShaderConstBo(ctx);
|
||||
if (pbo) {
|
||||
radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, pbo,
|
||||
RADEON_GEM_DOMAIN_GTT, 0);
|
||||
}
|
||||
|
||||
pbo = (struct radeon_bo *)r700GetActiveVpShaderConstBo(ctx);
|
||||
if (pbo) {
|
||||
radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, pbo,
|
||||
RADEON_GEM_DOMAIN_GTT, 0);
|
||||
}
|
||||
|
||||
ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs, first_elem(&rmesa->radeon.dma.reserved)->bo, RADEON_GEM_DOMAIN_GTT, 0);
|
||||
if (ret)
|
||||
return GL_FALSE;
|
||||
|
|
@ -897,6 +911,12 @@ void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
|
|||
if (!tObj)
|
||||
return;
|
||||
|
||||
if(rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_CEDAR)
|
||||
{
|
||||
evergreenSetTexOffset(pDRICtx, texname, offset, depth, pitch);
|
||||
return;
|
||||
}
|
||||
|
||||
t->image_override = GL_TRUE;
|
||||
|
||||
if (!offset)
|
||||
|
|
@ -989,6 +1009,12 @@ void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo
|
|||
radeon = pDRICtx->driverPrivate;
|
||||
rmesa = pDRICtx->driverPrivate;
|
||||
|
||||
if(rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_CEDAR)
|
||||
{
|
||||
evergreenSetTexBuffer(pDRICtx, target, glx_texture_format, dPriv);
|
||||
return;
|
||||
}
|
||||
|
||||
rfb = dPriv->driverPrivate;
|
||||
texUnit = &radeon->glCtx->Texture.Unit[radeon->glCtx->Texture.CurrentUnit];
|
||||
texObj = _mesa_select_tex_object(radeon->glCtx, texUnit, target);
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -464,6 +464,10 @@ typedef struct r700_AssemblerBase
|
|||
GLuint uiCurInst;
|
||||
GLubyte SamplerUnits[MAX_SAMPLERS];
|
||||
GLboolean bR6xx;
|
||||
|
||||
/* TODO : merge bR6xx */
|
||||
GLuint unAsic;
|
||||
|
||||
/* helper to decide which type of instruction to assemble */
|
||||
GLboolean is_tex;
|
||||
/* we inserted helper intructions and need barrier on next TEX ins */
|
||||
|
|
@ -489,6 +493,9 @@ typedef struct r700_AssemblerBase
|
|||
|
||||
GLuint shadow_regs[R700_MAX_TEXTURE_UNITS];
|
||||
|
||||
GLboolean bUseMemConstant;
|
||||
GLuint kcacheUsed;
|
||||
|
||||
} r700_AssemblerBase;
|
||||
|
||||
//Internal use
|
||||
|
|
@ -512,6 +519,8 @@ GLuint GetSurfaceFormat(GLenum eType, GLuint nChannels, GLuint * pClient_size);
|
|||
|
||||
unsigned int r700GetNumOperands(GLuint opcode, GLuint nIsOp3);
|
||||
|
||||
unsigned int EG_GetNumOperands(GLuint opcode, GLuint nIsOp3);
|
||||
|
||||
GLboolean IsTex(gl_inst_opcode Opcode);
|
||||
GLboolean IsAlu(gl_inst_opcode Opcode);
|
||||
int check_current_clause(r700_AssemblerBase* pAsm,
|
||||
|
|
@ -535,6 +544,18 @@ GLboolean assemble_vfetch_instruction2(r700_AssemblerBase* pAsm,
|
|||
GLboolean normalize,
|
||||
GLenum format,
|
||||
VTX_FETCH_METHOD * pFetchMethod);
|
||||
|
||||
GLboolean EG_assemble_vfetch_instruction(r700_AssemblerBase* pAsm,
|
||||
GLuint destination_register,
|
||||
GLenum type,
|
||||
GLint size,
|
||||
GLubyte element,
|
||||
GLuint _signed,
|
||||
GLboolean normalize,
|
||||
GLenum format,
|
||||
VTX_FETCH_METHOD * pFetchMethod);
|
||||
//-----------------------
|
||||
|
||||
GLboolean cleanup_vfetch_instructions(r700_AssemblerBase* pAsm);
|
||||
GLuint gethelpr(r700_AssemblerBase* pAsm);
|
||||
void resethelpr(r700_AssemblerBase* pAsm);
|
||||
|
|
@ -553,8 +574,10 @@ GLboolean assemble_tex_instruction(r700_AssemblerBase *pAsm, GLboolean normalize
|
|||
void initialize(r700_AssemblerBase *pAsm);
|
||||
GLboolean assemble_alu_src(R700ALUInstruction* alu_instruction_ptr,
|
||||
int source_index,
|
||||
PVSSRC* pSource,
|
||||
BITS scalar_channel_index);
|
||||
PVSSRC* pSource,
|
||||
BITS scalar_channel_index,
|
||||
r700_AssemblerBase *pAsm);
|
||||
|
||||
GLboolean add_alu_instruction(r700_AssemblerBase* pAsm,
|
||||
R700ALUInstruction* alu_instruction_ptr,
|
||||
GLuint contiguous_slots_needed);
|
||||
|
|
@ -664,6 +687,7 @@ GLboolean callPreSub(r700_AssemblerBase* pAsm,
|
|||
COMPILED_SUB * pCompiledSub,
|
||||
GLshort uOutReg,
|
||||
GLshort uNumValidSrc);
|
||||
GLboolean EG_add_ps_interp(r700_AssemblerBase* pAsm);
|
||||
|
||||
//Interface
|
||||
GLboolean AssembleInstr(GLuint uiFirstInst,
|
||||
|
|
|
|||
|
|
@ -721,6 +721,7 @@ static void r700SendPSState(GLcontext *ctx, struct radeon_state_atom *atom)
|
|||
context_t *context = R700_CONTEXT(ctx);
|
||||
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
|
||||
struct radeon_bo * pbo;
|
||||
struct radeon_bo * pbo_const;
|
||||
BATCH_LOCALS(&context->radeon);
|
||||
radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
|
||||
|
||||
|
|
@ -750,6 +751,9 @@ static void r700SendPSState(GLcontext *ctx, struct radeon_state_atom *atom)
|
|||
R600_OUT_BATCH_REGVAL(SQ_LOOP_CONST_0, 0x01000FFF);
|
||||
END_BATCH();
|
||||
|
||||
pbo_const = (struct radeon_bo *)r700GetActiveFpShaderConstBo(GL_CONTEXT(context));
|
||||
//TODO : set up shader const
|
||||
|
||||
COMMIT_BATCH();
|
||||
|
||||
}
|
||||
|
|
@ -759,13 +763,14 @@ static void r700SendVSState(GLcontext *ctx, struct radeon_state_atom *atom)
|
|||
context_t *context = R700_CONTEXT(ctx);
|
||||
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
|
||||
struct radeon_bo * pbo;
|
||||
struct radeon_bo * pbo_const;
|
||||
BATCH_LOCALS(&context->radeon);
|
||||
radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
|
||||
|
||||
pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
|
||||
|
||||
if (!pbo)
|
||||
return;
|
||||
return;
|
||||
|
||||
r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
|
||||
|
||||
|
|
@ -788,6 +793,29 @@ static void r700SendVSState(GLcontext *ctx, struct radeon_state_atom *atom)
|
|||
//R600_OUT_BATCH_REGVAL((SQ_LOOP_CONST_0 + (SQ_LOOP_CONST_vs<2)), 0x0100000F);
|
||||
END_BATCH();
|
||||
|
||||
/* TODO : handle 4 bufs */
|
||||
if(GL_TRUE == r700->bShaderUseMemConstant)
|
||||
{
|
||||
pbo_const = (struct radeon_bo *)r700GetActiveVpShaderConstBo(GL_CONTEXT(context));
|
||||
if(NULL != pbo_const)
|
||||
{
|
||||
r700SyncSurf(context, pbo_const, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); /* TODO : Check kc bit. */
|
||||
|
||||
BEGIN_BATCH_NO_AUTOSTATE(3);
|
||||
R600_OUT_BATCH_REGVAL(SQ_ALU_CONST_BUFFER_SIZE_VS_0, (r700->vs.num_consts * 4)/16 );
|
||||
END_BATCH();
|
||||
|
||||
BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
|
||||
R600_OUT_BATCH_REGSEQ(SQ_ALU_CONST_CACHE_VS_0, 1);
|
||||
R600_OUT_BATCH(r700->vs.SQ_ALU_CONST_CACHE_VS_0.u32All);
|
||||
R600_OUT_BATCH_RELOC(r700->vs.SQ_ALU_CONST_CACHE_VS_0.u32All,
|
||||
pbo_const,
|
||||
r700->vs.SQ_ALU_CONST_CACHE_VS_0.u32All,
|
||||
RADEON_GEM_DOMAIN_GTT, 0, 0);
|
||||
END_BATCH();
|
||||
}
|
||||
}
|
||||
|
||||
COMMIT_BATCH();
|
||||
}
|
||||
|
||||
|
|
@ -1558,45 +1586,55 @@ static void r600_init_query_stateobj(radeonContextPtr radeon, int SZ)
|
|||
|
||||
void r600InitAtoms(context_t *context)
|
||||
{
|
||||
radeon_print(RADEON_STATE, RADEON_NORMAL, "%s %p\n", __func__, context);
|
||||
context->radeon.hw.max_state_size = 10 + 5 + 14; /* start 3d, idle, cb/db flush */
|
||||
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
|
||||
radeon_print(RADEON_STATE, RADEON_NORMAL, "%s %p\n", __func__, context);
|
||||
context->radeon.hw.max_state_size = 10 + 5 + 14; /* start 3d, idle, cb/db flush */
|
||||
|
||||
/* Setup the atom linked list */
|
||||
make_empty_list(&context->radeon.hw.atomlist);
|
||||
context->radeon.hw.atomlist.name = "atom-list";
|
||||
/* Setup the atom linked list */
|
||||
make_empty_list(&context->radeon.hw.atomlist);
|
||||
context->radeon.hw.atomlist.name = "atom-list";
|
||||
|
||||
ALLOC_STATE(sq, always, 34, r700SendSQConfig);
|
||||
ALLOC_STATE(db, always, 17, r700SendDBState);
|
||||
ALLOC_STATE(stencil, always, 4, r700SendStencilState);
|
||||
ALLOC_STATE(db_target, always, 16, r700SendDepthTargetState);
|
||||
ALLOC_STATE(sc, always, 15, r700SendSCState);
|
||||
ALLOC_STATE(scissor, always, 22, r700SendScissorState);
|
||||
ALLOC_STATE(aa, always, 12, r700SendAAState);
|
||||
ALLOC_STATE(cl, always, 12, r700SendCLState);
|
||||
ALLOC_STATE(gb, always, 6, r700SendGBState);
|
||||
ALLOC_STATE(ucp, ucp, (R700_MAX_UCP * 6), r700SendUCPState);
|
||||
ALLOC_STATE(su, always, 9, r700SendSUState);
|
||||
ALLOC_STATE(poly, always, 10, r700SendPolyState);
|
||||
ALLOC_STATE(cb, cb, 18, r700SendCBState);
|
||||
ALLOC_STATE(clrcmp, always, 6, r700SendCBCLRCMPState);
|
||||
ALLOC_STATE(cb_target, always, 31, r700SendRenderTargetState);
|
||||
ALLOC_STATE(blnd, blnd, (6 + (R700_MAX_RENDER_TARGETS * 3)), r700SendCBBlendState);
|
||||
ALLOC_STATE(blnd_clr, always, 6, r700SendCBBlendColorState);
|
||||
ALLOC_STATE(sx, always, 9, r700SendSXState);
|
||||
ALLOC_STATE(vgt, always, 41, r700SendVGTState);
|
||||
ALLOC_STATE(spi, always, (59 + R700_MAX_SHADER_EXPORTS), r700SendSPIState);
|
||||
ALLOC_STATE(vpt, always, 16, r700SendViewportState);
|
||||
ALLOC_STATE(fs, always, 18, r700SendFSState);
|
||||
ALLOC_STATE(vs, always, 21, r700SendVSState);
|
||||
ALLOC_STATE(ps, always, 24, r700SendPSState);
|
||||
ALLOC_STATE(vs_consts, vs_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendVSConsts);
|
||||
ALLOC_STATE(ps_consts, ps_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendPSConsts);
|
||||
ALLOC_STATE(vtx, vtx, (VERT_ATTRIB_MAX * 18), r700SendVTXState);
|
||||
ALLOC_STATE(tx, tx, (R700_TEXTURE_NUMBERUNITS * 20), r700SendTexState);
|
||||
ALLOC_STATE(tx_smplr, tx, (R700_TEXTURE_NUMBERUNITS * 5), r700SendTexSamplerState);
|
||||
ALLOC_STATE(tx_brdr_clr, tx, (R700_TEXTURE_NUMBERUNITS * 6), r700SendTexBorderColorState);
|
||||
r600_init_query_stateobj(&context->radeon, 6 * 2);
|
||||
ALLOC_STATE(sq, always, 34, r700SendSQConfig);
|
||||
ALLOC_STATE(db, always, 17, r700SendDBState);
|
||||
ALLOC_STATE(stencil, always, 4, r700SendStencilState);
|
||||
ALLOC_STATE(db_target, always, 16, r700SendDepthTargetState);
|
||||
ALLOC_STATE(sc, always, 15, r700SendSCState);
|
||||
ALLOC_STATE(scissor, always, 22, r700SendScissorState);
|
||||
ALLOC_STATE(aa, always, 12, r700SendAAState);
|
||||
ALLOC_STATE(cl, always, 12, r700SendCLState);
|
||||
ALLOC_STATE(gb, always, 6, r700SendGBState);
|
||||
ALLOC_STATE(ucp, ucp, (R700_MAX_UCP * 6), r700SendUCPState);
|
||||
ALLOC_STATE(su, always, 9, r700SendSUState);
|
||||
ALLOC_STATE(poly, always, 10, r700SendPolyState);
|
||||
ALLOC_STATE(cb, cb, 18, r700SendCBState);
|
||||
ALLOC_STATE(clrcmp, always, 6, r700SendCBCLRCMPState);
|
||||
ALLOC_STATE(cb_target, always, 31, r700SendRenderTargetState);
|
||||
ALLOC_STATE(blnd, blnd, (6 + (R700_MAX_RENDER_TARGETS * 3)), r700SendCBBlendState);
|
||||
ALLOC_STATE(blnd_clr, always, 6, r700SendCBBlendColorState);
|
||||
ALLOC_STATE(sx, always, 9, r700SendSXState);
|
||||
ALLOC_STATE(vgt, always, 41, r700SendVGTState);
|
||||
ALLOC_STATE(spi, always, (59 + R700_MAX_SHADER_EXPORTS), r700SendSPIState);
|
||||
ALLOC_STATE(vpt, always, 16, r700SendViewportState);
|
||||
ALLOC_STATE(fs, always, 18, r700SendFSState);
|
||||
if(GL_TRUE == r700->bShaderUseMemConstant)
|
||||
{
|
||||
ALLOC_STATE(vs, always, 36, r700SendVSState);
|
||||
ALLOC_STATE(ps, always, 24, r700SendPSState); /* TODO : not imp yet, fix later. */
|
||||
}
|
||||
else
|
||||
{
|
||||
ALLOC_STATE(vs, always, 21, r700SendVSState);
|
||||
ALLOC_STATE(ps, always, 24, r700SendPSState);
|
||||
ALLOC_STATE(vs_consts, vs_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendVSConsts);
|
||||
ALLOC_STATE(ps_consts, ps_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendPSConsts);
|
||||
}
|
||||
|
||||
context->radeon.hw.is_dirty = GL_TRUE;
|
||||
context->radeon.hw.all_dirty = GL_TRUE;
|
||||
ALLOC_STATE(vtx, vtx, (VERT_ATTRIB_MAX * 18), r700SendVTXState);
|
||||
ALLOC_STATE(tx, tx, (R700_TEXTURE_NUMBERUNITS * 20), r700SendTexState);
|
||||
ALLOC_STATE(tx_smplr, tx, (R700_TEXTURE_NUMBERUNITS * 5), r700SendTexSamplerState);
|
||||
ALLOC_STATE(tx_brdr_clr, tx, (R700_TEXTURE_NUMBERUNITS * 6), r700SendTexBorderColorState);
|
||||
r600_init_query_stateobj(&context->radeon, 6 * 2);
|
||||
|
||||
context->radeon.hw.is_dirty = GL_TRUE;
|
||||
context->radeon.hw.all_dirty = GL_TRUE;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -43,6 +43,8 @@
|
|||
#define SETbit(x, bit) ( (x) |= (bit) )
|
||||
#define CLEARbit(x, bit) ( (x) &= ~(bit) )
|
||||
|
||||
#define GETbits(x, shift, mask) ( ((x) & (mask)) >> (shift) )
|
||||
|
||||
#define R700_TEXTURE_NUMBERUNITS 16
|
||||
#define R700_MAX_RENDER_TARGETS 8
|
||||
#define R700_MAX_VIEWPORTS 16
|
||||
|
|
@ -238,6 +240,9 @@ typedef struct _VS_STATE_STRUCT
|
|||
union UINT_FLOAT SQ_PGM_CF_OFFSET_VS ; /* 0xA234 */
|
||||
GLboolean dirty;
|
||||
int num_consts;
|
||||
|
||||
union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_0;
|
||||
|
||||
union UINT_FLOAT consts[R700_MAX_DX9_CONSTS][4];
|
||||
} VS_STATE_STRUCT;
|
||||
|
||||
|
|
@ -499,6 +504,8 @@ typedef struct _R700_CHIP_CONTEXT
|
|||
|
||||
GLboolean bEnablePerspective;
|
||||
|
||||
GLboolean bShaderUseMemConstant;
|
||||
|
||||
} R700_CHIP_CONTEXT;
|
||||
|
||||
#endif /* _R700_CHIP_H_ */
|
||||
|
|
|
|||
|
|
@ -362,6 +362,9 @@ GLboolean r700TranslateFragmentShader(struct r700_fragment_program *fp,
|
|||
struct gl_fragment_program *mesa_fp,
|
||||
GLcontext *ctx)
|
||||
{
|
||||
context_t *context = R700_CONTEXT(ctx);
|
||||
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
|
||||
|
||||
GLuint number_of_colors_exported;
|
||||
GLboolean z_enabled = GL_FALSE;
|
||||
GLuint unBit, shadow_unit;
|
||||
|
|
@ -373,6 +376,17 @@ GLboolean r700TranslateFragmentShader(struct r700_fragment_program *fp,
|
|||
//Init_Program
|
||||
Init_r700_AssemblerBase( SPT_FP, &(fp->r700AsmCode), &(fp->r700Shader) );
|
||||
|
||||
if(GL_TRUE == r700->bShaderUseMemConstant)
|
||||
{
|
||||
fp->r700AsmCode.bUseMemConstant = GL_TRUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
fp->r700AsmCode.bUseMemConstant = GL_FALSE;
|
||||
}
|
||||
|
||||
fp->r700AsmCode.unAsic = 7;
|
||||
|
||||
if(mesa_fp->Base.InputsRead & FRAG_BIT_WPOS)
|
||||
{
|
||||
insert_wpos_code(ctx, mesa_fp);
|
||||
|
|
@ -481,6 +495,14 @@ void * r700GetActiveFpShaderBo(GLcontext * ctx)
|
|||
return fp->shaderbo;
|
||||
}
|
||||
|
||||
void * r700GetActiveFpShaderConstBo(GLcontext * ctx)
|
||||
{
|
||||
struct r700_fragment_program *fp = (struct r700_fragment_program *)
|
||||
(ctx->FragmentProgram._Current);
|
||||
|
||||
return fp->constbo0;
|
||||
}
|
||||
|
||||
GLboolean r700SetupFragmentProgram(GLcontext * ctx)
|
||||
{
|
||||
context_t *context = R700_CONTEXT(ctx);
|
||||
|
|
@ -768,6 +790,17 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx)
|
|||
r700->ps.consts[ui][2].f32All = paramList->ParameterValues[ui][2];
|
||||
r700->ps.consts[ui][3].f32All = paramList->ParameterValues[ui][3];
|
||||
}
|
||||
|
||||
/* Load fp constants to gpu */
|
||||
if( (GL_TRUE == r700->bShaderUseMemConstant) && (unNumParamData > 0) )
|
||||
{
|
||||
r600EmitShader(ctx,
|
||||
&(fp->constbo0),
|
||||
(GLvoid *)&(paramList->ParameterValues[0][0]),
|
||||
unNumParamData * 4,
|
||||
"FS Const");
|
||||
}
|
||||
|
||||
} else
|
||||
r700->ps.num_consts = 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -43,6 +43,9 @@ struct r700_fragment_program
|
|||
|
||||
void * shaderbo;
|
||||
|
||||
GLuint k0used;
|
||||
void * constbo0;
|
||||
|
||||
GLboolean WritesDepth;
|
||||
GLuint optimization;
|
||||
};
|
||||
|
|
@ -67,4 +70,6 @@ extern GLboolean r700SetupFragmentProgram(GLcontext * ctx);
|
|||
|
||||
extern void * r700GetActiveFpShaderBo(GLcontext * ctx);
|
||||
|
||||
extern void * r700GetActiveFpShaderConstBo(GLcontext * ctx);
|
||||
|
||||
#endif /*_R700_FRAGPROG_H_*/
|
||||
|
|
|
|||
|
|
@ -48,6 +48,12 @@ static void freeVertProgCache(GLcontext *ctx, struct r700_vertex_program_cont *c
|
|||
tmp = vp->next;
|
||||
/* Release DMA region */
|
||||
r600DeleteShader(ctx, vp->shaderbo);
|
||||
|
||||
if(NULL != vp->constbo0)
|
||||
{
|
||||
r600DeleteShader(ctx, vp->constbo0);
|
||||
}
|
||||
|
||||
/* Clean up */
|
||||
Clean_Up_Assembler(&(vp->r700AsmCode));
|
||||
Clean_Up_Shader(&(vp->r700Shader));
|
||||
|
|
@ -79,6 +85,7 @@ static struct gl_program *r700NewProgram(GLcontext * ctx,
|
|||
&vpc->mesa_program,
|
||||
target,
|
||||
id);
|
||||
|
||||
break;
|
||||
case GL_FRAGMENT_PROGRAM_NV:
|
||||
case GL_FRAGMENT_PROGRAM_ARB:
|
||||
|
|
@ -92,6 +99,8 @@ static struct gl_program *r700NewProgram(GLcontext * ctx,
|
|||
|
||||
fp->shaderbo = NULL;
|
||||
|
||||
fp->constbo0 = NULL;
|
||||
|
||||
break;
|
||||
default:
|
||||
_mesa_problem(ctx, "Bad target in r700NewProgram");
|
||||
|
|
@ -121,6 +130,11 @@ static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog)
|
|||
|
||||
r600DeleteShader(ctx, fp->shaderbo);
|
||||
|
||||
if(NULL != fp->constbo0)
|
||||
{
|
||||
r600DeleteShader(ctx, fp->constbo0);
|
||||
}
|
||||
|
||||
/* Clean up */
|
||||
Clean_Up_Assembler(&(fp->r700AsmCode));
|
||||
Clean_Up_Shader(&(fp->r700Shader));
|
||||
|
|
@ -145,6 +159,13 @@ r700ProgramStringNotify(GLcontext * ctx, GLenum target, struct gl_program *prog)
|
|||
break;
|
||||
case GL_FRAGMENT_PROGRAM_ARB:
|
||||
r600DeleteShader(ctx, fp->shaderbo);
|
||||
|
||||
if(NULL != fp->constbo0)
|
||||
{
|
||||
r600DeleteShader(ctx, fp->constbo0);
|
||||
fp->constbo0 = NULL;
|
||||
}
|
||||
|
||||
Clean_Up_Assembler(&(fp->r700AsmCode));
|
||||
Clean_Up_Shader(&(fp->r700Shader));
|
||||
fp->translated = GL_FALSE;
|
||||
|
|
|
|||
|
|
@ -1580,7 +1580,16 @@ static void r700InitSQConfig(GLcontext * ctx)
|
|||
CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
|
||||
else
|
||||
SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
|
||||
SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
|
||||
|
||||
if(GL_TRUE == r700->bShaderUseMemConstant)
|
||||
{
|
||||
CLEARbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
|
||||
}
|
||||
else
|
||||
{
|
||||
SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
|
||||
}
|
||||
|
||||
SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
|
||||
SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
|
||||
SETfield(r700->sq_config.SQ_CONFIG.u32All, vs_prio, VS_PRIO_shift, VS_PRIO_mask);
|
||||
|
|
@ -1689,8 +1698,9 @@ void r700InitState(GLcontext * ctx) //-------------------
|
|||
SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
|
||||
}
|
||||
|
||||
/* Do scale XY and Z by 1/W0. */
|
||||
r700->bEnablePerspective = GL_TRUE;
|
||||
/* Do scale XY and Z by 1/W0. */
|
||||
r700->bEnablePerspective = GL_TRUE;
|
||||
|
||||
CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
|
||||
CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
|
||||
SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
|
||||
|
|
|
|||
|
|
@ -305,12 +305,17 @@ struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx,
|
|||
struct gl_vertex_program *mesa_vp)
|
||||
{
|
||||
context_t *context = R700_CONTEXT(ctx);
|
||||
|
||||
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
|
||||
|
||||
struct r700_vertex_program *vp;
|
||||
unsigned int i;
|
||||
|
||||
vp = calloc(1, sizeof(*vp));
|
||||
vp->mesa_program = _mesa_clone_vertex_program(ctx, mesa_vp);
|
||||
|
||||
vp->constbo0 = NULL;
|
||||
|
||||
if (mesa_vp->IsPositionInvariant)
|
||||
{
|
||||
_mesa_insert_mvp_code(ctx, vp->mesa_program);
|
||||
|
|
@ -331,6 +336,18 @@ struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx,
|
|||
|
||||
//Init_Program
|
||||
Init_r700_AssemblerBase(SPT_VP, &(vp->r700AsmCode), &(vp->r700Shader) );
|
||||
|
||||
if(GL_TRUE == r700->bShaderUseMemConstant)
|
||||
{
|
||||
vp->r700AsmCode.bUseMemConstant = GL_TRUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
vp->r700AsmCode.bUseMemConstant = GL_FALSE;
|
||||
}
|
||||
|
||||
vp->r700AsmCode.unAsic = 7;
|
||||
|
||||
Map_Vertex_Program(ctx, vp, vp->mesa_program );
|
||||
|
||||
if(GL_FALSE == Find_Instruction_Dependencies_vp(vp, vp->mesa_program))
|
||||
|
|
@ -576,6 +593,17 @@ void * r700GetActiveVpShaderBo(GLcontext * ctx)
|
|||
return NULL;
|
||||
}
|
||||
|
||||
void * r700GetActiveVpShaderConstBo(GLcontext * ctx)
|
||||
{
|
||||
context_t *context = R700_CONTEXT(ctx);
|
||||
struct r700_vertex_program *vp = context->selected_vp;;
|
||||
|
||||
if (vp)
|
||||
return vp->constbo0;
|
||||
else
|
||||
return NULL;
|
||||
}
|
||||
|
||||
GLboolean r700SetupVertexProgram(GLcontext * ctx)
|
||||
{
|
||||
context_t *context = R700_CONTEXT(ctx);
|
||||
|
|
@ -600,6 +628,19 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx)
|
|||
vp->r700Shader.uShaderBinaryDWORDSize,
|
||||
"VS");
|
||||
|
||||
if(GL_TRUE == r700->bShaderUseMemConstant)
|
||||
{
|
||||
paramList = vp->mesa_program->Base.Parameters;
|
||||
if(NULL != paramList)
|
||||
{
|
||||
unNumParamData = paramList->NumParameters;
|
||||
r600AllocShaderConsts(ctx,
|
||||
&(vp->constbo0),
|
||||
unNumParamData *4*4,
|
||||
"VSCON");
|
||||
}
|
||||
}
|
||||
|
||||
vp->loaded = GL_TRUE;
|
||||
}
|
||||
|
||||
|
|
@ -616,7 +657,9 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx)
|
|||
r700->vs.SQ_PGM_RESOURCES_VS.u32All = 0;
|
||||
SETbit(r700->vs.SQ_PGM_RESOURCES_VS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit);
|
||||
|
||||
r700->vs.SQ_PGM_START_VS.u32All = 0; /* set from buffer object. */
|
||||
r700->vs.SQ_ALU_CONST_CACHE_VS_0.u32All = 0; /* set from buffer object. */
|
||||
|
||||
r700->vs.SQ_PGM_START_VS.u32All = 0;
|
||||
|
||||
SETfield(r700->vs.SQ_PGM_RESOURCES_VS.u32All, vp->r700Shader.nRegs + 1,
|
||||
NUM_GPRS_shift, NUM_GPRS_mask);
|
||||
|
|
@ -687,6 +730,16 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx)
|
|||
r700->vs.consts[ui][3].f32All = paramList->ParameterValues[ui][3];
|
||||
}
|
||||
}
|
||||
|
||||
/* Load vp constants to gpu */
|
||||
if(GL_TRUE == r700->bShaderUseMemConstant)
|
||||
{
|
||||
r600EmitShaderConsts(ctx,
|
||||
vp->constbo0,
|
||||
0,
|
||||
(GLvoid *)&(r700->vs.consts[0][0]),
|
||||
unNumParamData * 4 * 4);
|
||||
}
|
||||
} else
|
||||
r700->vs.num_consts = 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -56,6 +56,9 @@ struct r700_vertex_program
|
|||
|
||||
void * shaderbo;
|
||||
|
||||
GLuint K0used;
|
||||
void * constbo0;
|
||||
|
||||
ArrayDesc aos_desc[VERT_ATTRIB_MAX];
|
||||
};
|
||||
|
||||
|
|
@ -97,6 +100,8 @@ extern GLboolean r700SetupVertexProgram(GLcontext * ctx);
|
|||
|
||||
extern void * r700GetActiveVpShaderBo(GLcontext * ctx);
|
||||
|
||||
extern void * r700GetActiveVpShaderConstBo(GLcontext * ctx);
|
||||
|
||||
extern int getTypeSize(GLenum type);
|
||||
|
||||
#endif /* _R700_VERTPROG_H_ */
|
||||
|
|
|
|||
|
|
@ -400,6 +400,46 @@
|
|||
#define PCI_CHIP_RV740_94B5 0x94B5
|
||||
#define PCI_CHIP_RV740_94B9 0x94B9
|
||||
|
||||
#define PCI_CHIP_CEDAR_68E0 0x68E0
|
||||
#define PCI_CHIP_CEDAR_68E1 0x68E1
|
||||
#define PCI_CHIP_CEDAR_68E4 0x68E4
|
||||
#define PCI_CHIP_CEDAR_68E5 0x68E5
|
||||
#define PCI_CHIP_CEDAR_68E8 0x68E8
|
||||
#define PCI_CHIP_CEDAR_68E9 0x68E9
|
||||
#define PCI_CHIP_CEDAR_68F1 0x68F1
|
||||
#define PCI_CHIP_CEDAR_68F8 0x68F8
|
||||
#define PCI_CHIP_CEDAR_68F9 0x68F9
|
||||
#define PCI_CHIP_CEDAR_68FE 0x68FE
|
||||
|
||||
#define PCI_CHIP_REDWOOD_68C0 0x68C0
|
||||
#define PCI_CHIP_REDWOOD_68C1 0x68C1
|
||||
#define PCI_CHIP_REDWOOD_68C8 0x68C8
|
||||
#define PCI_CHIP_REDWOOD_68C9 0x68C9
|
||||
#define PCI_CHIP_REDWOOD_68D8 0x68D8
|
||||
#define PCI_CHIP_REDWOOD_68D9 0x68D9
|
||||
#define PCI_CHIP_REDWOOD_68DA 0x68DA
|
||||
#define PCI_CHIP_REDWOOD_68DE 0x68DE
|
||||
|
||||
#define PCI_CHIP_JUNIPER_68A0 0x68A0
|
||||
#define PCI_CHIP_JUNIPER_68A1 0x68A1
|
||||
#define PCI_CHIP_JUNIPER_68A8 0x68A8
|
||||
#define PCI_CHIP_JUNIPER_68A9 0x68A9
|
||||
#define PCI_CHIP_JUNIPER_68B0 0x68B0
|
||||
#define PCI_CHIP_JUNIPER_68B8 0x68B8
|
||||
#define PCI_CHIP_JUNIPER_68B9 0x68B9
|
||||
#define PCI_CHIP_JUNIPER_68BE 0x68BE
|
||||
|
||||
#define PCI_CHIP_CYPRESS_6880 0x6880
|
||||
#define PCI_CHIP_CYPRESS_6888 0x6888
|
||||
#define PCI_CHIP_CYPRESS_6889 0x6889
|
||||
#define PCI_CHIP_CYPRESS_688A 0x688A
|
||||
#define PCI_CHIP_CYPRESS_6898 0x6898
|
||||
#define PCI_CHIP_CYPRESS_6899 0x6899
|
||||
#define PCI_CHIP_CYPRESS_689E 0x689E
|
||||
|
||||
#define PCI_CHIP_HEMLOCK_689C 0x689C
|
||||
#define PCI_CHIP_HEMLOCK_689D 0x689D
|
||||
|
||||
enum {
|
||||
CHIP_FAMILY_R100,
|
||||
CHIP_FAMILY_RV100,
|
||||
|
|
@ -438,6 +478,13 @@ enum {
|
|||
CHIP_FAMILY_RV730,
|
||||
CHIP_FAMILY_RV710,
|
||||
CHIP_FAMILY_RV740,
|
||||
|
||||
CHIP_FAMILY_CEDAR,
|
||||
CHIP_FAMILY_REDWOOD,
|
||||
CHIP_FAMILY_JUNIPER,
|
||||
CHIP_FAMILY_CYPRESS,
|
||||
CHIP_FAMILY_HEMLOCK,
|
||||
|
||||
CHIP_FAMILY_LAST
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -244,6 +244,8 @@ struct radeon_tex_obj {
|
|||
GLuint SQ_TEX_RESOURCE5;
|
||||
GLuint SQ_TEX_RESOURCE6;
|
||||
|
||||
GLuint SQ_TEX_RESOURCE7;
|
||||
|
||||
GLuint SQ_TEX_SAMPLER0;
|
||||
GLuint SQ_TEX_SAMPLER1;
|
||||
GLuint SQ_TEX_SAMPLER2;
|
||||
|
|
|
|||
|
|
@ -916,6 +916,61 @@ static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
|
|||
screen->chip_flags = RADEON_CHIPSET_TCL;
|
||||
break;
|
||||
|
||||
case PCI_CHIP_CEDAR_68E0:
|
||||
case PCI_CHIP_CEDAR_68E1:
|
||||
case PCI_CHIP_CEDAR_68E4:
|
||||
case PCI_CHIP_CEDAR_68E5:
|
||||
case PCI_CHIP_CEDAR_68E8:
|
||||
case PCI_CHIP_CEDAR_68E9:
|
||||
case PCI_CHIP_CEDAR_68F1:
|
||||
case PCI_CHIP_CEDAR_68F8:
|
||||
case PCI_CHIP_CEDAR_68F9:
|
||||
case PCI_CHIP_CEDAR_68FE:
|
||||
screen->chip_family = CHIP_FAMILY_CEDAR;
|
||||
screen->chip_flags = RADEON_CHIPSET_TCL;
|
||||
break;
|
||||
|
||||
case PCI_CHIP_REDWOOD_68C0:
|
||||
case PCI_CHIP_REDWOOD_68C1:
|
||||
case PCI_CHIP_REDWOOD_68C8:
|
||||
case PCI_CHIP_REDWOOD_68C9:
|
||||
case PCI_CHIP_REDWOOD_68D8:
|
||||
case PCI_CHIP_REDWOOD_68D9:
|
||||
case PCI_CHIP_REDWOOD_68DA:
|
||||
case PCI_CHIP_REDWOOD_68DE:
|
||||
screen->chip_family = CHIP_FAMILY_REDWOOD;
|
||||
screen->chip_flags = RADEON_CHIPSET_TCL;
|
||||
break;
|
||||
|
||||
case PCI_CHIP_JUNIPER_68A0:
|
||||
case PCI_CHIP_JUNIPER_68A1:
|
||||
case PCI_CHIP_JUNIPER_68A8:
|
||||
case PCI_CHIP_JUNIPER_68A9:
|
||||
case PCI_CHIP_JUNIPER_68B0:
|
||||
case PCI_CHIP_JUNIPER_68B8:
|
||||
case PCI_CHIP_JUNIPER_68B9:
|
||||
case PCI_CHIP_JUNIPER_68BE:
|
||||
screen->chip_family = CHIP_FAMILY_JUNIPER;
|
||||
screen->chip_flags = RADEON_CHIPSET_TCL;
|
||||
break;
|
||||
|
||||
case PCI_CHIP_CYPRESS_6880:
|
||||
case PCI_CHIP_CYPRESS_6888:
|
||||
case PCI_CHIP_CYPRESS_6889:
|
||||
case PCI_CHIP_CYPRESS_688A:
|
||||
case PCI_CHIP_CYPRESS_6898:
|
||||
case PCI_CHIP_CYPRESS_6899:
|
||||
case PCI_CHIP_CYPRESS_689E:
|
||||
screen->chip_family = CHIP_FAMILY_CYPRESS;
|
||||
screen->chip_flags = RADEON_CHIPSET_TCL;
|
||||
break;
|
||||
|
||||
case PCI_CHIP_HEMLOCK_689C:
|
||||
case PCI_CHIP_HEMLOCK_689D:
|
||||
screen->chip_family = CHIP_FAMILY_HEMLOCK;
|
||||
screen->chip_flags = RADEON_CHIPSET_TCL;
|
||||
break;
|
||||
|
||||
default:
|
||||
fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
|
||||
device_id);
|
||||
|
|
@ -1116,7 +1171,7 @@ radeonCreateScreen( __DRIscreen *sPriv )
|
|||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
{
|
||||
screen->fbLocation = (temp & 0xffff) << 16;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue