parent
87f44d5723
commit
0e6a02d299
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@ -1494,6 +1494,129 @@ static int tgsi_cmp(struct r600_shader_ctx *ctx)
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return 0;
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}
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static int tgsi_xpd(struct r600_shader_ctx *ctx)
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{
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struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
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struct r600_bc_alu_src r600_src[3];
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struct r600_bc_alu alu;
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uint32_t use_temp = 0;
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int i, r;
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if (inst->Dst[0].Register.WriteMask != 0xf)
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use_temp = 1;
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r = tgsi_split_constant(ctx, r600_src);
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if (r)
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return r;
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for (i = 0; i < 4; i++) {
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memset(&alu, 0, sizeof(struct r600_bc_alu));
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alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
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alu.src[0] = r600_src[0];
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switch (i) {
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case 0:
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alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
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break;
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case 1:
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alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
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break;
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case 2:
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alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
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break;
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case 3:
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alu.src[0].sel = V_SQ_ALU_SRC_0;
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alu.src[0].chan = i;
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}
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alu.src[1] = r600_src[1];
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switch (i) {
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case 0:
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alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
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break;
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case 1:
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alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
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break;
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case 2:
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alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
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break;
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case 3:
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alu.src[1].sel = V_SQ_ALU_SRC_0;
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alu.src[1].chan = i;
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}
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alu.dst.sel = ctx->temp_reg;
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alu.dst.chan = i;
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alu.dst.write = 1;
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if (i == 3)
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alu.last = 1;
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r = r600_bc_add_alu(ctx->bc, &alu);
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if (r)
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return r;
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}
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for (i = 0; i < 4; i++) {
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memset(&alu, 0, sizeof(struct r600_bc_alu));
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alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD;
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alu.src[0] = r600_src[0];
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switch (i) {
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case 0:
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alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
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break;
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case 1:
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alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
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break;
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case 2:
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alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
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break;
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case 3:
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alu.src[0].sel = V_SQ_ALU_SRC_0;
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alu.src[0].chan = i;
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}
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alu.src[1] = r600_src[1];
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switch (i) {
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case 0:
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alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
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break;
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case 1:
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alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
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break;
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case 2:
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alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
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break;
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case 3:
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alu.src[1].sel = V_SQ_ALU_SRC_0;
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alu.src[1].chan = i;
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}
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alu.src[2].sel = ctx->temp_reg;
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alu.src[2].neg = 1;
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alu.src[2].chan = i;
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if (use_temp)
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alu.dst.sel = ctx->temp_reg;
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else {
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r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
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if (r)
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return r;
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}
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alu.dst.chan = i;
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alu.dst.write = 1;
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alu.is_op3 = 1;
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if (i == 3)
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alu.last = 1;
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r = r600_bc_add_alu(ctx->bc, &alu);
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if (r)
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return r;
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}
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if (use_temp)
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return tgsi_helper_copy(ctx, inst);
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return 0;
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}
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static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
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{TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
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@ -1529,7 +1652,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
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{TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
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{TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
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{TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
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{TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
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{TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
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/* gap */
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{32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
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{TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
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