intel/ir/gen12: Add SYNC hardware instruction.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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@ -467,6 +467,7 @@ enum gen {
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static const struct opcode_desc opcode_descs[] = {
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static const struct opcode_desc opcode_descs[] = {
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/* IR, HW, name, nsrc, ndst, gens */
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/* IR, HW, name, nsrc, ndst, gens */
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{ BRW_OPCODE_ILLEGAL, 0, "illegal", 0, 0, GEN_ALL },
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{ BRW_OPCODE_ILLEGAL, 0, "illegal", 0, 0, GEN_ALL },
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{ BRW_OPCODE_SYNC, 1, "sync", 1, 0, GEN_GE(GEN12) },
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{ BRW_OPCODE_MOV, 1, "mov", 1, 1, GEN_LT(GEN12) },
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{ BRW_OPCODE_MOV, 1, "mov", 1, 1, GEN_LT(GEN12) },
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{ BRW_OPCODE_MOV, 97, "mov", 1, 1, GEN_GE(GEN12) },
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{ BRW_OPCODE_MOV, 97, "mov", 1, 1, GEN_GE(GEN12) },
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{ BRW_OPCODE_SEL, 2, "sel", 2, 1, GEN_LT(GEN12) },
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{ BRW_OPCODE_SEL, 2, "sel", 2, 1, GEN_LT(GEN12) },
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@ -197,6 +197,7 @@ enum PACKED gen10_align1_3src_dst_horizontal_stride {
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enum opcode {
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enum opcode {
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/* These are the actual hardware instructions. */
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/* These are the actual hardware instructions. */
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BRW_OPCODE_ILLEGAL,
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BRW_OPCODE_ILLEGAL,
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BRW_OPCODE_SYNC,
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BRW_OPCODE_MOV,
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BRW_OPCODE_MOV,
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BRW_OPCODE_SEL,
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BRW_OPCODE_SEL,
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BRW_OPCODE_MOVI, /**< G45+ */
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BRW_OPCODE_MOVI, /**< G45+ */
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@ -1042,6 +1042,7 @@ backend_instruction::has_side_effects() const
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case SHADER_OPCODE_SEND:
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case SHADER_OPCODE_SEND:
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return send_has_side_effects;
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return send_has_side_effects;
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case BRW_OPCODE_SYNC:
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case VEC4_OPCODE_UNTYPED_ATOMIC:
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case VEC4_OPCODE_UNTYPED_ATOMIC:
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case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
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case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
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case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
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case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
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